2016.3" PB_VioResults_ 1.2$ngFEC_top_methodology_drc_routed.rpxh)px)Methodology Checks Results Critical Warning"TIMING-2* Invalid primary clock source pin2 TIMING-2#18BA primary clock DRPclk is created on an inappropriate pin i_DRPclk_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc)JA primary clock DRPclk is created on an inappropriate pin i_DRPclk_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) O * i_DRPclk_bufg Critical Warning"TIMING-2* Invalid primary clock source pin2 TIMING-2#28BA primary clock clk125 is created on an inappropriate pin i_clk125_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc)JA primary clock clk125 is created on an inappropriate pin i_clk125_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) O * i_clk125_bufg Critical Warning"TIMING-2* Invalid primary clock source pin2 TIMING-2#38BA primary clock clk250 is created on an inappropriate pin i_clk250_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc)JA primary clock clk250 is created on an inappropriate pin i_clk250_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) O * i_clk250_bufgCritical Warning"TIMING-2* Invalid primary clock source pin2 TIMING-2#48BA primary clock fabric_clk is created on an inappropriate pin fabric_clk_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc)JA primary clock fabric_clk is created on an inappropriate pin fabric_clk_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) O *fabric_clk_bufgCritical Warning"TIMING-2* Invalid primary clock source pin2 TIMING-2#58BA primary clock ipb_clk is created on an inappropriate pin i_ipb_clk_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc)JA primary clock ipb_clk is created on an inappropriate pin i_ipb_clk_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) O *i_ipb_clk_bufgCritical Warning"TIMING-2* Invalid primary clock source pin2 TIMING-2#68BA primary clock tx_wordclk is created on an inappropriate pin tx_wordclk_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc)JA primary clock tx_wordclk is created on an inappropriate pin tx_wordclk_bufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) O *tx_wordclk_bufgCritical Warning"TIMING-3*.Invalid primary clock on Clock Modifying Block2 TIMING-3#18BA primary clock TTC_rxusrclk is created on the output pin or net i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O of a Clock Modifying BlockJA primary clock TTC_rxusrclk is created on the output pin or net i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O of a Clock Modifying Block= ;O 9*-gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_instCritical Warning"TIMING-4*2Invalid primary clock redefinition on a clock tree2 TIMING-4#18BInvalid clock redefinition on a clock tree. The primary clock DRPclk is defined downstream of clock DRPclk_dcm and overrides its insertion delay and/or waveform definitionJInvalid clock redefinition on a clock tree. The primary clock DRPclk is defined downstream of clock DRPclk_dcm and overrides its insertion delay and/or waveform definitionCritical Warning"TIMING-4*2Invalid primary clock redefinition on a clock tree2 TIMING-4#28BInvalid clock redefinition on a clock tree. The primary clock clk125 is defined downstream of clock clk125_dcm and overrides its insertion delay and/or waveform definitionJInvalid clock redefinition on a clock tree. The primary clock clk125 is defined downstream of clock clk125_dcm and overrides its insertion delay and/or waveform definitionCritical Warning"TIMING-4*2Invalid primary clock redefinition on a clock tree2 TIMING-4#38BInvalid clock redefinition on a clock tree. The primary clock clk250 is defined downstream of clock clk250_dcm and overrides its insertion delay and/or waveform definitionJInvalid clock redefinition on a clock tree. The primary clock clk250 is defined downstream of clock clk250_dcm and overrides its insertion delay and/or waveform definitionCritical Warning"TIMING-4*2Invalid primary clock redefinition on a clock tree2 TIMING-4#48BInvalid clock redefinition on a clock tree. The primary clock fabric_clk is defined downstream of clock fabric_clk_dcm and overrides its insertion delay and/or waveform definitionJInvalid clock redefinition on a clock tree. The primary clock fabric_clk is defined downstream of clock fabric_clk_dcm and overrides its insertion delay and/or waveform definitionCritical Warning"TIMING-4*2Invalid primary clock redefinition on a clock tree2 TIMING-4#58BInvalid clock redefinition on a clock tree. The primary clock ipb_clk is defined downstream of clock ipb_clk_dcm and overrides its insertion delay and/or waveform definitionJInvalid clock redefinition on a clock tree. The primary clock ipb_clk is defined downstream of clock ipb_clk_dcm and overrides its insertion delay and/or waveform definitionCritical Warning"TIMING-4*2Invalid primary clock redefinition on a clock tree2 TIMING-4#68BInvalid clock redefinition on a clock tree. The primary clock tx_wordclk is defined downstream of clock tx_wordclk_dcm and overrides its insertion delay and/or waveform definitionJInvalid clock redefinition on a clock tree. The primary clock tx_wordclk is defined downstream of clock tx_wordclk_dcm and overrides its insertion delay and/or waveform definition|Critical Warning"TIMING-6*.No common primary clock between related clocks2 TIMING-6#18BThe clocks clk250 and ipb_clk are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk250] -to [get_clocks ipb_clk]JThe clocks clk250 and ipb_clk are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk250] -to [get_clocks ipb_clk]Critical Warning"TIMING-6*.No common primary clock between related clocks2 TIMING-6#28BThe clocks fabric_clk and tx_wordclk are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks fabric_clk] -to [get_clocks tx_wordclk]JThe clocks fabric_clk and tx_wordclk are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks fabric_clk] -to [get_clocks tx_wordclk]|Critical Warning"TIMING-6*.No common primary clock between related clocks2 TIMING-6#38BThe clocks ipb_clk and clk250 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks ipb_clk] -to [get_clocks clk250]JThe clocks ipb_clk and clk250 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks ipb_clk] -to [get_clocks clk250]aCritical Warning"TIMING-7*%No common node between related clocks2 TIMING-7#18BThe clocks clk250 and ipb_clk are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk250] -to [get_clocks ipb_clk]JThe clocks clk250 and ipb_clk are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk250] -to [get_clocks ipb_clk]}Critical Warning"TIMING-7*%No common node between related clocks2 TIMING-7#28BThe clocks fabric_clk and tx_wordclk are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks fabric_clk] -to [get_clocks tx_wordclk]JThe clocks fabric_clk and tx_wordclk are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks fabric_clk] -to [get_clocks tx_wordclk]aCritical Warning"TIMING-7*%No common node between related clocks2 TIMING-7#38BThe clocks ipb_clk and clk250 are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks ipb_clk] -to [get_clocks clk250]JThe clocks ipb_clk and clk250 are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks ipb_clk] -to [get_clocks clk250]Warning"AVAL-324*Hard_blocks_needs_LOCs2 AVAL-324#18BThe hard block GTHE3_COMMON cell i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST is missing a valid LOC constraint for placement assignment, normally supplied by IP generation or manually assigned using the LOC property. Unguided placement of this block may cause problems in routing. Please set a valid LOC for this block to avoid these problem.JThe hard block GTHE3_COMMON cell i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_common.gen_common_container[24].gen_enabled_common.gthe3_common_wrapper_inst/common_inst/gthe3_common_gen.GTHE3_COMMON_PRIM_INST is missing a valid LOC constraint for placement assignment, normally supplied by IP generation or manually assigned using the LOC property. Unguided placement of this block may cause problems in routing. Please set a valid LOC for this block to avoid these problem. GTHE3_COMMON5 3='gthe3_common_gen.GTHE3_COMMON_PRIM_INST *|Warning"DPIR-2*Asynchronous driver check2DPIR-2#18BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2DPIR-2#28BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2DPIR-2#38BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2DPIR-2#48BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2DPIR-2#58BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst|Warning"DPIR-2*Asynchronous driver check2DPIR-2#68BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst|Warning"DPIR-2*Asynchronous driver check2DPIR-2#78BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst|Warning"DPIR-2*Asynchronous driver check2DPIR-2#88BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst| Warning"DPIR-2*Asynchronous driver check2DPIR-2#98BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst} Warning"DPIR-2*Asynchronous driver check2 DPIR-2#108BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst} Warning"DPIR-2*Asynchronous driver check2 DPIR-2#118BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst} Warning"DPIR-2*Asynchronous driver check2 DPIR-2#128BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst} Warning"DPIR-2*Asynchronous driver check2 DPIR-2#138BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst}Warning"DPIR-2*Asynchronous driver check2 DPIR-2#148BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst}Warning"DPIR-2*Asynchronous driver check2 DPIR-2#158BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#168BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#178BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#188BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#198BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#208BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#218BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#228BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#238BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst}Warning"DPIR-2*Asynchronous driver check2 DPIR-2#248BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst}Warning"DPIR-2*Asynchronous driver check2 DPIR-2#258BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst}Warning"DPIR-2*Asynchronous driver check2 DPIR-2#268BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst}Warning"DPIR-2*Asynchronous driver check2 DPIR-2#278BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst}Warning"DPIR-2*Asynchronous driver check2 DPIR-2#288BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst}Warning"DPIR-2*Asynchronous driver check2 DPIR-2#298BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst}Warning"DPIR-2*Asynchronous driver check2 DPIR-2#308BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst}Warning"DPIR-2*Asynchronous driver check2 DPIR-2#318BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst} Warning"DPIR-2*Asynchronous driver check2 DPIR-2#328BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst}!Warning"DPIR-2*Asynchronous driver check2 DPIR-2#338BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst"Warning"DPIR-2*Asynchronous driver check2 DPIR-2#348BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst#Warning"DPIR-2*Asynchronous driver check2 DPIR-2#358BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst$Warning"DPIR-2*Asynchronous driver check2 DPIR-2#368BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst%Warning"DPIR-2*Asynchronous driver check2 DPIR-2#378BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst&Warning"DPIR-2*Asynchronous driver check2 DPIR-2#388BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst'Warning"DPIR-2*Asynchronous driver check2 DPIR-2#398BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst(Warning"DPIR-2*Asynchronous driver check2 DPIR-2#408BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst)Warning"DPIR-2*Asynchronous driver check2 DPIR-2#418BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst*Warning"DPIR-2*Asynchronous driver check2 DPIR-2#428BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst+Warning"DPIR-2*Asynchronous driver check2 DPIR-2#438BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst},Warning"DPIR-2*Asynchronous driver check2 DPIR-2#448BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst-Warning"DPIR-2*Asynchronous driver check2 DPIR-2#458BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst.Warning"DPIR-2*Asynchronous driver check2 DPIR-2#468BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst/Warning"DPIR-2*Asynchronous driver check2 DPIR-2#478BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst0Warning"DPIR-2*Asynchronous driver check2 DPIR-2#488BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst1Warning"DPIR-2*Asynchronous driver check2 DPIR-2#498BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst2Warning"DPIR-2*Asynchronous driver check2 DPIR-2#508BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst3Warning"DPIR-2*Asynchronous driver check2 DPIR-2#518BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst4Warning"DPIR-2*Asynchronous driver check2 DPIR-2#528BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst5Warning"DPIR-2*Asynchronous driver check2 DPIR-2#538BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst6Warning"DPIR-2*Asynchronous driver check2 DPIR-2#548BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst}7Warning"DPIR-2*Asynchronous driver check2 DPIR-2#558BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst8Warning"DPIR-2*Asynchronous driver check2 DPIR-2#568BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst9Warning"DPIR-2*Asynchronous driver check2 DPIR-2#578BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst}:Warning"DPIR-2*Asynchronous driver check2 DPIR-2#588BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst};Warning"DPIR-2*Asynchronous driver check2 DPIR-2#598BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst}<Warning"DPIR-2*Asynchronous driver check2 DPIR-2#608BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst}=Warning"DPIR-2*Asynchronous driver check2 DPIR-2#618BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst}>Warning"DPIR-2*Asynchronous driver check2 DPIR-2#628BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst}?Warning"DPIR-2*Asynchronous driver check2 DPIR-2#638BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst}@Warning"DPIR-2*Asynchronous driver check2 DPIR-2#648BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst}AWarning"DPIR-2*Asynchronous driver check2 DPIR-2#658BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instBWarning"DPIR-2*Asynchronous driver check2 DPIR-2#668BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instCWarning"DPIR-2*Asynchronous driver check2 DPIR-2#678BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instDWarning"DPIR-2*Asynchronous driver check2 DPIR-2#688BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instEWarning"DPIR-2*Asynchronous driver check2 DPIR-2#698BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst}FWarning"DPIR-2*Asynchronous driver check2 DPIR-2#708BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst}GWarning"DPIR-2*Asynchronous driver check2 DPIR-2#718BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst}HWarning"DPIR-2*Asynchronous driver check2 DPIR-2#728BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst}IWarning"DPIR-2*Asynchronous driver check2 DPIR-2#738BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst}JWarning"DPIR-2*Asynchronous driver check2 DPIR-2#748BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst}KWarning"DPIR-2*Asynchronous driver check2 DPIR-2#758BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst}LWarning"DPIR-2*Asynchronous driver check2 DPIR-2#768BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst}MWarning"DPIR-2*Asynchronous driver check2 DPIR-2#778BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst}NWarning"DPIR-2*Asynchronous driver check2 DPIR-2#788BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst}OWarning"DPIR-2*Asynchronous driver check2 DPIR-2#798BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instPWarning"DPIR-2*Asynchronous driver check2 DPIR-2#808BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instQWarning"DPIR-2*Asynchronous driver check2 DPIR-2#818BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instRWarning"DPIR-2*Asynchronous driver check2 DPIR-2#828BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instSWarning"DPIR-2*Asynchronous driver check2 DPIR-2#838BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instTWarning"DPIR-2*Asynchronous driver check2 DPIR-2#848BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instUWarning"DPIR-2*Asynchronous driver check2 DPIR-2#858BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instVWarning"DPIR-2*Asynchronous driver check2 DPIR-2#868BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWWarning"DPIR-2*Asynchronous driver check2 DPIR-2#878BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst}XWarning"DPIR-2*Asynchronous driver check2 DPIR-2#888BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst}YWarning"DPIR-2*Asynchronous driver check2 DPIR-2#898BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst}ZWarning"DPIR-2*Asynchronous driver check2 DPIR-2#908BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst}[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#918BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst}\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#928BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst}]Warning"DPIR-2*Asynchronous driver check2 DPIR-2#938BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst}^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#948BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst}_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#958BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst}`Warning"DPIR-2*Asynchronous driver check2 DPIR-2#968BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst}aWarning"DPIR-2*Asynchronous driver check2 DPIR-2#978BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#988BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#998BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instdWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1008BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_insteWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1018BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instfWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1028BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instgWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1038BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_insthWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1048BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instiWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1058BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instjWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1068BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instkWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1078BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst~lWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1088BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instmWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1098BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instnWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1108BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instoWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1118BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instpWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1128BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instqWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1138BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instrWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1148BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instsWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1158BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_insttWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1168BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instuWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1178BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instvWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1188BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst~wWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1198BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instxWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1208BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instyWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1218BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst~zWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1228BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst~{Warning"DPIR-2*Asynchronous driver check2 DPIR-2#1238BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst~|Warning"DPIR-2*Asynchronous driver check2 DPIR-2#1248BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst~}Warning"DPIR-2*Asynchronous driver check2 DPIR-2#1258BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst~~Warning"DPIR-2*Asynchronous driver check2 DPIR-2#1268BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst~Warning"DPIR-2*Asynchronous driver check2 DPIR-2#1278BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1288BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1298BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1308BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1318BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1328BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1338BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1348BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1358BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1368BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1378BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1388BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1398BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1408BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1418BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1428BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1438BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1448BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1458BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1468BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1478BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1488BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1498BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1508BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1518BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1528BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1538BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1548BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1558BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1568BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1578BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1588BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1598BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1608BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1618BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1628BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1638BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1648BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1658BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1668BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1678BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1688BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1698BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1708BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1718BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1728BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1738BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1748BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1758BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1768BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1778BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1788BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1798BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1808BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1818BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1828BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1838BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1848BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1858BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1868BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1878BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1888BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1898BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1908BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1918BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#1928BDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#1938BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#1948BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#1958BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#1968BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#1978BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#1988BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#1998BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2008BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2018BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2028BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2038BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2048BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2058BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2068BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2078BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2088BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2098BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2108BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2118BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2128BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2138BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2148BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2158BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2168BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2178BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2188BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2198BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2208BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2218BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2228BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2238BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2248BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2258BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2268BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2278BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2288BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2298BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2308BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2318BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2328BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2338BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2348BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2358BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2368BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2378BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2388BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2398BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2408BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2418BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2428BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2438BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2448BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2458BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2468BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2478BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2488BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst^Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2498BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2508BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2518BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2528BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2538BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2548BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2558BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst[Warning"DPIR-2*Asynchronous driver check2 DPIR-2#2568BDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[0].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2578BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2588BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2598BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2608BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2618BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2628BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2638BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2648BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2658BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2668BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2678BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2688BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2698BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2708BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2718BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2728BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2738BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2748BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2758BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2768BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2778BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2788BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2798BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2808BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2818BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2828BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2838BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2848BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2858BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2868BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2878BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2888BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2898BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2908BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2918BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2928BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2938BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2948BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2958BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2968BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2978BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2988BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#2998BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3008BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3018BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3028BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3038BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3048BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3058BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3068BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3078BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3088BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3098BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3108BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3118BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3128BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3138BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3148BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3158BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3168BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3178BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3188BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3198BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3208BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3218BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3228BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3238BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3248BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3258BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3268BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3278BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3288BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3298BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3308BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3318BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3328BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3338BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3348BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3358BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3368BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3378BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3388BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3398BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3408BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3418BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3428BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3438BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3448BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3458BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3468BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3478BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3488BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3498BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3508BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3518BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3528BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3538BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3548BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3558BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3568BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3578BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3588BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3598BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3608BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3618BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3628BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3638BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3648BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3658BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3668BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3678BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3688BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3698BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3708BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3718BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3728BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3738BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3748BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3758BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3768BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3778BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3788BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3798BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3808BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3818BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3828BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3838BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3848BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3858BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3868BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3878BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3888BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3898BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3908BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3918BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3928BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3938BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3948BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3958BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3968BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3978BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3988BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#3998BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4008BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4018BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4028BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4038BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4048BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4058BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4068BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4078BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4088BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4098BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4108BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4118BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4128BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4138BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4148BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4158BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4168BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4178BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4188BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4198BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4208BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4218BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4228BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4238BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4248BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4258BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4268BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4278BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4288BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4298BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4308BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4318BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4328BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4338BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4348BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4358BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4368BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4378BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4388BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4398BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4408BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4418BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4428BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4438BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4448BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4458BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4468BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4478BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4488BDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4498BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4508BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4518BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4528BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4538BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4548BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4558BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4568BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4578BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4588BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4598BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4608BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4618BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4628BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4638BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4648BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4658BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4668BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4678BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4688BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4698BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4708BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4718BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4728BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4738BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4748BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4758BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4768BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4778BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4788BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4798BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4808BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4818BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4828BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4838BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4848BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4858BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4868BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4878BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4888BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4898BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4908BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4918BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#4928BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4938BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4948BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4958BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4968BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4978BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4988BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#4998BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5008BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5018BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5028BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#5038BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5048BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5058BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#5068BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#5078BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#5088BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#5098BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#5108BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#5118BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#5128BDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[10].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5138BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5148BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5158BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5168BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5178BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5188BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5198BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5208BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5218BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5228BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5238BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5248BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5258BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5268BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5278BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5288BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5298BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5308BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5318BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5328BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5338BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5348BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5358BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5368BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5378BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5388BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5398BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5408BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5418BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5428BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5438BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5448BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5458BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5468BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5478BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5488BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5498BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5508BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5518BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5528BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5538BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5548BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5558BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5568BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5578BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5588BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5598BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5608BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5618BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5628BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5638BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5648BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5658BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5668BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5678BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5688BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5698BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5708BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5718BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5728BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5738BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5748BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5758BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5768BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5778BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5788BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5798BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5808BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5818BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5828BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5838BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5848BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5858BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5868BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5878BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5888BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5898BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5908BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5918BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5928BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5938BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5948BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5958BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5968BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5978BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5988BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#5998BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6008BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6018BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6028BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6038BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6048BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6058BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6068BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6078BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6088BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6098BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6108BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6118BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6128BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6138BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6148BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6158BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6168BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6178BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6188BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6198BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6208BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6218BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6228BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6238BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6248BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6258BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6268BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6278BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6288BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6298BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6308BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6318BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6328BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6338BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6348BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6358BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6368BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6378BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6388BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6398BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6408BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6418BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6428BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6438BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6448BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6458BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6468BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6478BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6488BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6498BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6508BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6518BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6528BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6538BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6548BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6558BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6568BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6578BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6588BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6598BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6608BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6618BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6628BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6638BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6648BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6658BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6668BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6678BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6688BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6698BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6708BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6718BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6728BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6738BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6748BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6758BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6768BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6778BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6788BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6798BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6808BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6818BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6828BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6838BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6848BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6858BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6868BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6878BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6888BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6898BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6908BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6918BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6928BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6938BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6948BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6958BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6968BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6978BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6988BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#6998BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7008BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7018BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7028BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7038BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7048BDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7058BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7068BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7078BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7088BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7098BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7108BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7118BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7128BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7138BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7148BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7158BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7168BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7178BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7188BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7198BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7208BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7218BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7228BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7238BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7248BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7258BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7268BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7278BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7288BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7298BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7308BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7318BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7328BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7338BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7348BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7358BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7368BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7378BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7388BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7398BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7408BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7418BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7428BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7438BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7448BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7458BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7468BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7478BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7488BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7498BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7508BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7518BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7528BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7538BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7548BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7558BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7568BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7578BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7588BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7598BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7608BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7618BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7628BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7638BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7648BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7658BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7668BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7678BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#7688BDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[11].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7698BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7708BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7718BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7728BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7738BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7748BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7758BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7768BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7778BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7788BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7798BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7808BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7818BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7828BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7838BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7848BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7858BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7868BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7878BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7888BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7898BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7908BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7918BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7928BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7938BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7948BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7958BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7968BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7978BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7988BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#7998BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8008BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8018BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8028BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8038BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8048BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8058BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8068BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8078BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8088BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8098BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8108BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8118BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8128BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8138BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8148BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8158BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8168BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8178BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8188BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8198BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8208BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8218BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8228BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8238BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8248BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8258BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8268BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8278BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8288BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8298BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8308BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8318BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8328BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8338BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8348BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8358BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8368BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8378BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8388BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8398BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8408BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8418BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8428BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8438BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8448BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8458BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8468BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8478BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8488BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8498BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8508BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8518BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8528BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8538BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8548BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8558BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8568BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8578BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8588BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8598BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8608BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8618BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8628BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8638BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8648BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8658BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8668BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8678BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8688BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8698BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8708BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8718BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8728BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8738BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8748BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8758BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8768BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8778BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8788BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8798BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8808BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8818BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8828BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8838BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8848BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8858BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8868BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8878BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8888BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8898BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8908BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8918BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8928BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8938BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8948BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8958BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8968BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8978BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8988BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#8998BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9008BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9018BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9028BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9038BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9048BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9058BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9068BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9078BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9088BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9098BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9108BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9118BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9128BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9138BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9148BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9158BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9168BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9178BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9188BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9198BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9208BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9218BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9228BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9238BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9248BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9258BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9268BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9278BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9288BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9298BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9308BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9318BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9328BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9338BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9348BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9358BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9368BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9378BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9388BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9398BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9408BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9418BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9428BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9438BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9448BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9458BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9468BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9478BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9488BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9498BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9508BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9518BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9528BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9538BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9548BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9558BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9568BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9578BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9588BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9598BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9608BDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9618BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9628BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9638BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9648BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9658BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9668BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9678BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9688BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9698BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9708BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9718BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9728BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9738BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9748BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9758BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9768BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9778BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9788BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9798BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9808BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9818BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9828BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9838BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9848BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9858BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9868BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9878BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9888BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9898BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9908BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9918BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9928BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#9938BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9948BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9958BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9968BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9978BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9988BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instbWarning"DPIR-2*Asynchronous driver check2 DPIR-2#9998BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10008BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10018BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10028BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10038BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst`Warning"DPIR-2*Asynchronous driver check2 DPIR-2#10048BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10058BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10068BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10078BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10088BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10098BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10108BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10118BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10128BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10138BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10148BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst`Warning"DPIR-2*Asynchronous driver check2 DPIR-2#10158BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10168BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instcWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10178BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst`Warning"DPIR-2*Asynchronous driver check2 DPIR-2#10188BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst`Warning"DPIR-2*Asynchronous driver check2 DPIR-2#10198BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst`Warning"DPIR-2*Asynchronous driver check2 DPIR-2#10208BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst`Warning"DPIR-2*Asynchronous driver check2 DPIR-2#10218BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst`Warning"DPIR-2*Asynchronous driver check2 DPIR-2#10228BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst`Warning"DPIR-2*Asynchronous driver check2 DPIR-2#10238BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst`Warning"DPIR-2*Asynchronous driver check2 DPIR-2#10248BDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[12].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10258BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10268BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10278BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10288BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10298BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10308BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10318BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10328BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10338BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10348BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10358BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10368BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10378BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10388BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10398BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10408BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10418BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10428BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10438BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10448BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10458BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10468BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10478BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10488BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10498BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10508BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10518BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10528BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10538BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10548BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10558BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10568BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10578BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10588BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10598BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10608BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10618BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10628BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10638BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10648BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10658BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10668BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10678BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10688BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10698BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10708BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10718BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10728BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10738BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10748BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10758BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10768BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10778BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10788BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10798BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10808BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10818BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10828BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10838BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10848BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10858BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10868BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10878BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10888BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10898BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10908BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10918BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10928BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10938BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10948BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10958BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10968BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10978BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10988BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#10998BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11008BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11018BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11028BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11038BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11048BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11058BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11068BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11078BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11088BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11098BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11108BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11118BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11128BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11138BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11148BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11158BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11168BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11178BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11188BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11198BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11208BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11218BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11228BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11238BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11248BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11258BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11268BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11278BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11288BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11298BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11308BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11318BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11328BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11338BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11348BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11358BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11368BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11378BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11388BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11398BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11408BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11418BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11428BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11438BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11448BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11458BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11468BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11478BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11488BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11498BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11508BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#11518BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11528BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11538BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11548BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11558BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11568BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11578BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11588BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11598BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11608BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11618BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11628BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11638BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11648BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11658BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11668BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11678BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11688BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11698BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11708BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11718BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11728BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11738BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11748BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11758BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11768BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11778BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11788BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11798BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11808BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11818BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11828BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11838BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11848BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11858BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11868BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11878BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11888BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11898BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11908BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11918BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11928BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11938BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11948BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11958BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11968BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11978BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11988BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#11998BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12008BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12018BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12028BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12038BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12048BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12058BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12068BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12078BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12088BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12098BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12108BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12118BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12128BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12138BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12148BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12158BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12168BDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12178BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12188BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12198BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12208BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12218BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12228BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12238BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12248BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12258BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12268BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12278BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12288BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12298BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12308BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12318BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12328BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12338BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12348BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12358BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12368BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12378BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12388BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12398BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12408BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12418BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12428BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12438BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12448BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12458BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12468BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12478BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12488BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12498BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12508BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12518BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12528BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12538BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12548BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12558BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12568BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12578BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12588BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12598BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12608BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12618BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12628BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12638BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12648BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12658BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12668BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12678BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12688BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12698BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12708BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12718BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12728BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12738BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12748BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12758BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12768BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12778BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12788BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12798BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12808BDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[13].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12818BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12828BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12838BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12848BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12858BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12868BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12878BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12888BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12898BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12908BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12918BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12928BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12938BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12948BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12958BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12968BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12978BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12988BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#12998BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13008BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13018BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13028BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13038BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13048BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13058BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13068BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13078BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13088BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13098BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13108BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13118BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13128BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13138BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13148BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13158BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13168BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13178BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13188BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13198BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13208BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13218BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13228BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13238BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13248BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13258BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13268BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13278BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13288BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13298BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13308BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13318BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13328BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13338BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13348BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13358BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13368BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13378BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13388BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13398BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13408BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13418BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13428BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13438BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13448BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13458BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13468BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13478BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13488BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13498BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13508BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13518BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13528BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13538BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13548BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13558BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13568BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13578BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13588BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13598BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13608BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13618BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13628BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13638BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13648BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13658BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13668BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13678BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13688BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13698BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13708BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13718BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13728BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13738BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13748BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13758BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13768BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13778BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13788BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13798BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13808BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13818BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13828BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13838BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13848BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13858BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13868BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13878BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13888BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13898BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13908BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13918BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13928BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13938BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13948BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13958BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13968BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13978BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13988BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#13998BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14008BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14018BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14028BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14038BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14048BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14058BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14068BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14078BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14088BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14098BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14108BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14118BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14128BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14138BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14148BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14158BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14168BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14178BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14188BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14198BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14208BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14218BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14228BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14238BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14248BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14258BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14268BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14278BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14288BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14298BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14308BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14318BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14328BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14338BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14348BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14358BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14368BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14378BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14388BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14398BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14408BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14418BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14428BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14438BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14448BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14458BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14468BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14478BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14488BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14498BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14508BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14518BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14528BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14538BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14548BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14558BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14568BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14578BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14588BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14598BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14608BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14618BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14628BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14638BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14648BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14658BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14668BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14678BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14688BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14698BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14708BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14718BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14728BDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14738BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14748BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14758BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14768BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14778BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14788BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14798BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14808BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14818BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14828BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14838BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14848BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14858BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14868BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14878BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14888BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14898BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14908BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14918BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14928BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14938BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14948BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14958BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14968BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14978BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14988BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#14998BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15008BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15018BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15028BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15038BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15048BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15058BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15068BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15078BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15088BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15098BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15108BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15118BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15128BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15138BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15148BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15158BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15168BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15178BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15188BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15198BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15208BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15218BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15228BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15238BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15248BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15258BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15268BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15278BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15288BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15298BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15308BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15318BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15328BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15338BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15348BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15358BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15368BDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[14].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15378BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15388BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15398BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15408BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15418BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15428BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15438BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15448BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15458BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15468BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15478BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15488BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15498BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15508BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15518BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15528BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15538BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15548BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15558BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15568BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15578BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15588BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15598BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15608BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15618BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15628BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15638BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15648BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15658BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15668BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15678BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15688BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15698BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15708BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15718BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15728BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15738BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15748BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15758BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15768BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15778BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15788BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15798BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15808BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15818BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15828BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15838BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15848BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15858BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15868BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15878BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15888BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15898BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15908BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15918BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15928BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15938BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15948BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15958BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15968BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15978BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15988BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#15998BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16008BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16018BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16028BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16038BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16048BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16058BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16068BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16078BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16088BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16098BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16108BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16118BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16128BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16138BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16148BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16158BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16168BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16178BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16188BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16198BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16208BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16218BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16228BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16238BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16248BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16258BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16268BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16278BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16288BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16298BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16308BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16318BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16328BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16338BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16348BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16358BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16368BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16378BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16388BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16398BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16408BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16418BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16428BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16438BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16448BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16458BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16468BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16478BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16488BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16498BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16508BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16518BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16528BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16538BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16548BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16558BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16568BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16578BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16588BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16598BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16608BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16618BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16628BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16638BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16648BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16658BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16668BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16678BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16688BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16698BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16708BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16718BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16728BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16738BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16748BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16758BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16768BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16778BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16788BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16798BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16808BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16818BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16828BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16838BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16848BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16858BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16868BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16878BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16888BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16898BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16908BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16918BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16928BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16938BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16948BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16958BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16968BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16978BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16988BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#16998BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17008BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17018BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17028BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17038BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17048BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17058BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17068BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17078BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17088BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17098BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17108BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17118BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17128BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17138BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17148BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17158BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17168BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17178BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17188BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17198BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17208BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17218BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17228BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17238BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17248BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17258BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17268BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17278BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17288BDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17298BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17308BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17318BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17328BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17338BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17348BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17358BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17368BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17378BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17388BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17398BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17408BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17418BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17428BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17438BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17448BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17458BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17468BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17478BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17488BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17498BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17508BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17518BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17528BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17538BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17548BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17558BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17568BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17578BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17588BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17598BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17608BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17618BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17628BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17638BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17648BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17658BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17668BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17678BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17688BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17698BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17708BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17718BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17728BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17738BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17748BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17758BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17768BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17778BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17788BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17798BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17808BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17818BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17828BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17838BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17848BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instc Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17858BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17868BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17878BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17888BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17898BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17908BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst` Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17918BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst`Warning"DPIR-2*Asynchronous driver check2 DPIR-2#17928BDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[15].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#17938BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#17948BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#17958BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#17968BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#17978BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#17988BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#17998BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18008BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18018BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18028BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18038BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18048BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18058BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18068BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18078BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18088BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18098BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18108BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18118BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18128BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18138BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18148BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18158BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18168BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18178BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18188BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18198BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18208BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18218BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18228BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18238BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18248BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18258BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18268BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18278BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18288BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18298BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18308BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18318BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18328BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18338BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18348BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18358BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18368BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18378BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18388BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18398BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18408BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18418BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18428BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18438BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18448BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18458BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18468BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18478BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18488BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18498BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18508BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18518BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18528BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18538BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18548BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18558BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18568BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18578BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18588BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18598BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18608BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18618BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18628BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18638BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18648BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18658BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18668BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18678BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18688BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18698BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18708BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18718BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18728BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18738BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18748BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18758BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18768BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18778BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18788BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18798BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18808BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18818BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18828BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18838BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18848BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18858BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18868BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18878BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18888BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18898BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18908BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18918BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18928BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18938BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18948BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18958BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18968BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18978BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18988BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#18998BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19008BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19018BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19028BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19038BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19048BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19058BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19068BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19078BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19088BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19098BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19108BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19118BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19128BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19138BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19148BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19158BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19168BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19178BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19188BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19198BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19208BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19218BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19228BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19238BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19248BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19258BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19268BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19278BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19288BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19298BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19308BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19318BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19328BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19338BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19348BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19358BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19368BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19378BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19388BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19398BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19408BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19418BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19428BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19438BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19448BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19458BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19468BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19478BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19488BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19498BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19508BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19518BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19528BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19538BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19548BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19558BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19568BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19578BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19588BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19598BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19608BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19618BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19628BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19638BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19648BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19658BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19668BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19678BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19688BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19698BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19708BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19718BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19728BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19738BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19748BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19758BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19768BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19778BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19788BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19798BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19808BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19818BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19828BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19838BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#19848BDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#19858BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#19868BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#19878BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#19888BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#19898BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#19908BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#19918BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#19928BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#19938BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#19948BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#19958BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#19968BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#19978BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#19988BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#19998BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20008BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20018BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20028BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20038BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20048BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20058BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20068BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20078BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20088BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20098BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20108BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20118BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20128BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20138BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20148BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20158BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20168BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20178BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20188BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20198BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20208BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20218BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20228BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20238BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20248BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20258BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20268BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20278BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20288BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20298BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20308BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20318BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20328BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20338BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20348BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20358BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20368BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20378BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20388BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20398BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20408BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20418BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20428BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20438BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20448BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20458BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20468BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20478BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#20488BDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[1].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20498BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20508BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20518BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20528BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20538BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20548BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20558BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20568BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20578BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20588BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20598BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20608BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20618BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20628BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20638BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20648BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20658BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20668BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20678BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20688BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20698BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20708BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20718BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20728BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20738BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20748BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20758BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20768BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20778BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20788BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20798BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20808BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20818BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20828BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20838BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20848BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20858BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20868BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20878BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20888BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20898BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20908BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20918BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20928BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20938BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20948BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20958BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20968BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20978BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20988BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#20998BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21008BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21018BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21028BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21038BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21048BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21058BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21068BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21078BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21088BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21098BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21108BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21118BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21128BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21138BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21148BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21158BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21168BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21178BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21188BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21198BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21208BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21218BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21228BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21238BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21248BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21258BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21268BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21278BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21288BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21298BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21308BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21318BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21328BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21338BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21348BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21358BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21368BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21378BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21388BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21398BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21408BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21418BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21428BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21438BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21448BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21458BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21468BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21478BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21488BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21498BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21508BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21518BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21528BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21538BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21548BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21558BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21568BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21578BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21588BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21598BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21608BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21618BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21628BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21638BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21648BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21658BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21668BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21678BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21688BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21698BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21708BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21718BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21728BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21738BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21748BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21758BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21768BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21778BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21788BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21798BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21808BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21818BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21828BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21838BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21848BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21858BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21868BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21878BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21888BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21898BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21908BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21918BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21928BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21938BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21948BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21958BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21968BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21978BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21988BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#21998BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22008BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22018BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22028BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22038BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22048BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22058BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22068BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22078BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22088BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22098BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22108BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22118BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22128BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22138BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22148BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22158BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22168BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22178BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22188BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22198BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22208BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22218BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22228BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22238BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22248BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22258BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22268BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22278BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22288BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22298BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22308BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22318BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22328BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22338BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22348BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22358BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22368BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22378BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22388BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22398BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#22408BDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22418BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22428BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22438BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22448BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22458BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22468BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22478BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22488BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22498BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22508BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22518BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22528BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22538BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22548BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22558BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22568BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22578BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22588BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22598BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22608BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22618BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22628BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22638BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22648BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22658BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22668BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22678BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22688BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22698BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22708BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22718BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22728BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22738BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22748BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22758BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22768BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22778BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22788BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22798BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22808BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22818BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22828BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22838BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22848BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22858BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22868BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22878BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22888BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22898BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22908BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22918BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22928BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22938BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22948BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22958BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22968BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22978BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22988BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#22998BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#23008BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#23018BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#23028BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#23038BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#23048BDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[2].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23058BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23068BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23078BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23088BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23098BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23108BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23118BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23128BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23138BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23148BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23158BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23168BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23178BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23188BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23198BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23208BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23218BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23228BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23238BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23248BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23258BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23268BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23278BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23288BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23298BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23308BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23318BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23328BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23338BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23348BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23358BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23368BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23378BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23388BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23398BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23408BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23418BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23428BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23438BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23448BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23458BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23468BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23478BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23488BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23498BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23508BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23518BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23528BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23538BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23548BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23558BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23568BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23578BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23588BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23598BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23608BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23618BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23628BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23638BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23648BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23658BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23668BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23678BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23688BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23698BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23708BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23718BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23728BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23738BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23748BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23758BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23768BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23778BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23788BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23798BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23808BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23818BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23828BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23838BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23848BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23858BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23868BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23878BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23888BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23898BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23908BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23918BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23928BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23938BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23948BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23958BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23968BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23978BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23988BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#23998BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24008BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24018BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24028BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24038BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24048BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24058BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24068BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24078BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24088BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24098BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24108BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24118BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24128BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24138BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24148BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24158BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24168BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24178BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24188BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24198BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24208BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24218BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24228BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24238BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24248BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24258BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24268BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24278BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24288BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24298BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24308BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24318BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24328BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24338BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24348BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24358BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24368BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24378BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24388BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24398BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24408BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24418BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24428BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24438BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24448BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24458BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24468BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24478BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24488BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24498BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24508BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24518BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24528BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24538BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24548BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24558BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24568BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24578BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24588BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24598BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24608BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24618BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24628BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24638BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24648BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24658BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24668BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24678BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24688BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24698BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24708BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24718BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24728BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24738BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24748BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24758BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24768BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24778BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24788BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24798BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24808BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24818BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24828BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24838BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24848BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24858BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24868BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24878BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24888BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24898BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24908BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24918BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24928BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24938BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24948BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24958BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#24968BDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#24978BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#24988BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#24998BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25008BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25018BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25028BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25038BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25048BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25058BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25068BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25078BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25088BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25098BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25108BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25118BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25128BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25138BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25148BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25158BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25168BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25178BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25188BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25198BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25208BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25218BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25228BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25238BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25248BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25258BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25268BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25278BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25288BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25298BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25308BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25318BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25328BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25338BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25348BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25358BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25368BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25378BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25388BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25398BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25408BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25418BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25428BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25438BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25448BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25458BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25468BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25478BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25488BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25498BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25508BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25518BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25528BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25538BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25548BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25558BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25568BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25578BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25588BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25598BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#25608BDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[3].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25618BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25628BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25638BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25648BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25658BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25668BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25678BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25688BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25698BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25708BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25718BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25728BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25738BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25748BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25758BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25768BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25778BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25788BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25798BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25808BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25818BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25828BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25838BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25848BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25858BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25868BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25878BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25888BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25898BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25908BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25918BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25928BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25938BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25948BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25958BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25968BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25978BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25988BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#25998BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26008BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26018BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26028BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26038BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26048BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26058BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26068BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26078BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26088BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26098BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26108BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26118BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26128BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26138BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26148BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26158BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26168BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26178BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26188BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26198BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26208BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26218BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26228BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26238BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26248BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26258BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26268BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26278BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26288BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26298BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26308BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26318BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26328BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26338BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26348BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26358BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26368BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26378BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26388BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26398BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26408BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26418BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26428BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26438BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26448BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26458BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26468BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26478BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26488BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26498BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26508BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26518BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26528BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26538BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26548BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26558BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26568BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26578BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26588BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26598BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26608BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26618BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26628BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26638BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26648BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26658BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26668BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26678BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26688BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26698BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26708BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26718BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26728BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26738BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26748BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26758BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26768BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26778BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26788BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26798BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26808BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26818BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26828BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26838BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26848BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26858BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26868BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26878BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26888BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26898BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26908BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26918BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26928BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26938BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26948BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26958BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26968BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26978BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26988BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#26998BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27008BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27018BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27028BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27038BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27048BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27058BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27068BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27078BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27088BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27098BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27108BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27118BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27128BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27138BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27148BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27158BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27168BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27178BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27188BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27198BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27208BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27218BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27228BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27238BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27248BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27258BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27268BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27278BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27288BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27298BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27308BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27318BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27328BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27338BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27348BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27358BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27368BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27378BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27388BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27398BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27408BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27418BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27428BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27438BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27448BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27458BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27468BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27478BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27488BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27498BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27508BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27518BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#27528BDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27538BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27548BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27558BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27568BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27578BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27588BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27598BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27608BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27618BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27628BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27638BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27648BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27658BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27668BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27678BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27688BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27698BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27708BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27718BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27728BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27738BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27748BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27758BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27768BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27778BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27788BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27798BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27808BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27818BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27828BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27838BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27848BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27858BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27868BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27878BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27888BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27898BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27908BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27918BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27928BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27938BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27948BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27958BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27968BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27978BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27988BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#27998BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28008BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28018BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28028BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28038BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28048BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28058BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28068BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28078BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28088BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28098BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28108BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28118BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28128BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28138BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28148BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28158BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#28168BDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[4].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28178BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28188BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28198BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28208BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28218BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28228BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28238BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28248BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28258BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28268BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28278BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28288BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28298BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28308BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28318BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28328BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28338BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28348BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28358BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28368BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28378BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28388BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28398BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28408BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28418BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28428BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28438BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28448BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28458BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28468BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28478BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28488BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28498BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28508BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28518BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28528BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28538BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28548BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28558BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28568BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28578BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28588BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28598BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28608BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28618BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28628BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28638BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28648BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28658BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28668BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28678BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28688BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28698BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28708BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28718BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28728BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28738BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28748BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28758BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28768BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28778BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28788BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28798BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28808BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28818BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28828BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28838BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28848BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28858BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28868BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28878BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28888BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28898BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28908BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28918BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28928BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28938BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28948BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28958BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28968BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28978BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28988BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#28998BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29008BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29018BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29028BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29038BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29048BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29058BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29068BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29078BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29088BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29098BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29108BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29118BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29128BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29138BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29148BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29158BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29168BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29178BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29188BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29198BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29208BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29218BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29228BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29238BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29248BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29258BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29268BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29278BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29288BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29298BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29308BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29318BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29328BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29338BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29348BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29358BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29368BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29378BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29388BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29398BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29408BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29418BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29428BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29438BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29448BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29458BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29468BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29478BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29488BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29498BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29508BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29518BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29528BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29538BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29548BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29558BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29568BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29578BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29588BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29598BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29608BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29618BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29628BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29638BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29648BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29658BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29668BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29678BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29688BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29698BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29708BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29718BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29728BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29738BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29748BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29758BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29768BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29778BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29788BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29798BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29808BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29818BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29828BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29838BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29848BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29858BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29868BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29878BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29888BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29898BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29908BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29918BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29928BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29938BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29948BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29958BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29968BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29978BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29988BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#29998BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30008BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30018BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30028BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30038BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30048BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30058BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30068BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30078BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30088BDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30098BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30108BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30118BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30128BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30138BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30148BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30158BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30168BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30178BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30188BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30198BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30208BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30218BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30228BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30238BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30248BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30258BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30268BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30278BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30288BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30298BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30308BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30318BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30328BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30338BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30348BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30358BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30368BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30378BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30388BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30398BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30408BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30418BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30428BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30438BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30448BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30458BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30468BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30478BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30488BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30498BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30508BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30518BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30528BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30538BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30548BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30558BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30568BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30578BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30588BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30598BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30608BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30618BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30628BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30638BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30648BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30658BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30668BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30678BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30688BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30698BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30708BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30718BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#30728BDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[5].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30738BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30748BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30758BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30768BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30778BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30788BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30798BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30808BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30818BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30828BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30838BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30848BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30858BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30868BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30878BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30888BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30898BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30908BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30918BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30928BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30938BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30948BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30958BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30968BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30978BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30988BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#30998BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31008BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31018BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31028BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31038BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31048BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31058BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31068BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31078BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31088BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31098BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31108BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31118BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31128BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31138BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31148BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31158BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31168BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31178BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31188BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31198BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31208BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31218BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31228BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31238BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31248BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31258BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31268BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31278BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31288BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31298BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31308BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31318BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31328BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31338BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31348BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31358BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31368BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31378BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31388BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31398BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31408BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31418BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31428BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31438BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31448BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31458BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31468BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31478BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31488BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31498BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31508BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31518BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31528BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31538BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31548BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31558BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31568BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31578BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31588BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31598BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31608BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31618BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31628BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31638BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31648BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31658BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31668BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31678BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31688BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31698BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31708BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31718BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31728BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31738BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31748BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31758BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31768BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31778BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31788BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31798BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31808BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31818BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31828BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31838BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31848BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31858BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31868BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31878BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31888BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31898BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31908BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31918BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31928BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31938BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31948BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31958BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31968BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31978BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31988BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#31998BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32008BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32018BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32028BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32038BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32048BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32058BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32068BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32078BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32088BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32098BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32108BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32118BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32128BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32138BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32148BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32158BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32168BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32178BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32188BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32198BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32208BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32218BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32228BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32238BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32248BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32258BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32268BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32278BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32288BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32298BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32308BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32318BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32328BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32338BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32348BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32358BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32368BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32378BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32388BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32398BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32408BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32418BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32428BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32438BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32448BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32458BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32468BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32478BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32488BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32498BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32508BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32518BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32528BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32538BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32548BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32558BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32568BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32578BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32588BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32598BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32608BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32618BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32628BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32638BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#32648BDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32658BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32668BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32678BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32688BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32698BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32708BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32718BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32728BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32738BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32748BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32758BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32768BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32778BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32788BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32798BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32808BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32818BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32828BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32838BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32848BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32858BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32868BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32878BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32888BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32898BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32908BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32918BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32928BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32938BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32948BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32958BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32968BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32978BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32988BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#32998BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33008BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33018BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33028BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33038BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33048BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33058BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33068BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33078BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33088BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33098BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33108BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33118BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33128BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33138BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33148BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33158BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33168BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33178BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33188BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33198BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33208BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33218BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33228BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33238BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33248BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33258BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33268BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33278BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#33288BDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[6].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33298BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33308BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33318BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33328BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33338BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33348BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33358BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33368BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33378BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33388BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33398BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33408BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33418BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33428BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33438BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33448BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33458BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33468BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33478BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33488BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33498BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33508BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33518BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33528BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33538BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33548BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33558BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33568BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33578BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33588BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33598BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33608BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33618BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33628BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33638BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33648BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33658BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33668BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33678BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33688BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33698BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33708BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33718BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33728BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33738BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33748BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33758BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33768BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33778BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33788BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33798BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33808BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33818BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33828BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33838BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33848BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33858BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33868BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33878BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33888BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33898BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33908BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33918BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33928BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33938BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33948BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33958BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33968BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33978BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33988BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#33998BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34008BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34018BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34028BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34038BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34048BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34058BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34068BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34078BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34088BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34098BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34108BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34118BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34128BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34138BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34148BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34158BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34168BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34178BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34188BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34198BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34208BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34218BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34228BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34238BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34248BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34258BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34268BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34278BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34288BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34298BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34308BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34318BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34328BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34338BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34348BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34358BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34368BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34378BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34388BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34398BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34408BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34418BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34428BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34438BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34448BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34458BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34468BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34478BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34488BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34498BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34508BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34518BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34528BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34538BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34548BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34558BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34568BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34578BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34588BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34598BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34608BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34618BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34628BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34638BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34648BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34658BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34668BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34678BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34688BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34698BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34708BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34718BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34728BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34738BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34748BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34758BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34768BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34778BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34788BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34798BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34808BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34818BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34828BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34838BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34848BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34858BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34868BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34878BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34888BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34898BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34908BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34918BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34928BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34938BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34948BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34958BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34968BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34978BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34988BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#34998BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35008BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35018BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35028BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35038BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35048BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35058BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35068BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35078BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35088BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35098BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35108BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35118BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35128BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35138BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35148BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35158BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35168BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35178BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35188BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35198BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35208BDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35218BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35228BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35238BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35248BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35258BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35268BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35278BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35288BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35298BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35308BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35318BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35328BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35338BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35348BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35358BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35368BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35378BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35388BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35398BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35408BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35418BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35428BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35438BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35448BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35458BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35468BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35478BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35488BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35498BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35508BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35518BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35528BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35538BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35548BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35558BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35568BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35578BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35588BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35598BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35608BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35618BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35628BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35638BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35648BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35658BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35668BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35678BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35688BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35698BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35708BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35718BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35728BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35738BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35748BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35758BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35768BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35778BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35788BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35798BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35808BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35818BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35828BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35838BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#35848BDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[7].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35858BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35868BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35878BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35888BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35898BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35908BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35918BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35928BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35938BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35948BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35958BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35968BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35978BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35988BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#35998BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36008BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36018BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36028BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36038BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36048BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36058BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36068BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36078BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36088BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36098BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36108BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36118BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36128BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36138BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36148BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36158BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36168BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36178BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36188BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36198BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36208BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36218BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36228BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36238BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36248BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36258BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36268BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36278BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36288BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36298BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36308BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36318BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36328BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36338BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36348BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36358BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36368BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36378BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36388BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36398BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36408BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36418BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36428BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36438BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36448BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36458BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36468BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36478BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36488BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36498BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36508BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36518BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36528BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36538BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36548BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36558BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36568BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36578BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36588BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36598BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36608BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36618BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36628BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36638BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36648BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36658BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36668BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36678BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36688BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36698BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36708BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36718BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36728BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36738BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36748BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36758BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36768BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36778BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36788BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36798BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36808BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36818BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36828BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36838BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36848BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36858BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36868BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36878BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36888BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36898BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36908BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36918BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36928BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36938BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36948BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36958BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36968BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36978BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36988BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#36998BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37008BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37018BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37028BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37038BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37048BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37058BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37068BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37078BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37088BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37098BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37108BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37118BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37128BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37138BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37148BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37158BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37168BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37178BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37188BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37198BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37208BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37218BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37228BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37238BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37248BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37258BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37268BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37278BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37288BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37298BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37308BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37318BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37328BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37338BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37348BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37358BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37368BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37378BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37388BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37398BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37408BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37418BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37428BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37438BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37448BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37458BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37468BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37478BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37488BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37498BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37508BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37518BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37528BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37538BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37548BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37558BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37568BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37578BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37588BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37598BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37608BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37618BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37628BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37638BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37648BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37658BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37668BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37678BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37688BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37698BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37708BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37718BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37728BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37738BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37748BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37758BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#37768BDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37778BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37788BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37798BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37808BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37818BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37828BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37838BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37848BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37858BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37868BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37878BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37888BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37898BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37908BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37918BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37928BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37938BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37948BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37958BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37968BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37978BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37988BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#37998BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38008BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38018BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38028BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38038BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38048BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38058BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38068BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38078BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38088BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38098BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38108BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38118BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38128BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38138BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38148BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38158BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38168BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38178BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38188BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38198BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38208BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38218BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38228BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38238BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38248BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38258BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38268BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38278BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38288BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38298BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38308BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38318BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38328BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38338BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38348BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38358BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38368BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38378BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38388BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38398BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#38408BDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[8].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38418BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38428BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38438BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38448BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38458BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38468BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38478BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38488BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38498BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38508BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38518BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38528BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38538BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38548BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38558BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38568BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38578BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38588BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38598BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38608BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38618BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38628BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38638BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38648BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38658BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38668BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38678BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38688BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38698BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38708BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38718BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38728BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38738BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38748BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38758BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38768BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38778BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38788BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38798BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38808BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38818BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38828BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38838BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38848BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38858BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38868BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38878BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38888BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38898BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38908BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38918BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38928BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38938BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38948BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38958BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38968BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38978BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38988BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#38998BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39008BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39018BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39028BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39038BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39048BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[1].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39058BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39068BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39078BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39088BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39098BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39108BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39118BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39128BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39138BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39148BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39158BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39168BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39178BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39188BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39198BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39208BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39218BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39228BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39238BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39248BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39258BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39268BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39278BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39288BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39298BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39308BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39318BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39328BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39338BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39348BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39358BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39368BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39378BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39388BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39398BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39408BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39418BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39428BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39438BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39448BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39458BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39468BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39478BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39488BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39498BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39508BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39518BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39528BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39538BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39548BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39558BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39568BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39578BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39588BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39598BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39608BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39618BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39628BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39638BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39648BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39658BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39668BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39678BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39688BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[2].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39698BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39708BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39718BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39728BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39738BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39748BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39758BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39768BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39778BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39788BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39798BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39808BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39818BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39828BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39838BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39848BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39858BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39868BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39878BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39888BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39898BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39908BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39918BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39928BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39938BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39948BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39958BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39968BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39978BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39988BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#39998BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40008BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40018BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40028BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40038BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40048BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40058BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40068BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40078BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40088BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40098BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40108BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40118BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40128BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40138BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40148BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40158BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40168BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40178BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40188BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40198BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40208BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40218BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40228BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40238BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40248BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40258BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40268BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40278BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40288BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40298BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40308BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40318BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_instWarning"DPIR-2*Asynchronous driver check2 DPIR-2#40328BDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].g_MUX_i[3].i_DSP_MUX/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40338BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40348BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40358BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40368BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40378BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *A[13] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40388BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40398BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40408BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40418BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40428BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40438BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40448BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40458BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40468BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *A[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40478BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40488BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40498BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40508BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40518BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40528BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40538BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40548BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40558BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *B[17] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40568BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[1] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40578BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[2] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40588BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40598BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40608BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40618BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40628BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40638BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[8] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40648BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *B[9] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40658BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[0] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40668BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[10] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40678BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[11] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40688BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[12] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40698BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[13] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40708BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[14] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40718BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[15] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40728BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[16] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40738BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[17] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40748BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[18] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40758BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[19] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40768BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[1] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40778BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[20] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40788BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[21] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40798BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[22] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40808BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[23] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40818BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[24] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[24] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40828BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[25] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[25] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40838BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[26] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[26] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40848BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[27] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[27] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40858BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[28] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[28] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40868BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[29] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[29] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40878BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[2] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40888BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[30] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[30] .* DSP48E2_inst_Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40898BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[31] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst *! *C[31] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40908BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[3] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40918BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[4] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40928BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[5] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40938BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[6] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40948BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[7] .* DSP48E2_inst\Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40958BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[8] .* DSP48E2_inst\ Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40968BDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst input pin ctrl_regs_inst/g_MUX_j[9].i_DSP_MUX_b/DSP48E2_inst/C[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. . DSP48E2_inst * *C[9] .* DSP48E2_inst Warning"DPIR-2*Asynchronous driver check2 DPIR-2#40978BDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.JDSP stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst input pin stat_regs_inst/g_stat_MUX_k[0].g_stat_MUX_j[0].g_stat_MUX_i[1].i_DSP_MUX/DSP48E2_inst/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. ; DSP48E2_inst * *B[0] ;* DSP48E2_instuWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#18B LUT cell SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[0].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[0].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.3 1N&FSM_sequential_StateJTAGTDO[1]_i_3__26 *( CLR H*BitCount_reg[0] CLR H*BitCount_reg[10] CLR H*BitCount_reg[11] CLR H*BitCount_reg[12] CLR H*BitCount_reg[13] CLR H*BitCount_reg[14] CLR H*BitCount_reg[15] CLR H*BitCount_reg[1] CLR H*BitCount_reg[2] CLR H*BitCount_reg[3] CLR H*BitCount_reg[4] CLR H*BitCount_reg[5] CLR H*BitCount_reg[6] CLR H*BitCount_reg[7] CLR H*BitCount_reg[8] CLR H*BitCount_reg[9] CLR I*ClkDiv_o_reg[0] CLR I*ClkDiv_o_reg[1] CLR I*ClkDiv_o_reg[2] CLR I*ClkDiv_o_reg[3] CLR I*Count_o_reg[0] CLR I*Count_o_reg[10] CLR I*Count_o_reg[11] CLR I*Count_o_reg[12] CLR I*Count_o_reg[13] CLR I*Count_o_reg[14] CLR I*Count_o_reg[15] CLR I*Count_o_reg[1] CLR I*Count_o_reg[2] CLR I*Count_o_reg[3] CLR I*Count_o_reg[4] CLR I*Count_o_reg[5] CLR I*Count_o_reg[6] CLR I*Count_o_reg[7] CLR I*Count_o_reg[8] CLR I*Count_o_reg[9] CLR I*DoCapture_o_reg CLR M* DoSleep_reg CLR M* JTAGStart_reg CLR H*StateEnd_reg[0] CLR H*StateEnd_reg[1] CLR H*StateEnd_reg[2] CLR H*StateEnd_reg[3] CLR I*StateReset_o_reg PRE I* ClkDiv_reg[0] PRE I* ClkDiv_reg[1] PRE I* ClkDiv_reg[2] PRE I* ClkDiv_reg[3] "PRE I*JTAGIgnoreTDO_o_reg PRE H*JTAGIgnoreTDO_reg PRE I*SleepCount_reg[0] !PRE I*SleepCount_reg[10] !PRE I*SleepCount_reg[11] !PRE I*SleepCount_reg[12] !PRE I*SleepCount_reg[13] !PRE I*SleepCount_reg[14] !PRE I*SleepCount_reg[15] !PRE I*SleepCount_reg[16] !PRE I*SleepCount_reg[17] !PRE I*SleepCount_reg[18] !PRE I*SleepCount_reg[19] PRE I*SleepCount_reg[1] !PRE I*SleepCount_reg[20] !PRE I*SleepCount_reg[21] !PRE I*SleepCount_reg[22] !PRE I*SleepCount_reg[23] !PRE I*SleepCount_reg[24] !PRE I*SleepCount_reg[25] !PRE I*SleepCount_reg[26] !PRE I*SleepCount_reg[27] !PRE I*SleepCount_reg[28] !PRE I*SleepCount_reg[29] PRE I*SleepCount_reg[2] !PRE I*SleepCount_reg[30] !PRE I*SleepCount_reg[31] PRE I*SleepCount_reg[3] PRE I*SleepCount_reg[4] PRE I*SleepCount_reg[5] PRE I*SleepCount_reg[6] PRE I*SleepCount_reg[7] PRE I*SleepCount_reg[8] PRE I*SleepCount_reg[9] PRE H*StateReset_reg CLR M*Busy_reg CLR M* FSM_WR_reg 2CLR K*#FSM_sequential_StateJTAGCtrl_reg[0] 2CLR K*#FSM_sequential_StateJTAGCtrl_reg[1] 0CLR K*!FSM_sequential_StateJTAGIO_reg[0] 0CLR K*!FSM_sequential_StateJTAGIO_reg[1] 0CLR K*!FSM_sequential_StateJTAGIO_reg[2] 1CLR K*"FSM_sequential_StateJTAGTDO_reg[0] 1CLR K*"FSM_sequential_StateJTAGTDO_reg[1] CLR M*TCK_in_rise_reg CLR M*TCKi_sync_reg[2] CLR L*TDOi_sync_reg[0] CLR L*TDOi_sync_reg[1] CLR L*TDOi_sync_reg[2] CLR L*TDOi_sync_reg[3] CLR L*TDOi_sync_reg[4] #CLR L*TMS_StateCurr_reg[0] #CLR L*TMS_StateCurr_reg[1] #CLR L*TMS_StateCurr_reg[2] #CLR L*TMS_StateCurr_reg[3] CLR M*TRst_reg CLR M*TimeoutError_reg "CLR M*gotoState_Start_reg CLR L*rdBitCount_reg[0] !CLR K*rdBitCount_reg[10] !CLR K*rdBitCount_reg[11] !CLR K*rdBitCount_reg[12] !CLR K*rdBitCount_reg[13] !CLR K*rdBitCount_reg[14] !CLR K*rdBitCount_reg[15] CLR L*rdBitCount_reg[1] CLR L*rdBitCount_reg[2] CLR K*rdBitCount_reg[3] CLR K*rdBitCount_reg[4] CLR K*rdBitCount_reg[5] CLR K*rdBitCount_reg[6] CLR K*rdBitCount_reg[7] CLR K*rdBitCount_reg[8] CLR K*rdBitCount_reg[9] CLR K*tclk_cnt_reg[0] CLR K*tclk_cnt_reg[1] CLR K*tclk_cnt_reg[2] CLR K*tclk_cnt_reg[3] CLR K*tclk_cnt_reg[4] CLR K*tclk_cnt_reg[5] CLR K*tclk_cnt_reg[6] CLR K*tclk_cnt_reg[7] "CLR L*tmsStateCntr_reg[0] "CLR L*tmsStateCntr_reg[1] "CLR L*tmsStateCntr_reg[2] "CLR L*tmsStateCntr_reg[3] PRE M*TCK_reg PRE M*TDI_reg PRE M*TMSo_reg $PRE M*gotoState_DoneTDO_reg !PRE M*gotoState_Done_reg !PRE K*timeoutCntr_reg[0] "PRE K*timeoutCntr_reg[10] "PRE K*timeoutCntr_reg[11] "PRE K*timeoutCntr_reg[12] "PRE K*timeoutCntr_reg[13] "PRE K*timeoutCntr_reg[14] !PRE K*timeoutCntr_reg[1] !PRE K*timeoutCntr_reg[2] !PRE K*timeoutCntr_reg[3] !PRE K*timeoutCntr_reg[4] !PRE K*timeoutCntr_reg[5] !PRE K*timeoutCntr_reg[6] !PRE K*timeoutCntr_reg[7] !PRE K*timeoutCntr_reg[8] !PRE K*timeoutCntr_reg[9]0Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#28B LUT cell SFP_GEN[10].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[10].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&FSM_sequential_StateJTAGTDO[1]_i_3__23 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]0Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#38B LUT cell SFP_GEN[11].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__34, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[11].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__34, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&FSM_sequential_StateJTAGTDO[1]_i_3__34 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR ׽*ClkDiv_o_reg[0] CLR ֽ*ClkDiv_o_reg[1] CLR ս*ClkDiv_o_reg[2] CLR Խ*ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR ޽*Count_o_reg[10] CLR ݽ*Count_o_reg[11] CLR ܽ*Count_o_reg[12] CLR ۽*Count_o_reg[13] CLR ڽ*Count_o_reg[14] CLR ٽ*Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR ߽*Count_o_reg[9] CLR ؽ*DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR ӽ*StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE ҽ*JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE ѽ*SleepCount_reg[0] "PRE ǽ*SleepCount_reg[10] "PRE ƽ*SleepCount_reg[11] "PRE Ž*SleepCount_reg[12] "PRE Ľ*SleepCount_reg[13] "PRE ý*SleepCount_reg[14] "PRE ½*SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE н*SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE Ͻ*SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE ν*SleepCount_reg[3] !PRE ͽ*SleepCount_reg[4] !PRE ̽*SleepCount_reg[5] !PRE ˽*SleepCount_reg[6] !PRE ʽ*SleepCount_reg[7] !PRE ɽ*SleepCount_reg[8] !PRE Ƚ*SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]0Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#48B LUT cell SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&FSM_sequential_StateJTAGTDO[1]_i_3__43 ** CLR ŷ*BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR ķ*BitCount_reg[1] CLR ÷*BitCount_reg[2] CLR ·*BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR ʷ*StateEnd_reg[0] CLR ɷ*StateEnd_reg[1] CLR ȷ*StateEnd_reg[2] CLR Ƿ*StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE ߷*SleepCount_reg[11] "PRE ޷*SleepCount_reg[12] "PRE ݷ*SleepCount_reg[13] "PRE ܷ*SleepCount_reg[14] "PRE ۷*SleepCount_reg[15] "PRE ڷ*SleepCount_reg[16] "PRE ٷ*SleepCount_reg[17] "PRE ط*SleepCount_reg[18] "PRE ׷*SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE ַ*SleepCount_reg[20] "PRE շ*SleepCount_reg[21] "PRE Է*SleepCount_reg[22] "PRE ӷ*SleepCount_reg[23] "PRE ҷ*SleepCount_reg[24] "PRE ѷ*SleepCount_reg[25] "PRE з*SleepCount_reg[26] "PRE Ϸ*SleepCount_reg[27] "PRE η*SleepCount_reg[28] "PRE ͷ*SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE ̷*SleepCount_reg[30] "PRE ˷*SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE Ʒ*StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR Һ*TDOi_sync_reg[0] CLR Ѻ*TDOi_sync_reg[1] CLR к*TDOi_sync_reg[2] CLR Ϻ*TDOi_sync_reg[3] CLR κ*TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR ͺ*rdBitCount_reg[0] "CLR ú*rdBitCount_reg[10] "CLR º*rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR ̺*rdBitCount_reg[1] !CLR ˺*rdBitCount_reg[2] !CLR ʺ*rdBitCount_reg[3] !CLR ɺ*rdBitCount_reg[4] !CLR Ⱥ*rdBitCount_reg[5] !CLR Ǻ*rdBitCount_reg[6] !CLR ƺ*rdBitCount_reg[7] !CLR ź*rdBitCount_reg[8] !CLR ĺ*rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]$Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#58B LUT cell SFP_GEN[13].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[13].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[13].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.0 ."FSM_sequential_StateJTAGTDO[1]_i_3 ** CLR ˱*BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR ʱ*BitCount_reg[1] CLR ɱ*BitCount_reg[2] CLR ȱ*BitCount_reg[3] CLR DZ*BitCount_reg[4] CLR Ʊ*BitCount_reg[5] CLR ű*BitCount_reg[6] CLR ı*BitCount_reg[7] CLR ñ*BitCount_reg[8] CLR ±*BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR ϱ*StateEnd_reg[0] CLR α*StateEnd_reg[1] CLR ͱ*StateEnd_reg[2] CLR ̱*StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE ߱*SleepCount_reg[16] "PRE ޱ*SleepCount_reg[17] "PRE ݱ*SleepCount_reg[18] "PRE ܱ*SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE ۱*SleepCount_reg[20] "PRE ڱ*SleepCount_reg[21] "PRE ٱ*SleepCount_reg[22] "PRE ر*SleepCount_reg[23] "PRE ױ*SleepCount_reg[24] "PRE ֱ*SleepCount_reg[25] "PRE ձ*SleepCount_reg[26] "PRE Ա*SleepCount_reg[27] "PRE ӱ*SleepCount_reg[28] "PRE ұ*SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE ѱ*SleepCount_reg[30] "PRE б*SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR Ӵ*TDOi_sync_reg[0] CLR Ҵ*TDOi_sync_reg[1] CLR Ѵ*TDOi_sync_reg[2] CLR д*TDOi_sync_reg[3] CLR ϴ*TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR δ*rdBitCount_reg[0] "CLR Ĵ*rdBitCount_reg[10] "CLR ô*rdBitCount_reg[11] "CLR ´*rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR ʹ*rdBitCount_reg[1] !CLR ̴*rdBitCount_reg[2] !CLR ˴*rdBitCount_reg[3] !CLR ʴ*rdBitCount_reg[4] !CLR ɴ*rdBitCount_reg[5] !CLR ȴ*rdBitCount_reg[6] !CLR Ǵ*rdBitCount_reg[7] !CLR ƴ*rdBitCount_reg[8] !CLR Ŵ*rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]-Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#68B LUT cell SFP_GEN[14].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[14].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[14].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.3 1%FSM_sequential_StateJTAGTDO[1]_i_3__0 ** CLR *BitCount_reg[0] CLR ޫ*BitCount_reg[10] CLR ݫ*BitCount_reg[11] CLR ܫ*BitCount_reg[12] CLR ۫*BitCount_reg[13] CLR ګ*BitCount_reg[14] CLR ٫*BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR ߫*BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR ð* DoSleep_reg CLR İ* JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR ߮*rdBitCount_reg[12] "CLR ޮ*rdBitCount_reg[13] "CLR ݮ*rdBitCount_reg[14] "CLR ܮ*rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR ˮ*tclk_cnt_reg[0] CLR ʮ*tclk_cnt_reg[1] CLR ɮ*tclk_cnt_reg[2] CLR Ȯ*tclk_cnt_reg[3] CLR Ǯ*tclk_cnt_reg[4] CLR Ʈ*tclk_cnt_reg[5] CLR Ů*tclk_cnt_reg[6] CLR Į*tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE î*timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE ®*timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]-Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#78B LUT cell SFP_GEN[15].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[15].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[15].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.3 1%FSM_sequential_StateJTAGTDO[1]_i_3__1 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR ӥ*DoCapture_o_reg CLR ߪ* DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR ҥ*StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE ѥ*JTAGIgnoreTDO_o_reg !PRE ϥ*JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE Х*StateReset_reg CLR Ҫ*Busy_reg CLR Ъ* FSM_WR_reg 3CLR ɨ*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR Ȩ*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR ̨*!FSM_sequential_StateJTAGIO_reg[0] 1CLR ˨*!FSM_sequential_StateJTAGIO_reg[1] 1CLR ʨ*!FSM_sequential_StateJTAGIO_reg[2] 2CLR Ǩ*"FSM_sequential_StateJTAGTDO_reg[0] 2CLR ƨ*"FSM_sequential_StateJTAGTDO_reg[1] CLR Ϫ*TCK_in_rise_reg CLR Ϊ*TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR Ѫ*TRst_reg CLR Ӫ*TimeoutError_reg #CLR ת*gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE ڪ*TCK_reg PRE ۪*TDI_reg PRE ت*TMSo_reg %PRE ժ*gotoState_DoneTDO_reg "PRE ֪*gotoState_Done_reg "PRE ߨ*timeoutCntr_reg[0] #PRE ը*timeoutCntr_reg[10] #PRE Ԩ*timeoutCntr_reg[11] #PRE Ө*timeoutCntr_reg[12] #PRE Ҩ*timeoutCntr_reg[13] #PRE Ѩ*timeoutCntr_reg[14] "PRE ި*timeoutCntr_reg[1] "PRE ݨ*timeoutCntr_reg[2] "PRE ܨ*timeoutCntr_reg[3] "PRE ۨ*timeoutCntr_reg[4] "PRE ڨ*timeoutCntr_reg[5] "PRE ٨*timeoutCntr_reg[6] "PRE ب*timeoutCntr_reg[7] "PRE ר*timeoutCntr_reg[8] "PRE ֨*timeoutCntr_reg[9]-Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#88B LUT cell SFP_GEN[16].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[16].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[16].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.3 1%FSM_sequential_StateJTAGTDO[1]_i_3__2 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR Ƞ*ClkDiv_o_reg[0] CLR Ǡ*ClkDiv_o_reg[1] CLR Ơ*ClkDiv_o_reg[2] CLR Š*ClkDiv_o_reg[3] CLR ؠ*Count_o_reg[0] CLR Π*Count_o_reg[10] CLR ͠*Count_o_reg[11] CLR ̠*Count_o_reg[12] CLR ˠ*Count_o_reg[13] CLR ʠ*Count_o_reg[14] CLR ɠ*Count_o_reg[15] CLR נ*Count_o_reg[1] CLR ֠*Count_o_reg[2] CLR ՠ*Count_o_reg[3] CLR Ԡ*Count_o_reg[4] CLR Ӡ*Count_o_reg[5] CLR Ҡ*Count_o_reg[6] CLR Ѡ*Count_o_reg[7] CLR Р*Count_o_reg[8] CLR Ϡ*Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE ܠ* ClkDiv_reg[0] PRE ۠* ClkDiv_reg[1] PRE ڠ* ClkDiv_reg[2] PRE ٠* ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE Ġ*SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE à*SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE  *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR У*TMS_StateCurr_reg[0] $CLR ϣ*TMS_StateCurr_reg[1] $CLR Σ*TMS_StateCurr_reg[2] $CLR ͣ*TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR ̣*tmsStateCntr_reg[0] #CLR ˣ*tmsStateCntr_reg[1] #CLR ʣ*tmsStateCntr_reg[2] #CLR ɣ*tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]0 Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#98B LUT cell SFP_GEN[17].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__22, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[17].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__22, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[17].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&FSM_sequential_StateJTAGTDO[1]_i_3__22 ** CLR Ϛ*BitCount_reg[0] CLR Ś*BitCount_reg[10] CLR Ě*BitCount_reg[11] CLR Ú*BitCount_reg[12] CLR š*BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR Κ*BitCount_reg[1] CLR ͚*BitCount_reg[2] CLR ̚*BitCount_reg[3] CLR ˚*BitCount_reg[4] CLR ʚ*BitCount_reg[5] CLR ɚ*BitCount_reg[6] CLR Ț*BitCount_reg[7] CLR ǚ*BitCount_reg[8] CLR ƚ*BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR Ԛ*StateEnd_reg[0] CLR Ӛ*StateEnd_reg[1] CLR Қ*StateEnd_reg[2] CLR њ*StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE ߚ*SleepCount_reg[21] "PRE ޚ*SleepCount_reg[22] "PRE ݚ*SleepCount_reg[23] "PRE ܚ*SleepCount_reg[24] "PRE ۚ*SleepCount_reg[25] "PRE ښ*SleepCount_reg[26] "PRE ٚ*SleepCount_reg[27] "PRE ؚ*SleepCount_reg[28] "PRE ך*SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE ֚*SleepCount_reg[30] "PRE ՚*SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE К*StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR ܝ*TDOi_sync_reg[0] CLR ۝*TDOi_sync_reg[1] CLR ڝ*TDOi_sync_reg[2] CLR ٝ*TDOi_sync_reg[3] CLR ؝*TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR ם*rdBitCount_reg[0] "CLR ͝*rdBitCount_reg[10] "CLR ̝*rdBitCount_reg[11] "CLR ˝*rdBitCount_reg[12] "CLR ʝ*rdBitCount_reg[13] "CLR ɝ*rdBitCount_reg[14] "CLR ȝ*rdBitCount_reg[15] !CLR ֝*rdBitCount_reg[1] !CLR ՝*rdBitCount_reg[2] !CLR ԝ*rdBitCount_reg[3] !CLR ӝ*rdBitCount_reg[4] !CLR ҝ*rdBitCount_reg[5] !CLR ѝ*rdBitCount_reg[6] !CLR Н*rdBitCount_reg[7] !CLR ϝ*rdBitCount_reg[8] !CLR Ν*rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1 Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#108B LUT cell SFP_GEN[18].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[18].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[18].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2 &FSM_sequential_StateJTAGTDO[1]_i_3__37 ** CLR *BitCount_reg[0] CLR ޔ *BitCount_reg[10] CLR ݔ *BitCount_reg[11] CLR ܔ *BitCount_reg[12] CLR ۔ *BitCount_reg[13] CLR ڔ *BitCount_reg[14] CLR ٔ *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR ߔ *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR ̙ * DoSleep_reg CLR ͙ * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE ؔ *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR ę *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR З *tclk_cnt_reg[0] CLR ϗ *tclk_cnt_reg[1] CLR Η *tclk_cnt_reg[2] CLR ͗ *tclk_cnt_reg[3] CLR ̗ *tclk_cnt_reg[4] CLR ˗ *tclk_cnt_reg[5] CLR ʗ *tclk_cnt_reg[6] CLR ɗ *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE Ǚ *TCK_reg PRE ș *TDI_reg PRE ř *TMSo_reg %PRE ™ *gotoState_DoneTDO_reg "PRE Ù *gotoState_Done_reg "PRE ȗ *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE Ǘ *timeoutCntr_reg[1] "PRE Ɨ *timeoutCntr_reg[2] "PRE ŗ *timeoutCntr_reg[3] "PRE ė *timeoutCntr_reg[4] "PRE × *timeoutCntr_reg[5] "PRE — *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]. Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#118B LUT cell SFP_GEN[19].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[19].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[19].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.3 1 %FSM_sequential_StateJTAGTDO[1]_i_3__3 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR Ž *DoCapture_o_reg CLR Γ * DoSleep_reg CLR ϓ * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR “ *TimeoutError_reg #CLR Ɠ *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR ֑ *tclk_cnt_reg[0] CLR Ց *tclk_cnt_reg[1] CLR ԑ *tclk_cnt_reg[2] CLR ӑ *tclk_cnt_reg[3] CLR ґ *tclk_cnt_reg[4] CLR ё *tclk_cnt_reg[5] CLR Б *tclk_cnt_reg[6] CLR ϑ *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE ɓ *TCK_reg PRE ʓ *TDI_reg PRE Ǔ *TMSo_reg %PRE ē *gotoState_DoneTDO_reg "PRE œ *gotoState_Done_reg "PRE Α *timeoutCntr_reg[0] #PRE đ *timeoutCntr_reg[10] #PRE Ñ *timeoutCntr_reg[11] #PRE ‘ *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE ͑ *timeoutCntr_reg[1] "PRE ̑ *timeoutCntr_reg[2] "PRE ˑ *timeoutCntr_reg[3] "PRE ʑ *timeoutCntr_reg[4] "PRE ɑ *timeoutCntr_reg[5] "PRE ȑ *timeoutCntr_reg[6] "PRE Ǒ *timeoutCntr_reg[7] "PRE Ƒ *timeoutCntr_reg[8] "PRE ő *timeoutCntr_reg[9] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#128B LUT cell SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2Ŏ &FSM_sequential_StateJTAGTDO[1]_i_3__31 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR ͉ *ClkDiv_o_reg[0] CLR ̉ *ClkDiv_o_reg[1] CLR ˉ *ClkDiv_o_reg[2] CLR ʉ *ClkDiv_o_reg[3] CLR މ *Count_o_reg[0] CLR ԉ *Count_o_reg[10] CLR Ӊ *Count_o_reg[11] CLR ҉ *Count_o_reg[12] CLR щ *Count_o_reg[13] CLR Љ *Count_o_reg[14] CLR ω *Count_o_reg[15] CLR ݉ *Count_o_reg[1] CLR ܉ *Count_o_reg[2] CLR ۉ *Count_o_reg[3] CLR ډ *Count_o_reg[4] CLR ى *Count_o_reg[5] CLR ؉ *Count_o_reg[6] CLR ׉ *Count_o_reg[7] CLR ։ *Count_o_reg[8] CLR Չ *Count_o_reg[9] CLR Ή *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR ɉ *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE ߉ * ClkDiv_reg[3] #PRE ȉ *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE lj *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE Ɖ *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE ʼn *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE ĉ *SleepCount_reg[3] !PRE É *SleepCount_reg[4] !PRE ‰ *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR ׌ *TMS_StateCurr_reg[0] $CLR ֌ *TMS_StateCurr_reg[1] $CLR Ռ *TMS_StateCurr_reg[2] $CLR Ԍ *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR ӌ *tmsStateCntr_reg[0] #CLR Ҍ *tmsStateCntr_reg[1] #CLR ь *tmsStateCntr_reg[2] #CLR Ќ *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1 Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#138B LUT cell SFP_GEN[20].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[20].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[20].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2߈ &FSM_sequential_StateJTAGTDO[1]_i_3__36 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE ׃ *SleepCount_reg[10] "PRE փ *SleepCount_reg[11] "PRE Ճ *SleepCount_reg[12] "PRE ԃ *SleepCount_reg[13] "PRE Ӄ *SleepCount_reg[14] "PRE ҃ *SleepCount_reg[15] "PRE у *SleepCount_reg[16] "PRE Ѓ *SleepCount_reg[17] "PRE σ *SleepCount_reg[18] "PRE ΃ *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE ̓ *SleepCount_reg[20] "PRE ̃ *SleepCount_reg[21] "PRE ˃ *SleepCount_reg[22] "PRE ʃ *SleepCount_reg[23] "PRE Ƀ *SleepCount_reg[24] "PRE ȃ *SleepCount_reg[25] "PRE ǃ *SleepCount_reg[26] "PRE ƃ *SleepCount_reg[27] "PRE Ń *SleepCount_reg[28] "PRE ă *SleepCount_reg[29] !PRE ߃ *SleepCount_reg[2] "PRE à *SleepCount_reg[30] "PRE ƒ *SleepCount_reg[31] !PRE ރ *SleepCount_reg[3] !PRE ݃ *SleepCount_reg[4] !PRE ܃ *SleepCount_reg[5] !PRE ۃ *SleepCount_reg[6] !PRE ڃ *SleepCount_reg[7] !PRE ك *SleepCount_reg[8] !PRE ؃ *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR Ɇ *TDOi_sync_reg[0] CLR Ȇ *TDOi_sync_reg[1] CLR dž *TDOi_sync_reg[2] CLR Ɔ *TDOi_sync_reg[3] CLR ņ *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR Ć *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR Æ *rdBitCount_reg[1] !CLR † *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#148B LUT cell SFP_GEN[21].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[21].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[21].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2 &FSM_sequential_StateJTAGTDO[1]_i_3__39 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR ߀ *TDOi_sync_reg[3] CLR ހ *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR ݀ *rdBitCount_reg[0] "CLR Ӏ *rdBitCount_reg[10] "CLR Ҁ *rdBitCount_reg[11] "CLR р *rdBitCount_reg[12] "CLR Ѐ *rdBitCount_reg[13] "CLR π *rdBitCount_reg[14] "CLR ΀ *rdBitCount_reg[15] !CLR ܀ *rdBitCount_reg[1] !CLR ۀ *rdBitCount_reg[2] !CLR ڀ *rdBitCount_reg[3] !CLR ـ *rdBitCount_reg[4] !CLR ؀ *rdBitCount_reg[5] !CLR ׀ *rdBitCount_reg[6] !CLR ր *rdBitCount_reg[7] !CLR Հ *rdBitCount_reg[8] !CLR Ԁ *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#158B LUT cell SFP_GEN[22].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[22].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[22].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2 &FSM_sequential_StateJTAGTDO[1]_i_3__42 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#168B LUT cell SFP_GEN[23].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[23].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[23].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&FSM_sequential_StateJTAGTDO[1]_i_3__21 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#178B LUT cell SFP_GEN[24].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[24].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[24].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&FSM_sequential_StateJTAGTDO[1]_i_3__41 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9].Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#188B LUT cell SFP_GEN[25].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[25].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[25].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.3 1%FSM_sequential_StateJTAGTDO[1]_i_3__4 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#198B LUT cell SFP_GEN[26].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[26].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[26].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&FSM_sequential_StateJTAGTDO[1]_i_3__27 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#208B LUT cell SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[27].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[27].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&FSM_sequential_StateJTAGTDO[1]_i_3__20 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9].Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#218B LUT cell SFP_GEN[28].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[28].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[28].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.3 1%FSM_sequential_StateJTAGTDO[1]_i_3__5 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#228B LUT cell SFP_GEN[29].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[29].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[29].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&FSM_sequential_StateJTAGTDO[1]_i_3__29 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#238B LUT cell SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&FSM_sequential_StateJTAGTDO[1]_i_3__44 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9].Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#248B LUT cell SFP_GEN[30].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[30].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[30].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.3 1%FSM_sequential_StateJTAGTDO[1]_i_3__6 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#258B LUT cell SFP_GEN[31].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[31].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[31].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&FSM_sequential_StateJTAGTDO[1]_i_3__25 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#268B LUT cell SFP_GEN[32].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[32].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[32].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&FSM_sequential_StateJTAGTDO[1]_i_3__32 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR θ*Count_o_reg[0] CLR ĸ*Count_o_reg[10] CLR ø*Count_o_reg[11] CLR ¸*Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR ͸*Count_o_reg[1] CLR ̸*Count_o_reg[2] CLR ˸*Count_o_reg[3] CLR ʸ*Count_o_reg[4] CLR ɸ*Count_o_reg[5] CLR ȸ*Count_o_reg[6] CLR Ǹ*Count_o_reg[7] CLR Ƹ*Count_o_reg[8] CLR Ÿ*Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE Ҹ* ClkDiv_reg[0] PRE Ѹ* ClkDiv_reg[1] PRE и* ClkDiv_reg[2] PRE ϸ* ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR ܺ*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR ۺ*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR ߺ*!FSM_sequential_StateJTAGIO_reg[0] 1CLR ޺*!FSM_sequential_StateJTAGIO_reg[1] 1CLR ݺ*!FSM_sequential_StateJTAGIO_reg[2] 2CLR ں*"FSM_sequential_StateJTAGTDO_reg[0] 2CLR ٺ*"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR ǻ*TMS_StateCurr_reg[0] $CLR ƻ*TMS_StateCurr_reg[1] $CLR Ż*TMS_StateCurr_reg[2] $CLR Ļ*TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR û*tmsStateCntr_reg[0] #CLR »*tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#278B LUT cell SFP_GEN[33].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[33].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[33].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2η&FSM_sequential_StateJTAGTDO[1]_i_3__17 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR ֲ*ClkDiv_o_reg[0] CLR ղ*ClkDiv_o_reg[1] CLR Բ*ClkDiv_o_reg[2] CLR Ӳ*ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR ݲ*Count_o_reg[10] CLR ܲ*Count_o_reg[11] CLR ۲*Count_o_reg[12] CLR ڲ*Count_o_reg[13] CLR ٲ*Count_o_reg[14] CLR ز*Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR ߲*Count_o_reg[8] CLR ޲*Count_o_reg[9] CLR ײ*DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR Ҳ*StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE Ѳ*JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE в*SleepCount_reg[0] "PRE Ʋ*SleepCount_reg[10] "PRE Ų*SleepCount_reg[11] "PRE IJ*SleepCount_reg[12] "PRE ò*SleepCount_reg[13] "PRE ²*SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE ϲ*SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE β*SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE Ͳ*SleepCount_reg[3] !PRE ̲*SleepCount_reg[4] !PRE ˲*SleepCount_reg[5] !PRE ʲ*SleepCount_reg[6] !PRE ɲ*SleepCount_reg[7] !PRE Ȳ*SleepCount_reg[8] !PRE Dz*SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR ߵ*TMS_StateCurr_reg[1] $CLR ޵*TMS_StateCurr_reg[2] $CLR ݵ*TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR ܵ*tmsStateCntr_reg[0] #CLR ۵*tmsStateCntr_reg[1] #CLR ڵ*tmsStateCntr_reg[2] #CLR ٵ*tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#288B LUT cell SFP_GEN[34].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[34].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[34].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&FSM_sequential_StateJTAGTDO[1]_i_3__24 ** CLR Ĭ*BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR ì*BitCount_reg[1] CLR ¬*BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR ɬ*StateEnd_reg[0] CLR Ȭ*StateEnd_reg[1] CLR Ǭ*StateEnd_reg[2] CLR Ƭ*StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE ߬*SleepCount_reg[10] "PRE ެ*SleepCount_reg[11] "PRE ݬ*SleepCount_reg[12] "PRE ܬ*SleepCount_reg[13] "PRE ۬*SleepCount_reg[14] "PRE ڬ*SleepCount_reg[15] "PRE ٬*SleepCount_reg[16] "PRE ج*SleepCount_reg[17] "PRE ׬*SleepCount_reg[18] "PRE ֬*SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE լ*SleepCount_reg[20] "PRE Ԭ*SleepCount_reg[21] "PRE Ӭ*SleepCount_reg[22] "PRE Ҭ*SleepCount_reg[23] "PRE Ѭ*SleepCount_reg[24] "PRE Ь*SleepCount_reg[25] "PRE Ϭ*SleepCount_reg[26] "PRE ά*SleepCount_reg[27] "PRE ͬ*SleepCount_reg[28] "PRE ̬*SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE ˬ*SleepCount_reg[30] "PRE ʬ*SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE Ŭ*StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR ѯ*TDOi_sync_reg[0] CLR Я*TDOi_sync_reg[1] CLR ϯ*TDOi_sync_reg[2] CLR ί*TDOi_sync_reg[3] CLR ͯ*TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR ̯*rdBitCount_reg[0] "CLR ¯*rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR ˯*rdBitCount_reg[1] !CLR ʯ*rdBitCount_reg[2] !CLR ɯ*rdBitCount_reg[3] !CLR ȯ*rdBitCount_reg[4] !CLR ǯ*rdBitCount_reg[5] !CLR Ư*rdBitCount_reg[6] !CLR ů*rdBitCount_reg[7] !CLR į*rdBitCount_reg[8] !CLR ï*rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9].Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#298B LUT cell SFP_GEN[35].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[35].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[35].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.3 1%FSM_sequential_StateJTAGTDO[1]_i_3__7 ** CLR ʦ*BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR ɦ*BitCount_reg[1] CLR Ȧ*BitCount_reg[2] CLR Ǧ*BitCount_reg[3] CLR Ʀ*BitCount_reg[4] CLR Ŧ*BitCount_reg[5] CLR Ħ*BitCount_reg[6] CLR æ*BitCount_reg[7] CLR ¦*BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR Φ*StateEnd_reg[0] CLR ͦ*StateEnd_reg[1] CLR ̦*StateEnd_reg[2] CLR ˦*StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE ߦ*SleepCount_reg[15] "PRE ަ*SleepCount_reg[16] "PRE ݦ*SleepCount_reg[17] "PRE ܦ*SleepCount_reg[18] "PRE ۦ*SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE ڦ*SleepCount_reg[20] "PRE ٦*SleepCount_reg[21] "PRE ئ*SleepCount_reg[22] "PRE צ*SleepCount_reg[23] "PRE ֦*SleepCount_reg[24] "PRE զ*SleepCount_reg[25] "PRE Ԧ*SleepCount_reg[26] "PRE Ӧ*SleepCount_reg[27] "PRE Ҧ*SleepCount_reg[28] "PRE Ѧ*SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE Ц*SleepCount_reg[30] "PRE Ϧ*SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR ҩ*TDOi_sync_reg[0] CLR ѩ*TDOi_sync_reg[1] CLR Щ*TDOi_sync_reg[2] CLR ϩ*TDOi_sync_reg[3] CLR Ω*TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR ͩ*rdBitCount_reg[0] "CLR é*rdBitCount_reg[10] "CLR ©*rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR ̩*rdBitCount_reg[1] !CLR ˩*rdBitCount_reg[2] !CLR ʩ*rdBitCount_reg[3] !CLR ɩ*rdBitCount_reg[4] !CLR ȩ*rdBitCount_reg[5] !CLR ǩ*rdBitCount_reg[6] !CLR Ʃ*rdBitCount_reg[7] !CLR ũ*rdBitCount_reg[8] !CLR ĩ*rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#308B LUT cell SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[36].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[36].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&FSM_sequential_StateJTAGTDO[1]_i_3__33 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR ݥ* DoSleep_reg CLR ޥ* JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR Х*Busy_reg CLR Υ* FSM_WR_reg 3CLR ã*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR £*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR ƣ*!FSM_sequential_StateJTAGIO_reg[0] 1CLR ţ*!FSM_sequential_StateJTAGIO_reg[1] 1CLR ģ*!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR ͥ*TCK_in_rise_reg CLR ̥*TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR ϥ*TRst_reg CLR ѥ*TimeoutError_reg #CLR ե*gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR ߣ*tclk_cnt_reg[2] CLR ޣ*tclk_cnt_reg[3] CLR ݣ*tclk_cnt_reg[4] CLR ܣ*tclk_cnt_reg[5] CLR ۣ*tclk_cnt_reg[6] CLR ڣ*tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE إ*TCK_reg PRE ٥*TDI_reg PRE ֥*TMSo_reg %PRE ӥ*gotoState_DoneTDO_reg "PRE ԥ*gotoState_Done_reg "PRE ٣*timeoutCntr_reg[0] #PRE ϣ*timeoutCntr_reg[10] #PRE Σ*timeoutCntr_reg[11] #PRE ͣ*timeoutCntr_reg[12] #PRE ̣*timeoutCntr_reg[13] #PRE ˣ*timeoutCntr_reg[14] "PRE أ*timeoutCntr_reg[1] "PRE ף*timeoutCntr_reg[2] "PRE ֣*timeoutCntr_reg[3] "PRE գ*timeoutCntr_reg[4] "PRE ԣ*timeoutCntr_reg[5] "PRE ӣ*timeoutCntr_reg[6] "PRE ң*timeoutCntr_reg[7] "PRE ѣ*timeoutCntr_reg[8] "PRE У*timeoutCntr_reg[9]1Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#318B LUT cell SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[37].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[37].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&FSM_sequential_StateJTAGTDO[1]_i_3__19 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR Λ*Count_o_reg[0] CLR ě*Count_o_reg[10] CLR Û*Count_o_reg[11] CLR ›*Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR ͛*Count_o_reg[1] CLR ̛*Count_o_reg[2] CLR ˛*Count_o_reg[3] CLR ʛ*Count_o_reg[4] CLR ɛ*Count_o_reg[5] CLR ț*Count_o_reg[6] CLR Ǜ*Count_o_reg[7] CLR ƛ*Count_o_reg[8] CLR ś*Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR *StateReset_o_reg PRE қ* ClkDiv_reg[0] PRE ћ* ClkDiv_reg[1] PRE Л* ClkDiv_reg[2] PRE ϛ* ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR ܝ*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR ۝*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR ߝ*!FSM_sequential_StateJTAGIO_reg[0] 1CLR ޝ*!FSM_sequential_StateJTAGIO_reg[1] 1CLR ݝ*!FSM_sequential_StateJTAGIO_reg[2] 2CLR ڝ*"FSM_sequential_StateJTAGTDO_reg[0] 2CLR ٝ*"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR Ǟ*TMS_StateCurr_reg[0] $CLR ƞ*TMS_StateCurr_reg[1] $CLR Ş*TMS_StateCurr_reg[2] $CLR Ğ*TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR Þ*tmsStateCntr_reg[0] #CLR ž*tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1 Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#328B LUT cell SFP_GEN[38].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[38].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[38].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2Κ&FSM_sequential_StateJTAGTDO[1]_i_3__18 ** CLR *BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR *BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR ֕*ClkDiv_o_reg[0] CLR Օ*ClkDiv_o_reg[1] CLR ԕ*ClkDiv_o_reg[2] CLR ӕ*ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR ݕ*Count_o_reg[10] CLR ܕ*Count_o_reg[11] CLR ە*Count_o_reg[12] CLR ڕ*Count_o_reg[13] CLR ٕ*Count_o_reg[14] CLR ؕ*Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR ߕ*Count_o_reg[8] CLR ޕ*Count_o_reg[9] CLR ו*DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR *StateEnd_reg[3] CLR ҕ*StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE ѕ*JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE Е*SleepCount_reg[0] "PRE ƕ*SleepCount_reg[10] "PRE ŕ*SleepCount_reg[11] "PRE ĕ*SleepCount_reg[12] "PRE Õ*SleepCount_reg[13] "PRE •*SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE ϕ*SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE Ε*SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE ͕*SleepCount_reg[3] !PRE ̕*SleepCount_reg[4] !PRE ˕*SleepCount_reg[5] !PRE ʕ*SleepCount_reg[6] !PRE ɕ*SleepCount_reg[7] !PRE ȕ*SleepCount_reg[8] !PRE Ǖ*SleepCount_reg[9] PRE *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR ߘ*TMS_StateCurr_reg[1] $CLR ޘ*TMS_StateCurr_reg[2] $CLR ݘ*TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR *rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR *rdBitCount_reg[6] !CLR *rdBitCount_reg[7] !CLR *rdBitCount_reg[8] !CLR *rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR ܘ*tmsStateCntr_reg[0] #CLR ۘ*tmsStateCntr_reg[1] #CLR ژ*tmsStateCntr_reg[2] #CLR ٘*tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1!Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#338B LUT cell SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[39].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[39].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&FSM_sequential_StateJTAGTDO[1]_i_3__38 ** CLR ď*BitCount_reg[0] CLR *BitCount_reg[10] CLR *BitCount_reg[11] CLR *BitCount_reg[12] CLR *BitCount_reg[13] CLR *BitCount_reg[14] CLR *BitCount_reg[15] CLR Ï*BitCount_reg[1] CLR *BitCount_reg[2] CLR *BitCount_reg[3] CLR *BitCount_reg[4] CLR *BitCount_reg[5] CLR *BitCount_reg[6] CLR *BitCount_reg[7] CLR *BitCount_reg[8] CLR *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR * JTAGStart_reg CLR ɏ*StateEnd_reg[0] CLR ȏ*StateEnd_reg[1] CLR Ǐ*StateEnd_reg[2] CLR Ə*StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE ߏ*SleepCount_reg[10] "PRE ޏ*SleepCount_reg[11] "PRE ݏ*SleepCount_reg[12] "PRE ܏*SleepCount_reg[13] "PRE ۏ*SleepCount_reg[14] "PRE ڏ*SleepCount_reg[15] "PRE ُ*SleepCount_reg[16] "PRE ؏*SleepCount_reg[17] "PRE ׏*SleepCount_reg[18] "PRE ֏*SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE Տ*SleepCount_reg[20] "PRE ԏ*SleepCount_reg[21] "PRE ӏ*SleepCount_reg[22] "PRE ҏ*SleepCount_reg[23] "PRE я*SleepCount_reg[24] "PRE Џ*SleepCount_reg[25] "PRE Ϗ*SleepCount_reg[26] "PRE Ώ*SleepCount_reg[27] "PRE ͏*SleepCount_reg[28] "PRE ̏*SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE ˏ*SleepCount_reg[30] "PRE ʏ*SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE ŏ*StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR ђ*TDOi_sync_reg[0] CLR В*TDOi_sync_reg[1] CLR ϒ*TDOi_sync_reg[2] CLR Β*TDOi_sync_reg[3] CLR ͒*TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR ̒*rdBitCount_reg[0] "CLR ’*rdBitCount_reg[10] "CLR *rdBitCount_reg[11] "CLR *rdBitCount_reg[12] "CLR *rdBitCount_reg[13] "CLR *rdBitCount_reg[14] "CLR *rdBitCount_reg[15] !CLR ˒*rdBitCount_reg[1] !CLR ʒ*rdBitCount_reg[2] !CLR ɒ*rdBitCount_reg[3] !CLR Ȓ*rdBitCount_reg[4] !CLR ǒ*rdBitCount_reg[5] !CLR ƒ*rdBitCount_reg[6] !CLR Œ*rdBitCount_reg[7] !CLR Ē*rdBitCount_reg[8] !CLR Ò*rdBitCount_reg[9] CLR *tclk_cnt_reg[0] CLR *tclk_cnt_reg[1] CLR *tclk_cnt_reg[2] CLR *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]"Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#348B LUT cell SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2 &FSM_sequential_StateJTAGTDO[1]_i_3__40 ** CLR ݉ *BitCount_reg[0] CLR Ӊ *BitCount_reg[10] CLR ҉ *BitCount_reg[11] CLR щ *BitCount_reg[12] CLR Љ *BitCount_reg[13] CLR ω *BitCount_reg[14] CLR Ή *BitCount_reg[15] CLR ܉ *BitCount_reg[1] CLR ۉ *BitCount_reg[2] CLR ډ *BitCount_reg[3] CLR ى *BitCount_reg[4] CLR ؉ *BitCount_reg[5] CLR ׉ *BitCount_reg[6] CLR ։ *BitCount_reg[7] CLR Չ *BitCount_reg[8] CLR ԉ *BitCount_reg[9] CLR *ClkDiv_o_reg[0] CLR *ClkDiv_o_reg[1] CLR *ClkDiv_o_reg[2] CLR *ClkDiv_o_reg[3] CLR *Count_o_reg[0] CLR *Count_o_reg[10] CLR *Count_o_reg[11] CLR *Count_o_reg[12] CLR *Count_o_reg[13] CLR *Count_o_reg[14] CLR *Count_o_reg[15] CLR *Count_o_reg[1] CLR *Count_o_reg[2] CLR *Count_o_reg[3] CLR *Count_o_reg[4] CLR *Count_o_reg[5] CLR *Count_o_reg[6] CLR *Count_o_reg[7] CLR *Count_o_reg[8] CLR *Count_o_reg[9] CLR *DoCapture_o_reg CLR * DoSleep_reg CLR Ž * JTAGStart_reg CLR *StateEnd_reg[0] CLR *StateEnd_reg[1] CLR *StateEnd_reg[2] CLR ߉ *StateEnd_reg[3] CLR *StateReset_o_reg PRE * ClkDiv_reg[0] PRE * ClkDiv_reg[1] PRE * ClkDiv_reg[2] PRE * ClkDiv_reg[3] #PRE *JTAGIgnoreTDO_o_reg !PRE ͉ *JTAGIgnoreTDO_reg !PRE *SleepCount_reg[0] "PRE *SleepCount_reg[10] "PRE *SleepCount_reg[11] "PRE *SleepCount_reg[12] "PRE *SleepCount_reg[13] "PRE *SleepCount_reg[14] "PRE *SleepCount_reg[15] "PRE *SleepCount_reg[16] "PRE *SleepCount_reg[17] "PRE *SleepCount_reg[18] "PRE *SleepCount_reg[19] !PRE *SleepCount_reg[1] "PRE *SleepCount_reg[20] "PRE *SleepCount_reg[21] "PRE *SleepCount_reg[22] "PRE *SleepCount_reg[23] "PRE *SleepCount_reg[24] "PRE *SleepCount_reg[25] "PRE *SleepCount_reg[26] "PRE *SleepCount_reg[27] "PRE *SleepCount_reg[28] "PRE *SleepCount_reg[29] !PRE *SleepCount_reg[2] "PRE *SleepCount_reg[30] "PRE *SleepCount_reg[31] !PRE *SleepCount_reg[3] !PRE *SleepCount_reg[4] !PRE *SleepCount_reg[5] !PRE *SleepCount_reg[6] !PRE *SleepCount_reg[7] !PRE *SleepCount_reg[8] !PRE *SleepCount_reg[9] PRE މ *StateReset_reg CLR *Busy_reg CLR * FSM_WR_reg 3CLR *#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR *#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[0] 1CLR *!FSM_sequential_StateJTAGIO_reg[1] 1CLR *!FSM_sequential_StateJTAGIO_reg[2] 2CLR *"FSM_sequential_StateJTAGTDO_reg[0] 2CLR *"FSM_sequential_StateJTAGTDO_reg[1] CLR *TCK_in_rise_reg CLR *TCKi_sync_reg[2] CLR *TDOi_sync_reg[0] CLR *TDOi_sync_reg[1] CLR *TDOi_sync_reg[2] CLR *TDOi_sync_reg[3] CLR *TDOi_sync_reg[4] $CLR *TMS_StateCurr_reg[0] $CLR *TMS_StateCurr_reg[1] $CLR *TMS_StateCurr_reg[2] $CLR *TMS_StateCurr_reg[3] CLR *TRst_reg CLR *TimeoutError_reg #CLR *gotoState_Start_reg !CLR *rdBitCount_reg[0] "CLR ی *rdBitCount_reg[10] "CLR ڌ *rdBitCount_reg[11] "CLR ٌ *rdBitCount_reg[12] "CLR ، *rdBitCount_reg[13] "CLR ׌ *rdBitCount_reg[14] "CLR ֌ *rdBitCount_reg[15] !CLR *rdBitCount_reg[1] !CLR *rdBitCount_reg[2] !CLR *rdBitCount_reg[3] !CLR *rdBitCount_reg[4] !CLR *rdBitCount_reg[5] !CLR ߌ *rdBitCount_reg[6] !CLR ތ *rdBitCount_reg[7] !CLR ݌ *rdBitCount_reg[8] !CLR ܌ *rdBitCount_reg[9] CLR Ō *tclk_cnt_reg[0] CLR Č *tclk_cnt_reg[1] CLR Ì *tclk_cnt_reg[2] CLR Œ *tclk_cnt_reg[3] CLR *tclk_cnt_reg[4] CLR *tclk_cnt_reg[5] CLR *tclk_cnt_reg[6] CLR *tclk_cnt_reg[7] #CLR *tmsStateCntr_reg[0] #CLR *tmsStateCntr_reg[1] #CLR *tmsStateCntr_reg[2] #CLR *tmsStateCntr_reg[3] PRE *TCK_reg PRE *TDI_reg PRE *TMSo_reg %PRE *gotoState_DoneTDO_reg "PRE *gotoState_Done_reg "PRE *timeoutCntr_reg[0] #PRE *timeoutCntr_reg[10] #PRE *timeoutCntr_reg[11] #PRE *timeoutCntr_reg[12] #PRE *timeoutCntr_reg[13] #PRE *timeoutCntr_reg[14] "PRE *timeoutCntr_reg[1] "PRE *timeoutCntr_reg[2] "PRE *timeoutCntr_reg[3] "PRE *timeoutCntr_reg[4] "PRE *timeoutCntr_reg[5] "PRE *timeoutCntr_reg[6] "PRE *timeoutCntr_reg[7] "PRE *timeoutCntr_reg[8] "PRE *timeoutCntr_reg[9]1#Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#358B LUT cell SFP_GEN[40].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[40].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[40].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2!&FSM_sequential_StateJTAGTDO[1]_i_3__12 ** CLR !*BitCount_reg[0] CLR !*BitCount_reg[10] CLR !*BitCount_reg[11] CLR !*BitCount_reg[12] CLR !*BitCount_reg[13] CLR !*BitCount_reg[14] CLR !*BitCount_reg[15] CLR !*BitCount_reg[1] CLR !*BitCount_reg[2] CLR !*BitCount_reg[3] CLR !*BitCount_reg[4] CLR !*BitCount_reg[5] CLR !*BitCount_reg[6] CLR !*BitCount_reg[7] CLR !*BitCount_reg[8] CLR !*BitCount_reg[9] CLR !*ClkDiv_o_reg[0] CLR !*ClkDiv_o_reg[1] CLR !*ClkDiv_o_reg[2] CLR !*ClkDiv_o_reg[3] CLR !*Count_o_reg[0] CLR !*Count_o_reg[10] CLR !*Count_o_reg[11] CLR !*Count_o_reg[12] CLR !*Count_o_reg[13] CLR !*Count_o_reg[14] CLR !*Count_o_reg[15] CLR !*Count_o_reg[1] CLR !*Count_o_reg[2] CLR !*Count_o_reg[3] CLR !*Count_o_reg[4] CLR !*Count_o_reg[5] CLR !*Count_o_reg[6] CLR !*Count_o_reg[7] CLR !*Count_o_reg[8] CLR !*Count_o_reg[9] CLR !*DoCapture_o_reg CLR ڈ!* DoSleep_reg CLR ۈ!* JTAGStart_reg CLR !*StateEnd_reg[0] CLR !*StateEnd_reg[1] CLR !*StateEnd_reg[2] CLR !*StateEnd_reg[3] CLR !*StateReset_o_reg PRE !* ClkDiv_reg[0] PRE !* ClkDiv_reg[1] PRE !* ClkDiv_reg[2] PRE !* ClkDiv_reg[3] #PRE !*JTAGIgnoreTDO_o_reg !PRE !*JTAGIgnoreTDO_reg !PRE !*SleepCount_reg[0] "PRE !*SleepCount_reg[10] "PRE !*SleepCount_reg[11] "PRE !*SleepCount_reg[12] "PRE !*SleepCount_reg[13] "PRE !*SleepCount_reg[14] "PRE !*SleepCount_reg[15] "PRE !*SleepCount_reg[16] "PRE !*SleepCount_reg[17] "PRE !*SleepCount_reg[18] "PRE !*SleepCount_reg[19] !PRE !*SleepCount_reg[1] "PRE !*SleepCount_reg[20] "PRE !*SleepCount_reg[21] "PRE !*SleepCount_reg[22] "PRE !*SleepCount_reg[23] "PRE !*SleepCount_reg[24] "PRE !*SleepCount_reg[25] "PRE !*SleepCount_reg[26] "PRE !*SleepCount_reg[27] "PRE !*SleepCount_reg[28] "PRE !*SleepCount_reg[29] !PRE !*SleepCount_reg[2] "PRE !*SleepCount_reg[30] "PRE !*SleepCount_reg[31] !PRE !*SleepCount_reg[3] !PRE !*SleepCount_reg[4] !PRE !*SleepCount_reg[5] !PRE !*SleepCount_reg[6] !PRE !*SleepCount_reg[7] !PRE !*SleepCount_reg[8] !PRE !*SleepCount_reg[9] PRE !*StateReset_reg CLR ͈!*Busy_reg CLR ˈ!* FSM_WR_reg 3CLR !*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR !*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR Æ!*!FSM_sequential_StateJTAGIO_reg[0] 1CLR †!*!FSM_sequential_StateJTAGIO_reg[1] 1CLR !*!FSM_sequential_StateJTAGIO_reg[2] 2CLR !*"FSM_sequential_StateJTAGTDO_reg[0] 2CLR !*"FSM_sequential_StateJTAGTDO_reg[1] CLR ʈ!*TCK_in_rise_reg CLR Ɉ!*TCKi_sync_reg[2] CLR !*TDOi_sync_reg[0] CLR !*TDOi_sync_reg[1] CLR !*TDOi_sync_reg[2] CLR !*TDOi_sync_reg[3] CLR !*TDOi_sync_reg[4] $CLR !*TMS_StateCurr_reg[0] $CLR !*TMS_StateCurr_reg[1] $CLR !*TMS_StateCurr_reg[2] $CLR !*TMS_StateCurr_reg[3] CLR ̈!*TRst_reg CLR Έ!*TimeoutError_reg #CLR ҈!*gotoState_Start_reg !CLR !*rdBitCount_reg[0] "CLR !*rdBitCount_reg[10] "CLR !*rdBitCount_reg[11] "CLR !*rdBitCount_reg[12] "CLR !*rdBitCount_reg[13] "CLR !*rdBitCount_reg[14] "CLR !*rdBitCount_reg[15] !CLR !*rdBitCount_reg[1] !CLR !*rdBitCount_reg[2] !CLR !*rdBitCount_reg[3] !CLR !*rdBitCount_reg[4] !CLR !*rdBitCount_reg[5] !CLR !*rdBitCount_reg[6] !CLR !*rdBitCount_reg[7] !CLR !*rdBitCount_reg[8] !CLR !*rdBitCount_reg[9] CLR ކ!*tclk_cnt_reg[0] CLR ݆!*tclk_cnt_reg[1] CLR ܆!*tclk_cnt_reg[2] CLR ۆ!*tclk_cnt_reg[3] CLR چ!*tclk_cnt_reg[4] CLR ن!*tclk_cnt_reg[5] CLR ؆!*tclk_cnt_reg[6] CLR ׆!*tclk_cnt_reg[7] #CLR !*tmsStateCntr_reg[0] #CLR !*tmsStateCntr_reg[1] #CLR !*tmsStateCntr_reg[2] #CLR !*tmsStateCntr_reg[3] PRE Ո!*TCK_reg PRE ֈ!*TDI_reg PRE ӈ!*TMSo_reg %PRE Ј!*gotoState_DoneTDO_reg "PRE ш!*gotoState_Done_reg "PRE ֆ!*timeoutCntr_reg[0] #PRE ̆!*timeoutCntr_reg[10] #PRE ˆ!*timeoutCntr_reg[11] #PRE ʆ!*timeoutCntr_reg[12] #PRE Ɇ!*timeoutCntr_reg[13] #PRE Ȇ!*timeoutCntr_reg[14] "PRE Ն!*timeoutCntr_reg[1] "PRE Ԇ!*timeoutCntr_reg[2] "PRE ӆ!*timeoutCntr_reg[3] "PRE ҆!*timeoutCntr_reg[4] "PRE ц!*timeoutCntr_reg[5] "PRE І!*timeoutCntr_reg[6] "PRE φ!*timeoutCntr_reg[7] "PRE Ά!*timeoutCntr_reg[8] "PRE ͆!*timeoutCntr_reg[9]1$Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#368B LUT cell SFP_GEN[41].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[41].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[41].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2"&FSM_sequential_StateJTAGTDO[1]_i_3__15 ** CLR !*BitCount_reg[0] CLR !*BitCount_reg[10] CLR !*BitCount_reg[11] CLR !*BitCount_reg[12] CLR !*BitCount_reg[13] CLR !*BitCount_reg[14] CLR !*BitCount_reg[15] CLR !*BitCount_reg[1] CLR !*BitCount_reg[2] CLR !*BitCount_reg[3] CLR !*BitCount_reg[4] CLR !*BitCount_reg[5] CLR !*BitCount_reg[6] CLR !*BitCount_reg[7] CLR !*BitCount_reg[8] CLR !*BitCount_reg[9] CLR !*ClkDiv_o_reg[0] CLR !*ClkDiv_o_reg[1] CLR !*ClkDiv_o_reg[2] CLR !*ClkDiv_o_reg[3] CLR !*Count_o_reg[0] CLR !*Count_o_reg[10] CLR !*Count_o_reg[11] CLR !*Count_o_reg[12] CLR !*Count_o_reg[13] CLR !*Count_o_reg[14] CLR !*Count_o_reg[15] CLR !*Count_o_reg[1] CLR !*Count_o_reg[2] CLR !*Count_o_reg[3] CLR !*Count_o_reg[4] CLR !*Count_o_reg[5] CLR !*Count_o_reg[6] CLR !*Count_o_reg[7] CLR !*Count_o_reg[8] CLR !*Count_o_reg[9] CLR !*DoCapture_o_reg CLR "* DoSleep_reg CLR "* JTAGStart_reg CLR !*StateEnd_reg[0] CLR !*StateEnd_reg[1] CLR !*StateEnd_reg[2] CLR !*StateEnd_reg[3] CLR !*StateReset_o_reg PRE !* ClkDiv_reg[0] PRE !* ClkDiv_reg[1] PRE !* ClkDiv_reg[2] PRE !* ClkDiv_reg[3] #PRE !*JTAGIgnoreTDO_o_reg !PRE !*JTAGIgnoreTDO_reg !PRE !*SleepCount_reg[0] "PRE !*SleepCount_reg[10] "PRE !*SleepCount_reg[11] "PRE !*SleepCount_reg[12] "PRE !*SleepCount_reg[13] "PRE !*SleepCount_reg[14] "PRE !*SleepCount_reg[15] "PRE !*SleepCount_reg[16] "PRE !*SleepCount_reg[17] "PRE !*SleepCount_reg[18] "PRE !*SleepCount_reg[19] !PRE !*SleepCount_reg[1] "PRE !*SleepCount_reg[20] "PRE !*SleepCount_reg[21] "PRE !*SleepCount_reg[22] "PRE !*SleepCount_reg[23] "PRE !*SleepCount_reg[24] "PRE !*SleepCount_reg[25] "PRE !*SleepCount_reg[26] "PRE !*SleepCount_reg[27] "PRE !*SleepCount_reg[28] "PRE !*SleepCount_reg[29] !PRE !*SleepCount_reg[2] "PRE !*SleepCount_reg[30] "PRE !*SleepCount_reg[31] !PRE !*SleepCount_reg[3] !PRE !*SleepCount_reg[4] !PRE !*SleepCount_reg[5] !PRE !*SleepCount_reg[6] !PRE !*SleepCount_reg[7] !PRE !*SleepCount_reg[8] !PRE !*SleepCount_reg[9] PRE !*StateReset_reg CLR "*Busy_reg CLR "* FSM_WR_reg 3CLR ـ"*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR ؀"*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR ܀"*!FSM_sequential_StateJTAGIO_reg[0] 1CLR ۀ"*!FSM_sequential_StateJTAGIO_reg[1] 1CLR ڀ"*!FSM_sequential_StateJTAGIO_reg[2] 2CLR ׀"*"FSM_sequential_StateJTAGTDO_reg[0] 2CLR ր"*"FSM_sequential_StateJTAGTDO_reg[1] CLR "*TCK_in_rise_reg CLR "*TCKi_sync_reg[2] CLR "*TDOi_sync_reg[0] CLR "*TDOi_sync_reg[1] CLR "*TDOi_sync_reg[2] CLR "*TDOi_sync_reg[3] CLR "*TDOi_sync_reg[4] $CLR ā"*TMS_StateCurr_reg[0] $CLR Á"*TMS_StateCurr_reg[1] $CLR "*TMS_StateCurr_reg[2] $CLR "*TMS_StateCurr_reg[3] CLR "*TRst_reg CLR "*TimeoutError_reg #CLR "*gotoState_Start_reg !CLR "*rdBitCount_reg[0] "CLR "*rdBitCount_reg[10] "CLR "*rdBitCount_reg[11] "CLR "*rdBitCount_reg[12] "CLR "*rdBitCount_reg[13] "CLR "*rdBitCount_reg[14] "CLR "*rdBitCount_reg[15] !CLR "*rdBitCount_reg[1] !CLR "*rdBitCount_reg[2] !CLR "*rdBitCount_reg[3] !CLR "*rdBitCount_reg[4] !CLR "*rdBitCount_reg[5] !CLR "*rdBitCount_reg[6] !CLR "*rdBitCount_reg[7] !CLR "*rdBitCount_reg[8] !CLR "*rdBitCount_reg[9] CLR "*tclk_cnt_reg[0] CLR "*tclk_cnt_reg[1] CLR "*tclk_cnt_reg[2] CLR "*tclk_cnt_reg[3] CLR "*tclk_cnt_reg[4] CLR "*tclk_cnt_reg[5] CLR "*tclk_cnt_reg[6] CLR "*tclk_cnt_reg[7] #CLR "*tmsStateCntr_reg[0] #CLR "*tmsStateCntr_reg[1] #CLR "*tmsStateCntr_reg[2] #CLR "*tmsStateCntr_reg[3] PRE "*TCK_reg PRE "*TDI_reg PRE "*TMSo_reg %PRE "*gotoState_DoneTDO_reg "PRE "*gotoState_Done_reg "PRE "*timeoutCntr_reg[0] #PRE "*timeoutCntr_reg[10] #PRE "*timeoutCntr_reg[11] #PRE "*timeoutCntr_reg[12] #PRE "*timeoutCntr_reg[13] #PRE "*timeoutCntr_reg[14] "PRE "*timeoutCntr_reg[1] "PRE "*timeoutCntr_reg[2] "PRE "*timeoutCntr_reg[3] "PRE "*timeoutCntr_reg[4] "PRE "*timeoutCntr_reg[5] "PRE "*timeoutCntr_reg[6] "PRE "*timeoutCntr_reg[7] "PRE "*timeoutCntr_reg[8] "PRE "*timeoutCntr_reg[9].%Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#378B LUT cell SFP_GEN[42].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[42].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[42].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.3 1"%FSM_sequential_StateJTAGTDO[1]_i_3__8 ** CLR "*BitCount_reg[0] CLR "*BitCount_reg[10] CLR "*BitCount_reg[11] CLR "*BitCount_reg[12] CLR "*BitCount_reg[13] CLR "*BitCount_reg[14] CLR "*BitCount_reg[15] CLR "*BitCount_reg[1] CLR "*BitCount_reg[2] CLR "*BitCount_reg[3] CLR "*BitCount_reg[4] CLR "*BitCount_reg[5] CLR "*BitCount_reg[6] CLR "*BitCount_reg[7] CLR "*BitCount_reg[8] CLR "*BitCount_reg[9] CLR "*ClkDiv_o_reg[0] CLR "*ClkDiv_o_reg[1] CLR "*ClkDiv_o_reg[2] CLR "*ClkDiv_o_reg[3] CLR "*Count_o_reg[0] CLR "*Count_o_reg[10] CLR "*Count_o_reg[11] CLR "*Count_o_reg[12] CLR "*Count_o_reg[13] CLR "*Count_o_reg[14] CLR "*Count_o_reg[15] CLR "*Count_o_reg[1] CLR "*Count_o_reg[2] CLR "*Count_o_reg[3] CLR "*Count_o_reg[4] CLR "*Count_o_reg[5] CLR "*Count_o_reg[6] CLR "*Count_o_reg[7] CLR "*Count_o_reg[8] CLR "*Count_o_reg[9] CLR "*DoCapture_o_reg CLR "* DoSleep_reg CLR "* JTAGStart_reg CLR "*StateEnd_reg[0] CLR "*StateEnd_reg[1] CLR "*StateEnd_reg[2] CLR "*StateEnd_reg[3] CLR "*StateReset_o_reg PRE "* ClkDiv_reg[0] PRE "* ClkDiv_reg[1] PRE "* ClkDiv_reg[2] PRE "* ClkDiv_reg[3] #PRE "*JTAGIgnoreTDO_o_reg !PRE "*JTAGIgnoreTDO_reg !PRE "*SleepCount_reg[0] "PRE "*SleepCount_reg[10] "PRE "*SleepCount_reg[11] "PRE "*SleepCount_reg[12] "PRE "*SleepCount_reg[13] "PRE "*SleepCount_reg[14] "PRE "*SleepCount_reg[15] "PRE "*SleepCount_reg[16] "PRE "*SleepCount_reg[17] "PRE "*SleepCount_reg[18] "PRE "*SleepCount_reg[19] !PRE "*SleepCount_reg[1] "PRE "*SleepCount_reg[20] "PRE "*SleepCount_reg[21] "PRE "*SleepCount_reg[22] "PRE "*SleepCount_reg[23] "PRE "*SleepCount_reg[24] "PRE "*SleepCount_reg[25] "PRE "*SleepCount_reg[26] "PRE "*SleepCount_reg[27] "PRE "*SleepCount_reg[28] "PRE "*SleepCount_reg[29] !PRE "*SleepCount_reg[2] "PRE "*SleepCount_reg[30] "PRE "*SleepCount_reg[31] !PRE "*SleepCount_reg[3] !PRE "*SleepCount_reg[4] !PRE "*SleepCount_reg[5] !PRE "*SleepCount_reg[6] !PRE "*SleepCount_reg[7] !PRE "*SleepCount_reg[8] !PRE "*SleepCount_reg[9] PRE "*StateReset_reg CLR "*Busy_reg CLR "* FSM_WR_reg 3CLR "*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR "*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR "*!FSM_sequential_StateJTAGIO_reg[0] 1CLR "*!FSM_sequential_StateJTAGIO_reg[1] 1CLR "*!FSM_sequential_StateJTAGIO_reg[2] 2CLR "*"FSM_sequential_StateJTAGTDO_reg[0] 2CLR "*"FSM_sequential_StateJTAGTDO_reg[1] CLR "*TCK_in_rise_reg CLR "*TCKi_sync_reg[2] CLR "*TDOi_sync_reg[0] CLR "*TDOi_sync_reg[1] CLR "*TDOi_sync_reg[2] CLR "*TDOi_sync_reg[3] CLR "*TDOi_sync_reg[4] $CLR "*TMS_StateCurr_reg[0] $CLR "*TMS_StateCurr_reg[1] $CLR "*TMS_StateCurr_reg[2] $CLR "*TMS_StateCurr_reg[3] CLR "*TRst_reg CLR "*TimeoutError_reg #CLR "*gotoState_Start_reg !CLR "*rdBitCount_reg[0] "CLR "*rdBitCount_reg[10] "CLR "*rdBitCount_reg[11] "CLR "*rdBitCount_reg[12] "CLR "*rdBitCount_reg[13] "CLR "*rdBitCount_reg[14] "CLR "*rdBitCount_reg[15] !CLR "*rdBitCount_reg[1] !CLR "*rdBitCount_reg[2] !CLR "*rdBitCount_reg[3] !CLR "*rdBitCount_reg[4] !CLR "*rdBitCount_reg[5] !CLR "*rdBitCount_reg[6] !CLR "*rdBitCount_reg[7] !CLR "*rdBitCount_reg[8] !CLR "*rdBitCount_reg[9] CLR "*tclk_cnt_reg[0] CLR "*tclk_cnt_reg[1] CLR "*tclk_cnt_reg[2] CLR "*tclk_cnt_reg[3] CLR "*tclk_cnt_reg[4] CLR "*tclk_cnt_reg[5] CLR "*tclk_cnt_reg[6] CLR "*tclk_cnt_reg[7] #CLR "*tmsStateCntr_reg[0] #CLR "*tmsStateCntr_reg[1] #CLR "*tmsStateCntr_reg[2] #CLR "*tmsStateCntr_reg[3] PRE "*TCK_reg PRE "*TDI_reg PRE "*TMSo_reg %PRE "*gotoState_DoneTDO_reg "PRE "*gotoState_Done_reg "PRE "*timeoutCntr_reg[0] #PRE "*timeoutCntr_reg[10] #PRE "*timeoutCntr_reg[11] #PRE "*timeoutCntr_reg[12] #PRE "*timeoutCntr_reg[13] #PRE "*timeoutCntr_reg[14] "PRE "*timeoutCntr_reg[1] "PRE "*timeoutCntr_reg[2] "PRE "*timeoutCntr_reg[3] "PRE "*timeoutCntr_reg[4] "PRE "*timeoutCntr_reg[5] "PRE "*timeoutCntr_reg[6] "PRE "*timeoutCntr_reg[7] "PRE "*timeoutCntr_reg[8] "PRE "*timeoutCntr_reg[9].&Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#388B LUT cell SFP_GEN[43].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[43].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[43].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.3 1#%FSM_sequential_StateJTAGTDO[1]_i_3__9 ** CLR #*BitCount_reg[0] CLR #*BitCount_reg[10] CLR #*BitCount_reg[11] CLR #*BitCount_reg[12] CLR #*BitCount_reg[13] CLR #*BitCount_reg[14] CLR #*BitCount_reg[15] CLR #*BitCount_reg[1] CLR #*BitCount_reg[2] CLR #*BitCount_reg[3] CLR #*BitCount_reg[4] CLR #*BitCount_reg[5] CLR #*BitCount_reg[6] CLR #*BitCount_reg[7] CLR #*BitCount_reg[8] CLR #*BitCount_reg[9] CLR #*ClkDiv_o_reg[0] CLR #*ClkDiv_o_reg[1] CLR #*ClkDiv_o_reg[2] CLR #*ClkDiv_o_reg[3] CLR #*Count_o_reg[0] CLR #*Count_o_reg[10] CLR #*Count_o_reg[11] CLR #*Count_o_reg[12] CLR #*Count_o_reg[13] CLR #*Count_o_reg[14] CLR #*Count_o_reg[15] CLR #*Count_o_reg[1] CLR #*Count_o_reg[2] CLR #*Count_o_reg[3] CLR #*Count_o_reg[4] CLR #*Count_o_reg[5] CLR #*Count_o_reg[6] CLR #*Count_o_reg[7] CLR #*Count_o_reg[8] CLR #*Count_o_reg[9] CLR #*DoCapture_o_reg CLR #* DoSleep_reg CLR #* JTAGStart_reg CLR #*StateEnd_reg[0] CLR #*StateEnd_reg[1] CLR #*StateEnd_reg[2] CLR #*StateEnd_reg[3] CLR #*StateReset_o_reg PRE #* ClkDiv_reg[0] PRE #* ClkDiv_reg[1] PRE #* ClkDiv_reg[2] PRE #* ClkDiv_reg[3] #PRE #*JTAGIgnoreTDO_o_reg !PRE #*JTAGIgnoreTDO_reg !PRE #*SleepCount_reg[0] "PRE #*SleepCount_reg[10] "PRE #*SleepCount_reg[11] "PRE #*SleepCount_reg[12] "PRE #*SleepCount_reg[13] "PRE #*SleepCount_reg[14] "PRE #*SleepCount_reg[15] "PRE #*SleepCount_reg[16] "PRE #*SleepCount_reg[17] "PRE #*SleepCount_reg[18] "PRE #*SleepCount_reg[19] !PRE #*SleepCount_reg[1] "PRE #*SleepCount_reg[20] "PRE #*SleepCount_reg[21] "PRE #*SleepCount_reg[22] "PRE #*SleepCount_reg[23] "PRE #*SleepCount_reg[24] "PRE #*SleepCount_reg[25] "PRE #*SleepCount_reg[26] "PRE #*SleepCount_reg[27] "PRE #*SleepCount_reg[28] "PRE #*SleepCount_reg[29] !PRE #*SleepCount_reg[2] "PRE #*SleepCount_reg[30] "PRE #*SleepCount_reg[31] !PRE #*SleepCount_reg[3] !PRE #*SleepCount_reg[4] !PRE #*SleepCount_reg[5] !PRE #*SleepCount_reg[6] !PRE #*SleepCount_reg[7] !PRE #*SleepCount_reg[8] !PRE #*SleepCount_reg[9] PRE #*StateReset_reg CLR #*Busy_reg CLR #* FSM_WR_reg 3CLR #*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR #*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR #*!FSM_sequential_StateJTAGIO_reg[0] 1CLR #*!FSM_sequential_StateJTAGIO_reg[1] 1CLR #*!FSM_sequential_StateJTAGIO_reg[2] 2CLR #*"FSM_sequential_StateJTAGTDO_reg[0] 2CLR #*"FSM_sequential_StateJTAGTDO_reg[1] CLR #*TCK_in_rise_reg CLR #*TCKi_sync_reg[2] CLR #*TDOi_sync_reg[0] CLR #*TDOi_sync_reg[1] CLR #*TDOi_sync_reg[2] CLR #*TDOi_sync_reg[3] CLR #*TDOi_sync_reg[4] $CLR #*TMS_StateCurr_reg[0] $CLR #*TMS_StateCurr_reg[1] $CLR #*TMS_StateCurr_reg[2] $CLR #*TMS_StateCurr_reg[3] CLR #*TRst_reg CLR #*TimeoutError_reg #CLR #*gotoState_Start_reg !CLR #*rdBitCount_reg[0] "CLR #*rdBitCount_reg[10] "CLR #*rdBitCount_reg[11] "CLR #*rdBitCount_reg[12] "CLR #*rdBitCount_reg[13] "CLR #*rdBitCount_reg[14] "CLR #*rdBitCount_reg[15] !CLR #*rdBitCount_reg[1] !CLR #*rdBitCount_reg[2] !CLR #*rdBitCount_reg[3] !CLR #*rdBitCount_reg[4] !CLR #*rdBitCount_reg[5] !CLR #*rdBitCount_reg[6] !CLR #*rdBitCount_reg[7] !CLR #*rdBitCount_reg[8] !CLR #*rdBitCount_reg[9] CLR #*tclk_cnt_reg[0] CLR #*tclk_cnt_reg[1] CLR #*tclk_cnt_reg[2] CLR #*tclk_cnt_reg[3] CLR #*tclk_cnt_reg[4] CLR #*tclk_cnt_reg[5] CLR #*tclk_cnt_reg[6] CLR #*tclk_cnt_reg[7] #CLR #*tmsStateCntr_reg[0] #CLR #*tmsStateCntr_reg[1] #CLR #*tmsStateCntr_reg[2] #CLR #*tmsStateCntr_reg[3] PRE #*TCK_reg PRE #*TDI_reg PRE #*TMSo_reg %PRE #*gotoState_DoneTDO_reg "PRE #*gotoState_Done_reg "PRE #*timeoutCntr_reg[0] #PRE #*timeoutCntr_reg[10] #PRE #*timeoutCntr_reg[11] #PRE #*timeoutCntr_reg[12] #PRE #*timeoutCntr_reg[13] #PRE #*timeoutCntr_reg[14] "PRE #*timeoutCntr_reg[1] "PRE #*timeoutCntr_reg[2] "PRE #*timeoutCntr_reg[3] "PRE #*timeoutCntr_reg[4] "PRE #*timeoutCntr_reg[5] "PRE #*timeoutCntr_reg[6] "PRE #*timeoutCntr_reg[7] "PRE #*timeoutCntr_reg[8] "PRE #*timeoutCntr_reg[9]1'Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#398B LUT cell SFP_GEN[44].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[44].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[44].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2$&FSM_sequential_StateJTAGTDO[1]_i_3__45 ** CLR $*BitCount_reg[0] CLR $*BitCount_reg[10] CLR $*BitCount_reg[11] CLR $*BitCount_reg[12] CLR $*BitCount_reg[13] CLR $*BitCount_reg[14] CLR $*BitCount_reg[15] CLR $*BitCount_reg[1] CLR $*BitCount_reg[2] CLR $*BitCount_reg[3] CLR $*BitCount_reg[4] CLR $*BitCount_reg[5] CLR $*BitCount_reg[6] CLR $*BitCount_reg[7] CLR $*BitCount_reg[8] CLR $*BitCount_reg[9] CLR $*ClkDiv_o_reg[0] CLR $*ClkDiv_o_reg[1] CLR $*ClkDiv_o_reg[2] CLR $*ClkDiv_o_reg[3] CLR $*Count_o_reg[0] CLR $*Count_o_reg[10] CLR $*Count_o_reg[11] CLR $*Count_o_reg[12] CLR $*Count_o_reg[13] CLR $*Count_o_reg[14] CLR $*Count_o_reg[15] CLR $*Count_o_reg[1] CLR $*Count_o_reg[2] CLR $*Count_o_reg[3] CLR $*Count_o_reg[4] CLR $*Count_o_reg[5] CLR $*Count_o_reg[6] CLR $*Count_o_reg[7] CLR $*Count_o_reg[8] CLR $*Count_o_reg[9] CLR $*DoCapture_o_reg CLR $* DoSleep_reg CLR $* JTAGStart_reg CLR $*StateEnd_reg[0] CLR $*StateEnd_reg[1] CLR $*StateEnd_reg[2] CLR $*StateEnd_reg[3] CLR $*StateReset_o_reg PRE $* ClkDiv_reg[0] PRE $* ClkDiv_reg[1] PRE $* ClkDiv_reg[2] PRE $* ClkDiv_reg[3] #PRE $*JTAGIgnoreTDO_o_reg !PRE $*JTAGIgnoreTDO_reg !PRE $*SleepCount_reg[0] "PRE $*SleepCount_reg[10] "PRE $*SleepCount_reg[11] "PRE $*SleepCount_reg[12] "PRE $*SleepCount_reg[13] "PRE $*SleepCount_reg[14] "PRE $*SleepCount_reg[15] "PRE $*SleepCount_reg[16] "PRE $*SleepCount_reg[17] "PRE $*SleepCount_reg[18] "PRE $*SleepCount_reg[19] !PRE $*SleepCount_reg[1] "PRE $*SleepCount_reg[20] "PRE $*SleepCount_reg[21] "PRE $*SleepCount_reg[22] "PRE $*SleepCount_reg[23] "PRE $*SleepCount_reg[24] "PRE $*SleepCount_reg[25] "PRE $*SleepCount_reg[26] "PRE $*SleepCount_reg[27] "PRE $*SleepCount_reg[28] "PRE $*SleepCount_reg[29] !PRE $*SleepCount_reg[2] "PRE $*SleepCount_reg[30] "PRE $*SleepCount_reg[31] !PRE $*SleepCount_reg[3] !PRE $*SleepCount_reg[4] !PRE $*SleepCount_reg[5] !PRE $*SleepCount_reg[6] !PRE $*SleepCount_reg[7] !PRE $*SleepCount_reg[8] !PRE $*SleepCount_reg[9] PRE $*StateReset_reg CLR $*Busy_reg CLR $* FSM_WR_reg 3CLR $*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR $*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR $*!FSM_sequential_StateJTAGIO_reg[0] 1CLR $*!FSM_sequential_StateJTAGIO_reg[1] 1CLR $*!FSM_sequential_StateJTAGIO_reg[2] 2CLR $*"FSM_sequential_StateJTAGTDO_reg[0] 2CLR $*"FSM_sequential_StateJTAGTDO_reg[1] CLR $*TCK_in_rise_reg CLR $*TCKi_sync_reg[2] CLR $*TDOi_sync_reg[0] CLR $*TDOi_sync_reg[1] CLR $*TDOi_sync_reg[2] CLR $*TDOi_sync_reg[3] CLR $*TDOi_sync_reg[4] $CLR $*TMS_StateCurr_reg[0] $CLR $*TMS_StateCurr_reg[1] $CLR $*TMS_StateCurr_reg[2] $CLR $*TMS_StateCurr_reg[3] CLR $*TRst_reg CLR $*TimeoutError_reg #CLR $*gotoState_Start_reg !CLR $*rdBitCount_reg[0] "CLR $*rdBitCount_reg[10] "CLR $*rdBitCount_reg[11] "CLR $*rdBitCount_reg[12] "CLR $*rdBitCount_reg[13] "CLR $*rdBitCount_reg[14] "CLR $*rdBitCount_reg[15] !CLR $*rdBitCount_reg[1] !CLR $*rdBitCount_reg[2] !CLR $*rdBitCount_reg[3] !CLR $*rdBitCount_reg[4] !CLR $*rdBitCount_reg[5] !CLR $*rdBitCount_reg[6] !CLR $*rdBitCount_reg[7] !CLR $*rdBitCount_reg[8] !CLR $*rdBitCount_reg[9] CLR $*tclk_cnt_reg[0] CLR $*tclk_cnt_reg[1] CLR $*tclk_cnt_reg[2] CLR $*tclk_cnt_reg[3] CLR $*tclk_cnt_reg[4] CLR $*tclk_cnt_reg[5] CLR $*tclk_cnt_reg[6] CLR $*tclk_cnt_reg[7] #CLR $*tmsStateCntr_reg[0] #CLR $*tmsStateCntr_reg[1] #CLR $*tmsStateCntr_reg[2] #CLR $*tmsStateCntr_reg[3] PRE $*TCK_reg PRE $*TDI_reg PRE $*TMSo_reg %PRE $*gotoState_DoneTDO_reg "PRE $*gotoState_Done_reg "PRE $*timeoutCntr_reg[0] #PRE $*timeoutCntr_reg[10] #PRE $*timeoutCntr_reg[11] #PRE $*timeoutCntr_reg[12] #PRE $*timeoutCntr_reg[13] #PRE $*timeoutCntr_reg[14] "PRE $*timeoutCntr_reg[1] "PRE $*timeoutCntr_reg[2] "PRE $*timeoutCntr_reg[3] "PRE $*timeoutCntr_reg[4] "PRE $*timeoutCntr_reg[5] "PRE $*timeoutCntr_reg[6] "PRE $*timeoutCntr_reg[7] "PRE $*timeoutCntr_reg[8] "PRE $*timeoutCntr_reg[9]1(Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#408B LUT cell SFP_GEN[45].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[45].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[45].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2%&FSM_sequential_StateJTAGTDO[1]_i_3__11 ** CLR %*BitCount_reg[0] CLR %*BitCount_reg[10] CLR %*BitCount_reg[11] CLR %*BitCount_reg[12] CLR %*BitCount_reg[13] CLR %*BitCount_reg[14] CLR %*BitCount_reg[15] CLR %*BitCount_reg[1] CLR %*BitCount_reg[2] CLR %*BitCount_reg[3] CLR %*BitCount_reg[4] CLR %*BitCount_reg[5] CLR %*BitCount_reg[6] CLR %*BitCount_reg[7] CLR %*BitCount_reg[8] CLR %*BitCount_reg[9] CLR %*ClkDiv_o_reg[0] CLR %*ClkDiv_o_reg[1] CLR %*ClkDiv_o_reg[2] CLR %*ClkDiv_o_reg[3] CLR %*Count_o_reg[0] CLR %*Count_o_reg[10] CLR %*Count_o_reg[11] CLR %*Count_o_reg[12] CLR %*Count_o_reg[13] CLR %*Count_o_reg[14] CLR %*Count_o_reg[15] CLR %*Count_o_reg[1] CLR %*Count_o_reg[2] CLR %*Count_o_reg[3] CLR %*Count_o_reg[4] CLR %*Count_o_reg[5] CLR %*Count_o_reg[6] CLR %*Count_o_reg[7] CLR %*Count_o_reg[8] CLR %*Count_o_reg[9] CLR %*DoCapture_o_reg CLR %* DoSleep_reg CLR %* JTAGStart_reg CLR %*StateEnd_reg[0] CLR %*StateEnd_reg[1] CLR %*StateEnd_reg[2] CLR %*StateEnd_reg[3] CLR %*StateReset_o_reg PRE %* ClkDiv_reg[0] PRE %* ClkDiv_reg[1] PRE %* ClkDiv_reg[2] PRE %* ClkDiv_reg[3] #PRE %*JTAGIgnoreTDO_o_reg !PRE %*JTAGIgnoreTDO_reg !PRE %*SleepCount_reg[0] "PRE %*SleepCount_reg[10] "PRE %*SleepCount_reg[11] "PRE %*SleepCount_reg[12] "PRE %*SleepCount_reg[13] "PRE %*SleepCount_reg[14] "PRE %*SleepCount_reg[15] "PRE %*SleepCount_reg[16] "PRE %*SleepCount_reg[17] "PRE %*SleepCount_reg[18] "PRE %*SleepCount_reg[19] !PRE %*SleepCount_reg[1] "PRE %*SleepCount_reg[20] "PRE %*SleepCount_reg[21] "PRE %*SleepCount_reg[22] "PRE %*SleepCount_reg[23] "PRE %*SleepCount_reg[24] "PRE %*SleepCount_reg[25] "PRE %*SleepCount_reg[26] "PRE %*SleepCount_reg[27] "PRE %*SleepCount_reg[28] "PRE %*SleepCount_reg[29] !PRE %*SleepCount_reg[2] "PRE %*SleepCount_reg[30] "PRE %*SleepCount_reg[31] !PRE %*SleepCount_reg[3] !PRE %*SleepCount_reg[4] !PRE %*SleepCount_reg[5] !PRE %*SleepCount_reg[6] !PRE %*SleepCount_reg[7] !PRE %*SleepCount_reg[8] !PRE %*SleepCount_reg[9] PRE %*StateReset_reg CLR %*Busy_reg CLR %* FSM_WR_reg 3CLR %*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR %*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR %*!FSM_sequential_StateJTAGIO_reg[0] 1CLR %*!FSM_sequential_StateJTAGIO_reg[1] 1CLR %*!FSM_sequential_StateJTAGIO_reg[2] 2CLR %*"FSM_sequential_StateJTAGTDO_reg[0] 2CLR %*"FSM_sequential_StateJTAGTDO_reg[1] CLR %*TCK_in_rise_reg CLR %*TCKi_sync_reg[2] CLR %*TDOi_sync_reg[0] CLR %*TDOi_sync_reg[1] CLR %*TDOi_sync_reg[2] CLR %*TDOi_sync_reg[3] CLR %*TDOi_sync_reg[4] $CLR %*TMS_StateCurr_reg[0] $CLR %*TMS_StateCurr_reg[1] $CLR %*TMS_StateCurr_reg[2] $CLR %*TMS_StateCurr_reg[3] CLR %*TRst_reg CLR %*TimeoutError_reg #CLR %*gotoState_Start_reg !CLR %*rdBitCount_reg[0] "CLR %*rdBitCount_reg[10] "CLR %*rdBitCount_reg[11] "CLR %*rdBitCount_reg[12] "CLR %*rdBitCount_reg[13] "CLR %*rdBitCount_reg[14] "CLR %*rdBitCount_reg[15] !CLR %*rdBitCount_reg[1] !CLR %*rdBitCount_reg[2] !CLR %*rdBitCount_reg[3] !CLR %*rdBitCount_reg[4] !CLR %*rdBitCount_reg[5] !CLR %*rdBitCount_reg[6] !CLR %*rdBitCount_reg[7] !CLR %*rdBitCount_reg[8] !CLR %*rdBitCount_reg[9] CLR %*tclk_cnt_reg[0] CLR %*tclk_cnt_reg[1] CLR %*tclk_cnt_reg[2] CLR %*tclk_cnt_reg[3] CLR %*tclk_cnt_reg[4] CLR %*tclk_cnt_reg[5] CLR %*tclk_cnt_reg[6] CLR %*tclk_cnt_reg[7] #CLR %*tmsStateCntr_reg[0] #CLR %*tmsStateCntr_reg[1] #CLR %*tmsStateCntr_reg[2] #CLR %*tmsStateCntr_reg[3] PRE %*TCK_reg PRE %*TDI_reg PRE %*TMSo_reg %PRE %*gotoState_DoneTDO_reg "PRE %*gotoState_Done_reg "PRE %*timeoutCntr_reg[0] #PRE %*timeoutCntr_reg[10] #PRE %*timeoutCntr_reg[11] #PRE %*timeoutCntr_reg[12] #PRE %*timeoutCntr_reg[13] #PRE %*timeoutCntr_reg[14] "PRE %*timeoutCntr_reg[1] "PRE %*timeoutCntr_reg[2] "PRE %*timeoutCntr_reg[3] "PRE %*timeoutCntr_reg[4] "PRE %*timeoutCntr_reg[5] "PRE %*timeoutCntr_reg[6] "PRE %*timeoutCntr_reg[7] "PRE %*timeoutCntr_reg[8] "PRE %*timeoutCntr_reg[9]1)Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#418B LUT cell SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[46].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[46].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2&&FSM_sequential_StateJTAGTDO[1]_i_3__46 ** CLR &*BitCount_reg[0] CLR &*BitCount_reg[10] CLR &*BitCount_reg[11] CLR &*BitCount_reg[12] CLR &*BitCount_reg[13] CLR &*BitCount_reg[14] CLR &*BitCount_reg[15] CLR &*BitCount_reg[1] CLR &*BitCount_reg[2] CLR &*BitCount_reg[3] CLR &*BitCount_reg[4] CLR &*BitCount_reg[5] CLR &*BitCount_reg[6] CLR &*BitCount_reg[7] CLR &*BitCount_reg[8] CLR &*BitCount_reg[9] CLR &*ClkDiv_o_reg[0] CLR &*ClkDiv_o_reg[1] CLR &*ClkDiv_o_reg[2] CLR &*ClkDiv_o_reg[3] CLR &*Count_o_reg[0] CLR &*Count_o_reg[10] CLR &*Count_o_reg[11] CLR &*Count_o_reg[12] CLR &*Count_o_reg[13] CLR &*Count_o_reg[14] CLR &*Count_o_reg[15] CLR &*Count_o_reg[1] CLR &*Count_o_reg[2] CLR &*Count_o_reg[3] CLR &*Count_o_reg[4] CLR &*Count_o_reg[5] CLR &*Count_o_reg[6] CLR &*Count_o_reg[7] CLR &*Count_o_reg[8] CLR &*Count_o_reg[9] CLR &*DoCapture_o_reg CLR &* DoSleep_reg CLR &* JTAGStart_reg CLR &*StateEnd_reg[0] CLR &*StateEnd_reg[1] CLR &*StateEnd_reg[2] CLR &*StateEnd_reg[3] CLR &*StateReset_o_reg PRE &* ClkDiv_reg[0] PRE &* ClkDiv_reg[1] PRE &* ClkDiv_reg[2] PRE &* ClkDiv_reg[3] #PRE &*JTAGIgnoreTDO_o_reg !PRE &*JTAGIgnoreTDO_reg !PRE &*SleepCount_reg[0] "PRE &*SleepCount_reg[10] "PRE &*SleepCount_reg[11] "PRE &*SleepCount_reg[12] "PRE &*SleepCount_reg[13] "PRE &*SleepCount_reg[14] "PRE &*SleepCount_reg[15] "PRE &*SleepCount_reg[16] "PRE &*SleepCount_reg[17] "PRE &*SleepCount_reg[18] "PRE &*SleepCount_reg[19] !PRE &*SleepCount_reg[1] "PRE &*SleepCount_reg[20] "PRE &*SleepCount_reg[21] "PRE &*SleepCount_reg[22] "PRE &*SleepCount_reg[23] "PRE &*SleepCount_reg[24] "PRE &*SleepCount_reg[25] "PRE &*SleepCount_reg[26] "PRE &*SleepCount_reg[27] "PRE &*SleepCount_reg[28] "PRE &*SleepCount_reg[29] !PRE &*SleepCount_reg[2] "PRE &*SleepCount_reg[30] "PRE &*SleepCount_reg[31] !PRE &*SleepCount_reg[3] !PRE &*SleepCount_reg[4] !PRE &*SleepCount_reg[5] !PRE &*SleepCount_reg[6] !PRE &*SleepCount_reg[7] !PRE &*SleepCount_reg[8] !PRE &*SleepCount_reg[9] PRE &*StateReset_reg CLR &*Busy_reg CLR &* FSM_WR_reg 3CLR &*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR &*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR &*!FSM_sequential_StateJTAGIO_reg[0] 1CLR &*!FSM_sequential_StateJTAGIO_reg[1] 1CLR &*!FSM_sequential_StateJTAGIO_reg[2] 2CLR &*"FSM_sequential_StateJTAGTDO_reg[0] 2CLR &*"FSM_sequential_StateJTAGTDO_reg[1] CLR &*TCK_in_rise_reg CLR &*TCKi_sync_reg[2] CLR &*TDOi_sync_reg[0] CLR &*TDOi_sync_reg[1] CLR &*TDOi_sync_reg[2] CLR &*TDOi_sync_reg[3] CLR &*TDOi_sync_reg[4] $CLR &*TMS_StateCurr_reg[0] $CLR &*TMS_StateCurr_reg[1] $CLR &*TMS_StateCurr_reg[2] $CLR &*TMS_StateCurr_reg[3] CLR &*TRst_reg CLR &*TimeoutError_reg #CLR &*gotoState_Start_reg !CLR &*rdBitCount_reg[0] "CLR &*rdBitCount_reg[10] "CLR &*rdBitCount_reg[11] "CLR &*rdBitCount_reg[12] "CLR &*rdBitCount_reg[13] "CLR &*rdBitCount_reg[14] "CLR &*rdBitCount_reg[15] !CLR &*rdBitCount_reg[1] !CLR &*rdBitCount_reg[2] !CLR &*rdBitCount_reg[3] !CLR &*rdBitCount_reg[4] !CLR &*rdBitCount_reg[5] !CLR &*rdBitCount_reg[6] !CLR &*rdBitCount_reg[7] !CLR &*rdBitCount_reg[8] !CLR &*rdBitCount_reg[9] CLR &*tclk_cnt_reg[0] CLR &*tclk_cnt_reg[1] CLR &*tclk_cnt_reg[2] CLR &*tclk_cnt_reg[3] CLR &*tclk_cnt_reg[4] CLR &*tclk_cnt_reg[5] CLR &*tclk_cnt_reg[6] CLR &*tclk_cnt_reg[7] #CLR &*tmsStateCntr_reg[0] #CLR &*tmsStateCntr_reg[1] #CLR &*tmsStateCntr_reg[2] #CLR &*tmsStateCntr_reg[3] PRE &*TCK_reg PRE &*TDI_reg PRE &*TMSo_reg %PRE &*gotoState_DoneTDO_reg "PRE &*gotoState_Done_reg "PRE &*timeoutCntr_reg[0] #PRE &*timeoutCntr_reg[10] #PRE &*timeoutCntr_reg[11] #PRE &*timeoutCntr_reg[12] #PRE &*timeoutCntr_reg[13] #PRE &*timeoutCntr_reg[14] "PRE &*timeoutCntr_reg[1] "PRE &*timeoutCntr_reg[2] "PRE &*timeoutCntr_reg[3] "PRE &*timeoutCntr_reg[4] "PRE &*timeoutCntr_reg[5] "PRE &*timeoutCntr_reg[6] "PRE &*timeoutCntr_reg[7] "PRE &*timeoutCntr_reg[8] "PRE &*timeoutCntr_reg[9]1*Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#428B LUT cell SFP_GEN[47].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[47].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[47].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2'&FSM_sequential_StateJTAGTDO[1]_i_3__10 ** CLR '*BitCount_reg[0] CLR '*BitCount_reg[10] CLR '*BitCount_reg[11] CLR '*BitCount_reg[12] CLR '*BitCount_reg[13] CLR '*BitCount_reg[14] CLR '*BitCount_reg[15] CLR '*BitCount_reg[1] CLR '*BitCount_reg[2] CLR '*BitCount_reg[3] CLR '*BitCount_reg[4] CLR '*BitCount_reg[5] CLR '*BitCount_reg[6] CLR '*BitCount_reg[7] CLR '*BitCount_reg[8] CLR '*BitCount_reg[9] CLR '*ClkDiv_o_reg[0] CLR '*ClkDiv_o_reg[1] CLR '*ClkDiv_o_reg[2] CLR '*ClkDiv_o_reg[3] CLR '*Count_o_reg[0] CLR '*Count_o_reg[10] CLR '*Count_o_reg[11] CLR '*Count_o_reg[12] CLR '*Count_o_reg[13] CLR '*Count_o_reg[14] CLR '*Count_o_reg[15] CLR '*Count_o_reg[1] CLR '*Count_o_reg[2] CLR '*Count_o_reg[3] CLR '*Count_o_reg[4] CLR '*Count_o_reg[5] CLR '*Count_o_reg[6] CLR '*Count_o_reg[7] CLR '*Count_o_reg[8] CLR '*Count_o_reg[9] CLR '*DoCapture_o_reg CLR '* DoSleep_reg CLR '* JTAGStart_reg CLR '*StateEnd_reg[0] CLR '*StateEnd_reg[1] CLR '*StateEnd_reg[2] CLR '*StateEnd_reg[3] CLR '*StateReset_o_reg PRE '* ClkDiv_reg[0] PRE '* ClkDiv_reg[1] PRE '* ClkDiv_reg[2] PRE '* ClkDiv_reg[3] #PRE '*JTAGIgnoreTDO_o_reg !PRE '*JTAGIgnoreTDO_reg !PRE '*SleepCount_reg[0] "PRE '*SleepCount_reg[10] "PRE '*SleepCount_reg[11] "PRE '*SleepCount_reg[12] "PRE '*SleepCount_reg[13] "PRE '*SleepCount_reg[14] "PRE '*SleepCount_reg[15] "PRE '*SleepCount_reg[16] "PRE '*SleepCount_reg[17] "PRE '*SleepCount_reg[18] "PRE '*SleepCount_reg[19] !PRE '*SleepCount_reg[1] "PRE '*SleepCount_reg[20] "PRE '*SleepCount_reg[21] "PRE '*SleepCount_reg[22] "PRE '*SleepCount_reg[23] "PRE '*SleepCount_reg[24] "PRE '*SleepCount_reg[25] "PRE '*SleepCount_reg[26] "PRE '*SleepCount_reg[27] "PRE '*SleepCount_reg[28] "PRE '*SleepCount_reg[29] !PRE '*SleepCount_reg[2] "PRE '*SleepCount_reg[30] "PRE '*SleepCount_reg[31] !PRE '*SleepCount_reg[3] !PRE '*SleepCount_reg[4] !PRE '*SleepCount_reg[5] !PRE '*SleepCount_reg[6] !PRE '*SleepCount_reg[7] !PRE '*SleepCount_reg[8] !PRE '*SleepCount_reg[9] PRE '*StateReset_reg CLR '*Busy_reg CLR '* FSM_WR_reg 3CLR '*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR '*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR '*!FSM_sequential_StateJTAGIO_reg[0] 1CLR '*!FSM_sequential_StateJTAGIO_reg[1] 1CLR '*!FSM_sequential_StateJTAGIO_reg[2] 2CLR '*"FSM_sequential_StateJTAGTDO_reg[0] 2CLR '*"FSM_sequential_StateJTAGTDO_reg[1] CLR '*TCK_in_rise_reg CLR '*TCKi_sync_reg[2] CLR '*TDOi_sync_reg[0] CLR '*TDOi_sync_reg[1] CLR '*TDOi_sync_reg[2] CLR '*TDOi_sync_reg[3] CLR '*TDOi_sync_reg[4] $CLR '*TMS_StateCurr_reg[0] $CLR '*TMS_StateCurr_reg[1] $CLR '*TMS_StateCurr_reg[2] $CLR '*TMS_StateCurr_reg[3] CLR '*TRst_reg CLR '*TimeoutError_reg #CLR '*gotoState_Start_reg !CLR '*rdBitCount_reg[0] "CLR '*rdBitCount_reg[10] "CLR '*rdBitCount_reg[11] "CLR '*rdBitCount_reg[12] "CLR '*rdBitCount_reg[13] "CLR '*rdBitCount_reg[14] "CLR '*rdBitCount_reg[15] !CLR '*rdBitCount_reg[1] !CLR '*rdBitCount_reg[2] !CLR '*rdBitCount_reg[3] !CLR '*rdBitCount_reg[4] !CLR '*rdBitCount_reg[5] !CLR '*rdBitCount_reg[6] !CLR '*rdBitCount_reg[7] !CLR '*rdBitCount_reg[8] !CLR '*rdBitCount_reg[9] CLR '*tclk_cnt_reg[0] CLR '*tclk_cnt_reg[1] CLR '*tclk_cnt_reg[2] CLR '*tclk_cnt_reg[3] CLR '*tclk_cnt_reg[4] CLR '*tclk_cnt_reg[5] CLR '*tclk_cnt_reg[6] CLR '*tclk_cnt_reg[7] #CLR '*tmsStateCntr_reg[0] #CLR '*tmsStateCntr_reg[1] #CLR '*tmsStateCntr_reg[2] #CLR '*tmsStateCntr_reg[3] PRE '*TCK_reg PRE '*TDI_reg PRE '*TMSo_reg %PRE '*gotoState_DoneTDO_reg "PRE '*gotoState_Done_reg "PRE '*timeoutCntr_reg[0] #PRE '*timeoutCntr_reg[10] #PRE '*timeoutCntr_reg[11] #PRE '*timeoutCntr_reg[12] #PRE '*timeoutCntr_reg[13] #PRE '*timeoutCntr_reg[14] "PRE '*timeoutCntr_reg[1] "PRE '*timeoutCntr_reg[2] "PRE '*timeoutCntr_reg[3] "PRE '*timeoutCntr_reg[4] "PRE '*timeoutCntr_reg[5] "PRE '*timeoutCntr_reg[6] "PRE '*timeoutCntr_reg[7] "PRE '*timeoutCntr_reg[8] "PRE '*timeoutCntr_reg[9]+Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#438B LUT cell SFP_GEN[4].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[4].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2(&FSM_sequential_StateJTAGTDO[1]_i_3__30 ** CLR (*BitCount_reg[0] CLR (*BitCount_reg[10] CLR (*BitCount_reg[11] CLR (*BitCount_reg[12] CLR (*BitCount_reg[13] CLR (*BitCount_reg[14] CLR (*BitCount_reg[15] CLR (*BitCount_reg[1] CLR (*BitCount_reg[2] CLR (*BitCount_reg[3] CLR (*BitCount_reg[4] CLR (*BitCount_reg[5] CLR (*BitCount_reg[6] CLR (*BitCount_reg[7] CLR (*BitCount_reg[8] CLR (*BitCount_reg[9] CLR (*ClkDiv_o_reg[0] CLR (*ClkDiv_o_reg[1] CLR (*ClkDiv_o_reg[2] CLR (*ClkDiv_o_reg[3] CLR (*Count_o_reg[0] CLR (*Count_o_reg[10] CLR (*Count_o_reg[11] CLR (*Count_o_reg[12] CLR (*Count_o_reg[13] CLR (*Count_o_reg[14] CLR (*Count_o_reg[15] CLR (*Count_o_reg[1] CLR (*Count_o_reg[2] CLR (*Count_o_reg[3] CLR (*Count_o_reg[4] CLR (*Count_o_reg[5] CLR (*Count_o_reg[6] CLR (*Count_o_reg[7] CLR (*Count_o_reg[8] CLR (*Count_o_reg[9] CLR (*DoCapture_o_reg CLR (* DoSleep_reg CLR (* JTAGStart_reg CLR (*StateEnd_reg[0] CLR (*StateEnd_reg[1] CLR (*StateEnd_reg[2] CLR (*StateEnd_reg[3] CLR (*StateReset_o_reg PRE (* ClkDiv_reg[0] PRE (* ClkDiv_reg[1] PRE (* ClkDiv_reg[2] PRE (* ClkDiv_reg[3] #PRE (*JTAGIgnoreTDO_o_reg !PRE (*JTAGIgnoreTDO_reg !PRE (*SleepCount_reg[0] "PRE (*SleepCount_reg[10] "PRE (*SleepCount_reg[11] "PRE (*SleepCount_reg[12] "PRE (*SleepCount_reg[13] "PRE (*SleepCount_reg[14] "PRE (*SleepCount_reg[15] "PRE (*SleepCount_reg[16] "PRE (*SleepCount_reg[17] "PRE (*SleepCount_reg[18] "PRE (*SleepCount_reg[19] !PRE (*SleepCount_reg[1] "PRE (*SleepCount_reg[20] "PRE (*SleepCount_reg[21] "PRE (*SleepCount_reg[22] "PRE (*SleepCount_reg[23] "PRE (*SleepCount_reg[24] "PRE (*SleepCount_reg[25] "PRE (*SleepCount_reg[26] "PRE (*SleepCount_reg[27] "PRE (*SleepCount_reg[28] "PRE (*SleepCount_reg[29] !PRE (*SleepCount_reg[2] "PRE (*SleepCount_reg[30] "PRE (*SleepCount_reg[31] !PRE (*SleepCount_reg[3] !PRE (*SleepCount_reg[4] !PRE (*SleepCount_reg[5] !PRE (*SleepCount_reg[6] !PRE (*SleepCount_reg[7] !PRE (*SleepCount_reg[8] !PRE (*SleepCount_reg[9] PRE (*StateReset_reg CLR (*Busy_reg CLR (* FSM_WR_reg 3CLR (*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR (*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR (*!FSM_sequential_StateJTAGIO_reg[0] 1CLR (*!FSM_sequential_StateJTAGIO_reg[1] 1CLR (*!FSM_sequential_StateJTAGIO_reg[2] 2CLR (*"FSM_sequential_StateJTAGTDO_reg[0] 2CLR (*"FSM_sequential_StateJTAGTDO_reg[1] CLR (*TCK_in_rise_reg CLR (*TCKi_sync_reg[2] CLR (*TDOi_sync_reg[0] CLR (*TDOi_sync_reg[1] CLR (*TDOi_sync_reg[2] CLR (*TDOi_sync_reg[3] CLR (*TDOi_sync_reg[4] $CLR (*TMS_StateCurr_reg[0] $CLR (*TMS_StateCurr_reg[1] $CLR (*TMS_StateCurr_reg[2] $CLR (*TMS_StateCurr_reg[3] CLR (*TRst_reg CLR (*TimeoutError_reg #CLR (*gotoState_Start_reg !CLR (*rdBitCount_reg[0] "CLR (*rdBitCount_reg[10] "CLR (*rdBitCount_reg[11] "CLR (*rdBitCount_reg[12] "CLR (*rdBitCount_reg[13] "CLR (*rdBitCount_reg[14] "CLR (*rdBitCount_reg[15] !CLR (*rdBitCount_reg[1] !CLR (*rdBitCount_reg[2] !CLR (*rdBitCount_reg[3] !CLR (*rdBitCount_reg[4] !CLR (*rdBitCount_reg[5] !CLR (*rdBitCount_reg[6] !CLR (*rdBitCount_reg[7] !CLR (*rdBitCount_reg[8] !CLR (*rdBitCount_reg[9] CLR (*tclk_cnt_reg[0] CLR (*tclk_cnt_reg[1] CLR (*tclk_cnt_reg[2] CLR (*tclk_cnt_reg[3] CLR (*tclk_cnt_reg[4] CLR (*tclk_cnt_reg[5] CLR (*tclk_cnt_reg[6] CLR (*tclk_cnt_reg[7] #CLR (*tmsStateCntr_reg[0] #CLR (*tmsStateCntr_reg[1] #CLR (*tmsStateCntr_reg[2] #CLR (*tmsStateCntr_reg[3] PRE (*TCK_reg PRE (*TDI_reg PRE (*TMSo_reg %PRE (*gotoState_DoneTDO_reg "PRE (*gotoState_Done_reg "PRE (*timeoutCntr_reg[0] #PRE (*timeoutCntr_reg[10] #PRE (*timeoutCntr_reg[11] #PRE (*timeoutCntr_reg[12] #PRE (*timeoutCntr_reg[13] #PRE (*timeoutCntr_reg[14] "PRE (*timeoutCntr_reg[1] "PRE (*timeoutCntr_reg[2] "PRE (*timeoutCntr_reg[3] "PRE (*timeoutCntr_reg[4] "PRE (*timeoutCntr_reg[5] "PRE (*timeoutCntr_reg[6] "PRE (*timeoutCntr_reg[7] "PRE (*timeoutCntr_reg[8] "PRE (*timeoutCntr_reg[9],Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#448B LUT cell SFP_GEN[5].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[5].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2)&FSM_sequential_StateJTAGTDO[1]_i_3__13 ** CLR )*BitCount_reg[0] CLR )*BitCount_reg[10] CLR )*BitCount_reg[11] CLR )*BitCount_reg[12] CLR )*BitCount_reg[13] CLR )*BitCount_reg[14] CLR )*BitCount_reg[15] CLR )*BitCount_reg[1] CLR )*BitCount_reg[2] CLR )*BitCount_reg[3] CLR )*BitCount_reg[4] CLR )*BitCount_reg[5] CLR )*BitCount_reg[6] CLR )*BitCount_reg[7] CLR )*BitCount_reg[8] CLR )*BitCount_reg[9] CLR )*ClkDiv_o_reg[0] CLR )*ClkDiv_o_reg[1] CLR )*ClkDiv_o_reg[2] CLR )*ClkDiv_o_reg[3] CLR )*Count_o_reg[0] CLR )*Count_o_reg[10] CLR )*Count_o_reg[11] CLR )*Count_o_reg[12] CLR )*Count_o_reg[13] CLR )*Count_o_reg[14] CLR )*Count_o_reg[15] CLR )*Count_o_reg[1] CLR )*Count_o_reg[2] CLR )*Count_o_reg[3] CLR )*Count_o_reg[4] CLR )*Count_o_reg[5] CLR )*Count_o_reg[6] CLR )*Count_o_reg[7] CLR )*Count_o_reg[8] CLR )*Count_o_reg[9] CLR )*DoCapture_o_reg CLR )* DoSleep_reg CLR )* JTAGStart_reg CLR )*StateEnd_reg[0] CLR )*StateEnd_reg[1] CLR )*StateEnd_reg[2] CLR )*StateEnd_reg[3] CLR )*StateReset_o_reg PRE )* ClkDiv_reg[0] PRE )* ClkDiv_reg[1] PRE )* ClkDiv_reg[2] PRE )* ClkDiv_reg[3] #PRE )*JTAGIgnoreTDO_o_reg !PRE )*JTAGIgnoreTDO_reg !PRE )*SleepCount_reg[0] "PRE )*SleepCount_reg[10] "PRE )*SleepCount_reg[11] "PRE )*SleepCount_reg[12] "PRE )*SleepCount_reg[13] "PRE )*SleepCount_reg[14] "PRE )*SleepCount_reg[15] "PRE )*SleepCount_reg[16] "PRE )*SleepCount_reg[17] "PRE )*SleepCount_reg[18] "PRE )*SleepCount_reg[19] !PRE )*SleepCount_reg[1] "PRE )*SleepCount_reg[20] "PRE )*SleepCount_reg[21] "PRE )*SleepCount_reg[22] "PRE )*SleepCount_reg[23] "PRE )*SleepCount_reg[24] "PRE )*SleepCount_reg[25] "PRE )*SleepCount_reg[26] "PRE )*SleepCount_reg[27] "PRE )*SleepCount_reg[28] "PRE )*SleepCount_reg[29] !PRE )*SleepCount_reg[2] "PRE )*SleepCount_reg[30] "PRE )*SleepCount_reg[31] !PRE )*SleepCount_reg[3] !PRE )*SleepCount_reg[4] !PRE )*SleepCount_reg[5] !PRE )*SleepCount_reg[6] !PRE )*SleepCount_reg[7] !PRE )*SleepCount_reg[8] !PRE )*SleepCount_reg[9] PRE )*StateReset_reg CLR )*Busy_reg CLR )* FSM_WR_reg 3CLR )*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR )*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR )*!FSM_sequential_StateJTAGIO_reg[0] 1CLR )*!FSM_sequential_StateJTAGIO_reg[1] 1CLR )*!FSM_sequential_StateJTAGIO_reg[2] 2CLR )*"FSM_sequential_StateJTAGTDO_reg[0] 2CLR )*"FSM_sequential_StateJTAGTDO_reg[1] CLR )*TCK_in_rise_reg CLR )*TCKi_sync_reg[2] CLR )*TDOi_sync_reg[0] CLR )*TDOi_sync_reg[1] CLR )*TDOi_sync_reg[2] CLR )*TDOi_sync_reg[3] CLR )*TDOi_sync_reg[4] $CLR )*TMS_StateCurr_reg[0] $CLR )*TMS_StateCurr_reg[1] $CLR )*TMS_StateCurr_reg[2] $CLR )*TMS_StateCurr_reg[3] CLR )*TRst_reg CLR )*TimeoutError_reg #CLR )*gotoState_Start_reg !CLR )*rdBitCount_reg[0] "CLR )*rdBitCount_reg[10] "CLR )*rdBitCount_reg[11] "CLR )*rdBitCount_reg[12] "CLR )*rdBitCount_reg[13] "CLR )*rdBitCount_reg[14] "CLR )*rdBitCount_reg[15] !CLR )*rdBitCount_reg[1] !CLR )*rdBitCount_reg[2] !CLR )*rdBitCount_reg[3] !CLR )*rdBitCount_reg[4] !CLR )*rdBitCount_reg[5] !CLR )*rdBitCount_reg[6] !CLR )*rdBitCount_reg[7] !CLR )*rdBitCount_reg[8] !CLR )*rdBitCount_reg[9] CLR )*tclk_cnt_reg[0] CLR )*tclk_cnt_reg[1] CLR )*tclk_cnt_reg[2] CLR )*tclk_cnt_reg[3] CLR )*tclk_cnt_reg[4] CLR )*tclk_cnt_reg[5] CLR )*tclk_cnt_reg[6] CLR )*tclk_cnt_reg[7] #CLR )*tmsStateCntr_reg[0] #CLR )*tmsStateCntr_reg[1] #CLR )*tmsStateCntr_reg[2] #CLR )*tmsStateCntr_reg[3] PRE )*TCK_reg PRE )*TDI_reg PRE )*TMSo_reg %PRE )*gotoState_DoneTDO_reg "PRE )*gotoState_Done_reg "PRE )*timeoutCntr_reg[0] #PRE )*timeoutCntr_reg[10] #PRE )*timeoutCntr_reg[11] #PRE )*timeoutCntr_reg[12] #PRE )*timeoutCntr_reg[13] #PRE )*timeoutCntr_reg[14] "PRE )*timeoutCntr_reg[1] "PRE )*timeoutCntr_reg[2] "PRE )*timeoutCntr_reg[3] "PRE )*timeoutCntr_reg[4] "PRE )*timeoutCntr_reg[5] "PRE )*timeoutCntr_reg[6] "PRE )*timeoutCntr_reg[7] "PRE )*timeoutCntr_reg[8] "PRE )*timeoutCntr_reg[9]-Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#458B LUT cell SFP_GEN[6].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[6].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2*&FSM_sequential_StateJTAGTDO[1]_i_3__28 ** CLR **BitCount_reg[0] CLR **BitCount_reg[10] CLR **BitCount_reg[11] CLR **BitCount_reg[12] CLR **BitCount_reg[13] CLR **BitCount_reg[14] CLR **BitCount_reg[15] CLR **BitCount_reg[1] CLR **BitCount_reg[2] CLR **BitCount_reg[3] CLR **BitCount_reg[4] CLR **BitCount_reg[5] CLR **BitCount_reg[6] CLR **BitCount_reg[7] CLR **BitCount_reg[8] CLR **BitCount_reg[9] CLR **ClkDiv_o_reg[0] CLR **ClkDiv_o_reg[1] CLR **ClkDiv_o_reg[2] CLR **ClkDiv_o_reg[3] CLR **Count_o_reg[0] CLR **Count_o_reg[10] CLR **Count_o_reg[11] CLR **Count_o_reg[12] CLR **Count_o_reg[13] CLR **Count_o_reg[14] CLR **Count_o_reg[15] CLR **Count_o_reg[1] CLR **Count_o_reg[2] CLR **Count_o_reg[3] CLR **Count_o_reg[4] CLR **Count_o_reg[5] CLR **Count_o_reg[6] CLR **Count_o_reg[7] CLR **Count_o_reg[8] CLR **Count_o_reg[9] CLR **DoCapture_o_reg CLR ** DoSleep_reg CLR ** JTAGStart_reg CLR **StateEnd_reg[0] CLR **StateEnd_reg[1] CLR **StateEnd_reg[2] CLR **StateEnd_reg[3] CLR **StateReset_o_reg PRE ** ClkDiv_reg[0] PRE ** ClkDiv_reg[1] PRE ** ClkDiv_reg[2] PRE ** ClkDiv_reg[3] #PRE **JTAGIgnoreTDO_o_reg !PRE **JTAGIgnoreTDO_reg !PRE **SleepCount_reg[0] "PRE **SleepCount_reg[10] "PRE **SleepCount_reg[11] "PRE **SleepCount_reg[12] "PRE **SleepCount_reg[13] "PRE **SleepCount_reg[14] "PRE **SleepCount_reg[15] "PRE **SleepCount_reg[16] "PRE **SleepCount_reg[17] "PRE **SleepCount_reg[18] "PRE **SleepCount_reg[19] !PRE **SleepCount_reg[1] "PRE **SleepCount_reg[20] "PRE **SleepCount_reg[21] "PRE **SleepCount_reg[22] "PRE **SleepCount_reg[23] "PRE **SleepCount_reg[24] "PRE **SleepCount_reg[25] "PRE **SleepCount_reg[26] "PRE **SleepCount_reg[27] "PRE **SleepCount_reg[28] "PRE **SleepCount_reg[29] !PRE **SleepCount_reg[2] "PRE **SleepCount_reg[30] "PRE **SleepCount_reg[31] !PRE **SleepCount_reg[3] !PRE **SleepCount_reg[4] !PRE **SleepCount_reg[5] !PRE **SleepCount_reg[6] !PRE **SleepCount_reg[7] !PRE **SleepCount_reg[8] !PRE **SleepCount_reg[9] PRE **StateReset_reg CLR **Busy_reg CLR ** FSM_WR_reg 3CLR **#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR **#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR **!FSM_sequential_StateJTAGIO_reg[0] 1CLR **!FSM_sequential_StateJTAGIO_reg[1] 1CLR **!FSM_sequential_StateJTAGIO_reg[2] 2CLR **"FSM_sequential_StateJTAGTDO_reg[0] 2CLR **"FSM_sequential_StateJTAGTDO_reg[1] CLR **TCK_in_rise_reg CLR **TCKi_sync_reg[2] CLR **TDOi_sync_reg[0] CLR **TDOi_sync_reg[1] CLR **TDOi_sync_reg[2] CLR **TDOi_sync_reg[3] CLR **TDOi_sync_reg[4] $CLR **TMS_StateCurr_reg[0] $CLR **TMS_StateCurr_reg[1] $CLR **TMS_StateCurr_reg[2] $CLR **TMS_StateCurr_reg[3] CLR **TRst_reg CLR **TimeoutError_reg #CLR **gotoState_Start_reg !CLR **rdBitCount_reg[0] "CLR **rdBitCount_reg[10] "CLR **rdBitCount_reg[11] "CLR **rdBitCount_reg[12] "CLR **rdBitCount_reg[13] "CLR **rdBitCount_reg[14] "CLR **rdBitCount_reg[15] !CLR **rdBitCount_reg[1] !CLR **rdBitCount_reg[2] !CLR **rdBitCount_reg[3] !CLR **rdBitCount_reg[4] !CLR **rdBitCount_reg[5] !CLR **rdBitCount_reg[6] !CLR **rdBitCount_reg[7] !CLR **rdBitCount_reg[8] !CLR **rdBitCount_reg[9] CLR **tclk_cnt_reg[0] CLR **tclk_cnt_reg[1] CLR **tclk_cnt_reg[2] CLR **tclk_cnt_reg[3] CLR **tclk_cnt_reg[4] CLR **tclk_cnt_reg[5] CLR **tclk_cnt_reg[6] CLR **tclk_cnt_reg[7] #CLR **tmsStateCntr_reg[0] #CLR **tmsStateCntr_reg[1] #CLR **tmsStateCntr_reg[2] #CLR **tmsStateCntr_reg[3] PRE **TCK_reg PRE **TDI_reg PRE **TMSo_reg %PRE **gotoState_DoneTDO_reg "PRE **gotoState_Done_reg "PRE **timeoutCntr_reg[0] #PRE **timeoutCntr_reg[10] #PRE **timeoutCntr_reg[11] #PRE **timeoutCntr_reg[12] #PRE **timeoutCntr_reg[13] #PRE **timeoutCntr_reg[14] "PRE **timeoutCntr_reg[1] "PRE **timeoutCntr_reg[2] "PRE **timeoutCntr_reg[3] "PRE **timeoutCntr_reg[4] "PRE **timeoutCntr_reg[5] "PRE **timeoutCntr_reg[6] "PRE **timeoutCntr_reg[7] "PRE **timeoutCntr_reg[8] "PRE **timeoutCntr_reg[9].Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#468B LUT cell SFP_GEN[7].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[7].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2+&FSM_sequential_StateJTAGTDO[1]_i_3__16 ** CLR +*BitCount_reg[0] CLR +*BitCount_reg[10] CLR +*BitCount_reg[11] CLR +*BitCount_reg[12] CLR +*BitCount_reg[13] CLR +*BitCount_reg[14] CLR +*BitCount_reg[15] CLR +*BitCount_reg[1] CLR +*BitCount_reg[2] CLR +*BitCount_reg[3] CLR +*BitCount_reg[4] CLR +*BitCount_reg[5] CLR +*BitCount_reg[6] CLR +*BitCount_reg[7] CLR +*BitCount_reg[8] CLR +*BitCount_reg[9] CLR +*ClkDiv_o_reg[0] CLR +*ClkDiv_o_reg[1] CLR +*ClkDiv_o_reg[2] CLR +*ClkDiv_o_reg[3] CLR +*Count_o_reg[0] CLR +*Count_o_reg[10] CLR +*Count_o_reg[11] CLR +*Count_o_reg[12] CLR +*Count_o_reg[13] CLR +*Count_o_reg[14] CLR +*Count_o_reg[15] CLR +*Count_o_reg[1] CLR +*Count_o_reg[2] CLR +*Count_o_reg[3] CLR +*Count_o_reg[4] CLR +*Count_o_reg[5] CLR +*Count_o_reg[6] CLR +*Count_o_reg[7] CLR +*Count_o_reg[8] CLR +*Count_o_reg[9] CLR +*DoCapture_o_reg CLR +* DoSleep_reg CLR +* JTAGStart_reg CLR +*StateEnd_reg[0] CLR +*StateEnd_reg[1] CLR +*StateEnd_reg[2] CLR +*StateEnd_reg[3] CLR +*StateReset_o_reg PRE +* ClkDiv_reg[0] PRE +* ClkDiv_reg[1] PRE +* ClkDiv_reg[2] PRE +* ClkDiv_reg[3] #PRE +*JTAGIgnoreTDO_o_reg !PRE +*JTAGIgnoreTDO_reg !PRE +*SleepCount_reg[0] "PRE +*SleepCount_reg[10] "PRE +*SleepCount_reg[11] "PRE +*SleepCount_reg[12] "PRE +*SleepCount_reg[13] "PRE +*SleepCount_reg[14] "PRE +*SleepCount_reg[15] "PRE +*SleepCount_reg[16] "PRE +*SleepCount_reg[17] "PRE +*SleepCount_reg[18] "PRE +*SleepCount_reg[19] !PRE +*SleepCount_reg[1] "PRE +*SleepCount_reg[20] "PRE +*SleepCount_reg[21] "PRE +*SleepCount_reg[22] "PRE +*SleepCount_reg[23] "PRE +*SleepCount_reg[24] "PRE +*SleepCount_reg[25] "PRE +*SleepCount_reg[26] "PRE +*SleepCount_reg[27] "PRE +*SleepCount_reg[28] "PRE +*SleepCount_reg[29] !PRE +*SleepCount_reg[2] "PRE +*SleepCount_reg[30] "PRE +*SleepCount_reg[31] !PRE +*SleepCount_reg[3] !PRE +*SleepCount_reg[4] !PRE +*SleepCount_reg[5] !PRE +*SleepCount_reg[6] !PRE +*SleepCount_reg[7] !PRE +*SleepCount_reg[8] !PRE +*SleepCount_reg[9] PRE +*StateReset_reg CLR +*Busy_reg CLR +* FSM_WR_reg 3CLR +*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR +*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR +*!FSM_sequential_StateJTAGIO_reg[0] 1CLR +*!FSM_sequential_StateJTAGIO_reg[1] 1CLR +*!FSM_sequential_StateJTAGIO_reg[2] 2CLR +*"FSM_sequential_StateJTAGTDO_reg[0] 2CLR +*"FSM_sequential_StateJTAGTDO_reg[1] CLR +*TCK_in_rise_reg CLR +*TCKi_sync_reg[2] CLR +*TDOi_sync_reg[0] CLR +*TDOi_sync_reg[1] CLR +*TDOi_sync_reg[2] CLR +*TDOi_sync_reg[3] CLR +*TDOi_sync_reg[4] $CLR +*TMS_StateCurr_reg[0] $CLR +*TMS_StateCurr_reg[1] $CLR +*TMS_StateCurr_reg[2] $CLR +*TMS_StateCurr_reg[3] CLR +*TRst_reg CLR +*TimeoutError_reg #CLR +*gotoState_Start_reg !CLR +*rdBitCount_reg[0] "CLR +*rdBitCount_reg[10] "CLR +*rdBitCount_reg[11] "CLR +*rdBitCount_reg[12] "CLR +*rdBitCount_reg[13] "CLR +*rdBitCount_reg[14] "CLR +*rdBitCount_reg[15] !CLR +*rdBitCount_reg[1] !CLR +*rdBitCount_reg[2] !CLR +*rdBitCount_reg[3] !CLR +*rdBitCount_reg[4] !CLR +*rdBitCount_reg[5] !CLR +*rdBitCount_reg[6] !CLR +*rdBitCount_reg[7] !CLR +*rdBitCount_reg[8] !CLR +*rdBitCount_reg[9] CLR +*tclk_cnt_reg[0] CLR +*tclk_cnt_reg[1] CLR +*tclk_cnt_reg[2] CLR +*tclk_cnt_reg[3] CLR +*tclk_cnt_reg[4] CLR +*tclk_cnt_reg[5] CLR +*tclk_cnt_reg[6] CLR +*tclk_cnt_reg[7] #CLR +*tmsStateCntr_reg[0] #CLR +*tmsStateCntr_reg[1] #CLR +*tmsStateCntr_reg[2] #CLR +*tmsStateCntr_reg[3] PRE +*TCK_reg PRE +*TDI_reg PRE +*TMSo_reg %PRE +*gotoState_DoneTDO_reg "PRE +*gotoState_Done_reg "PRE +*timeoutCntr_reg[0] #PRE +*timeoutCntr_reg[10] #PRE +*timeoutCntr_reg[11] #PRE +*timeoutCntr_reg[12] #PRE +*timeoutCntr_reg[13] #PRE +*timeoutCntr_reg[14] "PRE +*timeoutCntr_reg[1] "PRE +*timeoutCntr_reg[2] "PRE +*timeoutCntr_reg[3] "PRE +*timeoutCntr_reg[4] "PRE +*timeoutCntr_reg[5] "PRE +*timeoutCntr_reg[6] "PRE +*timeoutCntr_reg[7] "PRE +*timeoutCntr_reg[8] "PRE +*timeoutCntr_reg[9]/Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#478B LUT cell SFP_GEN[8].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[8].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2,&FSM_sequential_StateJTAGTDO[1]_i_3__35 ** CLR ,*BitCount_reg[0] CLR ,*BitCount_reg[10] CLR ,*BitCount_reg[11] CLR ,*BitCount_reg[12] CLR ,*BitCount_reg[13] CLR ,*BitCount_reg[14] CLR ,*BitCount_reg[15] CLR ,*BitCount_reg[1] CLR ,*BitCount_reg[2] CLR ,*BitCount_reg[3] CLR ,*BitCount_reg[4] CLR ,*BitCount_reg[5] CLR ,*BitCount_reg[6] CLR ,*BitCount_reg[7] CLR ,*BitCount_reg[8] CLR ,*BitCount_reg[9] CLR ߾,*ClkDiv_o_reg[0] CLR ޾,*ClkDiv_o_reg[1] CLR ݾ,*ClkDiv_o_reg[2] CLR ܾ,*ClkDiv_o_reg[3] CLR ,*Count_o_reg[0] CLR ,*Count_o_reg[10] CLR ,*Count_o_reg[11] CLR ,*Count_o_reg[12] CLR ,*Count_o_reg[13] CLR ,*Count_o_reg[14] CLR ,*Count_o_reg[15] CLR ,*Count_o_reg[1] CLR ,*Count_o_reg[2] CLR ,*Count_o_reg[3] CLR ,*Count_o_reg[4] CLR ,*Count_o_reg[5] CLR ,*Count_o_reg[6] CLR ,*Count_o_reg[7] CLR ,*Count_o_reg[8] CLR ,*Count_o_reg[9] CLR ,*DoCapture_o_reg CLR ,* DoSleep_reg CLR ,* JTAGStart_reg CLR ,*StateEnd_reg[0] CLR ,*StateEnd_reg[1] CLR ,*StateEnd_reg[2] CLR ,*StateEnd_reg[3] CLR ۾,*StateReset_o_reg PRE ,* ClkDiv_reg[0] PRE ,* ClkDiv_reg[1] PRE ,* ClkDiv_reg[2] PRE ,* ClkDiv_reg[3] #PRE ھ,*JTAGIgnoreTDO_o_reg !PRE ,*JTAGIgnoreTDO_reg !PRE پ,*SleepCount_reg[0] "PRE Ͼ,*SleepCount_reg[10] "PRE ξ,*SleepCount_reg[11] "PRE ;,*SleepCount_reg[12] "PRE ̾,*SleepCount_reg[13] "PRE ˾,*SleepCount_reg[14] "PRE ʾ,*SleepCount_reg[15] "PRE ɾ,*SleepCount_reg[16] "PRE Ⱦ,*SleepCount_reg[17] "PRE Ǿ,*SleepCount_reg[18] "PRE ƾ,*SleepCount_reg[19] !PRE ؾ,*SleepCount_reg[1] "PRE ž,*SleepCount_reg[20] "PRE ľ,*SleepCount_reg[21] "PRE þ,*SleepCount_reg[22] "PRE ¾,*SleepCount_reg[23] "PRE ,*SleepCount_reg[24] "PRE ,*SleepCount_reg[25] "PRE ,*SleepCount_reg[26] "PRE ,*SleepCount_reg[27] "PRE ,*SleepCount_reg[28] "PRE ,*SleepCount_reg[29] !PRE ׾,*SleepCount_reg[2] "PRE ,*SleepCount_reg[30] "PRE ,*SleepCount_reg[31] !PRE ־,*SleepCount_reg[3] !PRE վ,*SleepCount_reg[4] !PRE Ծ,*SleepCount_reg[5] !PRE Ӿ,*SleepCount_reg[6] !PRE Ҿ,*SleepCount_reg[7] !PRE Ѿ,*SleepCount_reg[8] !PRE о,*SleepCount_reg[9] PRE ,*StateReset_reg CLR ,*Busy_reg CLR ,* FSM_WR_reg 3CLR ,*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR ,*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR ,*!FSM_sequential_StateJTAGIO_reg[0] 1CLR ,*!FSM_sequential_StateJTAGIO_reg[1] 1CLR ,*!FSM_sequential_StateJTAGIO_reg[2] 2CLR ,*"FSM_sequential_StateJTAGTDO_reg[0] 2CLR ,*"FSM_sequential_StateJTAGTDO_reg[1] CLR ,*TCK_in_rise_reg CLR ,*TCKi_sync_reg[2] CLR ,*TDOi_sync_reg[0] CLR ,*TDOi_sync_reg[1] CLR ,*TDOi_sync_reg[2] CLR ,*TDOi_sync_reg[3] CLR ,*TDOi_sync_reg[4] $CLR ,*TMS_StateCurr_reg[0] $CLR ,*TMS_StateCurr_reg[1] $CLR ,*TMS_StateCurr_reg[2] $CLR ,*TMS_StateCurr_reg[3] CLR ,*TRst_reg CLR ,*TimeoutError_reg #CLR ,*gotoState_Start_reg !CLR ,*rdBitCount_reg[0] "CLR ,*rdBitCount_reg[10] "CLR ,*rdBitCount_reg[11] "CLR ,*rdBitCount_reg[12] "CLR ,*rdBitCount_reg[13] "CLR ,*rdBitCount_reg[14] "CLR ,*rdBitCount_reg[15] !CLR ,*rdBitCount_reg[1] !CLR ,*rdBitCount_reg[2] !CLR ,*rdBitCount_reg[3] !CLR ,*rdBitCount_reg[4] !CLR ,*rdBitCount_reg[5] !CLR ,*rdBitCount_reg[6] !CLR ,*rdBitCount_reg[7] !CLR ,*rdBitCount_reg[8] !CLR ,*rdBitCount_reg[9] CLR ,*tclk_cnt_reg[0] CLR ,*tclk_cnt_reg[1] CLR ,*tclk_cnt_reg[2] CLR ,*tclk_cnt_reg[3] CLR ,*tclk_cnt_reg[4] CLR ,*tclk_cnt_reg[5] CLR ,*tclk_cnt_reg[6] CLR ,*tclk_cnt_reg[7] #CLR ,*tmsStateCntr_reg[0] #CLR ,*tmsStateCntr_reg[1] #CLR ,*tmsStateCntr_reg[2] #CLR ,*tmsStateCntr_reg[3] PRE ,*TCK_reg PRE ,*TDI_reg PRE ,*TMSo_reg %PRE ,*gotoState_DoneTDO_reg "PRE ,*gotoState_Done_reg "PRE ,*timeoutCntr_reg[0] #PRE ,*timeoutCntr_reg[10] #PRE ,*timeoutCntr_reg[11] #PRE ,*timeoutCntr_reg[12] #PRE ,*timeoutCntr_reg[13] #PRE ,*timeoutCntr_reg[14] "PRE ,*timeoutCntr_reg[1] "PRE ,*timeoutCntr_reg[2] "PRE ,*timeoutCntr_reg[3] "PRE ,*timeoutCntr_reg[4] "PRE ,*timeoutCntr_reg[5] "PRE ,*timeoutCntr_reg[6] "PRE ,*timeoutCntr_reg[7] "PRE ,*timeoutCntr_reg[8] "PRE ,*timeoutCntr_reg[9]0Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#488B LUT cell SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_3__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.4 2-&FSM_sequential_StateJTAGTDO[1]_i_3__14 ** CLR ͸-*BitCount_reg[0] CLR ø-*BitCount_reg[10] CLR ¸-*BitCount_reg[11] CLR -*BitCount_reg[12] CLR -*BitCount_reg[13] CLR -*BitCount_reg[14] CLR -*BitCount_reg[15] CLR ̸-*BitCount_reg[1] CLR ˸-*BitCount_reg[2] CLR ʸ-*BitCount_reg[3] CLR ɸ-*BitCount_reg[4] CLR ȸ-*BitCount_reg[5] CLR Ǹ-*BitCount_reg[6] CLR Ƹ-*BitCount_reg[7] CLR Ÿ-*BitCount_reg[8] CLR ĸ-*BitCount_reg[9] CLR -*ClkDiv_o_reg[0] CLR -*ClkDiv_o_reg[1] CLR -*ClkDiv_o_reg[2] CLR -*ClkDiv_o_reg[3] CLR -*Count_o_reg[0] CLR -*Count_o_reg[10] CLR -*Count_o_reg[11] CLR -*Count_o_reg[12] CLR -*Count_o_reg[13] CLR -*Count_o_reg[14] CLR -*Count_o_reg[15] CLR -*Count_o_reg[1] CLR -*Count_o_reg[2] CLR -*Count_o_reg[3] CLR -*Count_o_reg[4] CLR -*Count_o_reg[5] CLR -*Count_o_reg[6] CLR -*Count_o_reg[7] CLR -*Count_o_reg[8] CLR -*Count_o_reg[9] CLR -*DoCapture_o_reg CLR -* DoSleep_reg CLR -* JTAGStart_reg CLR Ҹ-*StateEnd_reg[0] CLR Ѹ-*StateEnd_reg[1] CLR и-*StateEnd_reg[2] CLR ϸ-*StateEnd_reg[3] CLR -*StateReset_o_reg PRE -* ClkDiv_reg[0] PRE -* ClkDiv_reg[1] PRE -* ClkDiv_reg[2] PRE -* ClkDiv_reg[3] #PRE -*JTAGIgnoreTDO_o_reg !PRE -*JTAGIgnoreTDO_reg !PRE -*SleepCount_reg[0] "PRE -*SleepCount_reg[10] "PRE -*SleepCount_reg[11] "PRE -*SleepCount_reg[12] "PRE -*SleepCount_reg[13] "PRE -*SleepCount_reg[14] "PRE -*SleepCount_reg[15] "PRE -*SleepCount_reg[16] "PRE -*SleepCount_reg[17] "PRE -*SleepCount_reg[18] "PRE ߸-*SleepCount_reg[19] !PRE -*SleepCount_reg[1] "PRE ޸-*SleepCount_reg[20] "PRE ݸ-*SleepCount_reg[21] "PRE ܸ-*SleepCount_reg[22] "PRE ۸-*SleepCount_reg[23] "PRE ڸ-*SleepCount_reg[24] "PRE ٸ-*SleepCount_reg[25] "PRE ظ-*SleepCount_reg[26] "PRE ׸-*SleepCount_reg[27] "PRE ָ-*SleepCount_reg[28] "PRE ո-*SleepCount_reg[29] !PRE -*SleepCount_reg[2] "PRE Ը-*SleepCount_reg[30] "PRE Ӹ-*SleepCount_reg[31] !PRE -*SleepCount_reg[3] !PRE -*SleepCount_reg[4] !PRE -*SleepCount_reg[5] !PRE -*SleepCount_reg[6] !PRE -*SleepCount_reg[7] !PRE -*SleepCount_reg[8] !PRE -*SleepCount_reg[9] PRE θ-*StateReset_reg CLR -*Busy_reg CLR -* FSM_WR_reg 3CLR -*#FSM_sequential_StateJTAGCtrl_reg[0] 3CLR -*#FSM_sequential_StateJTAGCtrl_reg[1] 1CLR -*!FSM_sequential_StateJTAGIO_reg[0] 1CLR -*!FSM_sequential_StateJTAGIO_reg[1] 1CLR -*!FSM_sequential_StateJTAGIO_reg[2] 2CLR -*"FSM_sequential_StateJTAGTDO_reg[0] 2CLR -*"FSM_sequential_StateJTAGTDO_reg[1] CLR -*TCK_in_rise_reg CLR -*TCKi_sync_reg[2] CLR ڻ-*TDOi_sync_reg[0] CLR ٻ-*TDOi_sync_reg[1] CLR ػ-*TDOi_sync_reg[2] CLR ׻-*TDOi_sync_reg[3] CLR ֻ-*TDOi_sync_reg[4] $CLR -*TMS_StateCurr_reg[0] $CLR -*TMS_StateCurr_reg[1] $CLR -*TMS_StateCurr_reg[2] $CLR -*TMS_StateCurr_reg[3] CLR -*TRst_reg CLR -*TimeoutError_reg #CLR -*gotoState_Start_reg !CLR ջ-*rdBitCount_reg[0] "CLR ˻-*rdBitCount_reg[10] "CLR ʻ-*rdBitCount_reg[11] "CLR ɻ-*rdBitCount_reg[12] "CLR Ȼ-*rdBitCount_reg[13] "CLR ǻ-*rdBitCount_reg[14] "CLR ƻ-*rdBitCount_reg[15] !CLR Ի-*rdBitCount_reg[1] !CLR ӻ-*rdBitCount_reg[2] !CLR һ-*rdBitCount_reg[3] !CLR ѻ-*rdBitCount_reg[4] !CLR л-*rdBitCount_reg[5] !CLR ϻ-*rdBitCount_reg[6] !CLR λ-*rdBitCount_reg[7] !CLR ͻ-*rdBitCount_reg[8] !CLR ̻-*rdBitCount_reg[9] CLR -*tclk_cnt_reg[0] CLR -*tclk_cnt_reg[1] CLR -*tclk_cnt_reg[2] CLR -*tclk_cnt_reg[3] CLR -*tclk_cnt_reg[4] CLR -*tclk_cnt_reg[5] CLR -*tclk_cnt_reg[6] CLR -*tclk_cnt_reg[7] #CLR -*tmsStateCntr_reg[0] #CLR -*tmsStateCntr_reg[1] #CLR -*tmsStateCntr_reg[2] #CLR -*tmsStateCntr_reg[3] PRE -*TCK_reg PRE -*TDI_reg PRE -*TMSo_reg %PRE -*gotoState_DoneTDO_reg "PRE -*gotoState_Done_reg "PRE -*timeoutCntr_reg[0] #PRE -*timeoutCntr_reg[10] #PRE -*timeoutCntr_reg[11] #PRE -*timeoutCntr_reg[12] #PRE -*timeoutCntr_reg[13] #PRE -*timeoutCntr_reg[14] "PRE -*timeoutCntr_reg[1] "PRE -*timeoutCntr_reg[2] "PRE -*timeoutCntr_reg[3] "PRE -*timeoutCntr_reg[4] "PRE -*timeoutCntr_reg[5] "PRE -*timeoutCntr_reg[6] "PRE -*timeoutCntr_reg[7] "PRE -*timeoutCntr_reg[8] "PRE -*timeoutCntr_reg[9]1Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#498BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." .genRxRstMgtClk_s_i_1 *Q $PRE /*genRxRstMgtClk_s_reg )PRE /*genRxRstMgtClk_sync_s_reg2Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#508BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.% #.genRxRstMgtClk_s_i_1__0 *Q $PRE /*genRxRstMgtClk_s_reg )PRE /*genRxRstMgtClk_sync_s_reg3Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#518BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.% #.genRxRstMgtClk_s_i_1__1 *Q $PRE /*genRxRstMgtClk_s_reg )PRE /*genRxRstMgtClk_sync_s_reg4Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#528BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__10 *Q $PRE /*genRxRstMgtClk_s_reg )PRE /*genRxRstMgtClk_sync_s_reg5Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#538BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__11 *Q $PRE 1*genRxRstMgtClk_s_reg )PRE 1*genRxRstMgtClk_sync_s_reg6Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#548BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__12 *Q $PRE 1*genRxRstMgtClk_s_reg )PRE 1*genRxRstMgtClk_sync_s_reg7Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#558BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__13 *Q $PRE 1*genRxRstMgtClk_s_reg )PRE 1*genRxRstMgtClk_sync_s_reg8Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#568BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__14 *Q $PRE 1*genRxRstMgtClk_s_reg )PRE 1*genRxRstMgtClk_sync_s_reg9Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#578BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__15 *Q $PRE 1*genRxRstMgtClk_s_reg )PRE 1*genRxRstMgtClk_sync_s_reg:Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#588BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__16 *Q $PRE 1*genRxRstMgtClk_s_reg )PRE 1*genRxRstMgtClk_sync_s_reg;Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#598BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__17 *Q $PRE 1*genRxRstMgtClk_s_reg )PRE 1*genRxRstMgtClk_sync_s_reg<Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#608BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__18 *Q $PRE 2*genRxRstMgtClk_s_reg )PRE 2*genRxRstMgtClk_sync_s_reg=Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#618BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__19 *Q $PRE 2*genRxRstMgtClk_s_reg )PRE 2*genRxRstMgtClk_sync_s_reg>Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#628BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.% #.genRxRstMgtClk_s_i_1__2 *Q $PRE /*genRxRstMgtClk_s_reg )PRE /*genRxRstMgtClk_sync_s_reg?Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#638BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__20 *Q $PRE 2*genRxRstMgtClk_s_reg )PRE 2*genRxRstMgtClk_sync_s_reg@Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#648BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__21 *Q $PRE 1*genRxRstMgtClk_s_reg )PRE 1*genRxRstMgtClk_sync_s_regAWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#658BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__22, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__22, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__22 *Q $PRE 1*genRxRstMgtClk_s_reg )PRE 1*genRxRstMgtClk_sync_s_regBWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#668BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__23 *Q $PRE 4*genRxRstMgtClk_s_reg )PRE 4*genRxRstMgtClk_sync_s_regCWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#678BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__24 *Q $PRE 4*genRxRstMgtClk_s_reg )PRE 4*genRxRstMgtClk_sync_s_regDWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#688BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__25 *Q $PRE ͏4*genRxRstMgtClk_s_reg )PRE Ώ4*genRxRstMgtClk_sync_s_regEWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#698BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__26 *Q $PRE 4*genRxRstMgtClk_s_reg )PRE 4*genRxRstMgtClk_sync_s_regFWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#708BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__27 *Q $PRE 4*genRxRstMgtClk_s_reg )PRE 4*genRxRstMgtClk_sync_s_regGWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#718BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__28 *Q $PRE 4*genRxRstMgtClk_s_reg )PRE 4*genRxRstMgtClk_sync_s_regHWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#728BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__29 *Q $PRE Ñ4*genRxRstMgtClk_s_reg )PRE đ4*genRxRstMgtClk_sync_s_regIWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#738BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.% #.genRxRstMgtClk_s_i_1__3 *Q $PRE /*genRxRstMgtClk_s_reg )PRE /*genRxRstMgtClk_sync_s_regJWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#748BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__30 *Q $PRE 4*genRxRstMgtClk_s_reg )PRE 4*genRxRstMgtClk_sync_s_regKWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#758BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__31 *Q $PRE 4*genRxRstMgtClk_s_reg )PRE 4*genRxRstMgtClk_sync_s_regLWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#768BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__32 *Q $PRE 4*genRxRstMgtClk_s_reg )PRE 4*genRxRstMgtClk_sync_s_regMWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#778BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__33 *Q $PRE 4*genRxRstMgtClk_s_reg )PRE 4*genRxRstMgtClk_sync_s_regNWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#788BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__34, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__34, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__34 *Q $PRE َ4*genRxRstMgtClk_s_reg )PRE ڎ4*genRxRstMgtClk_sync_s_regOWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#798BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__35 *Q $PRE 6*genRxRstMgtClk_s_reg )PRE 6*genRxRstMgtClk_sync_s_regPWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#808BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__36 *Q $PRE 6*genRxRstMgtClk_s_reg )PRE 6*genRxRstMgtClk_sync_s_regQWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#818BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__37 *Q $PRE ۠6*genRxRstMgtClk_s_reg )PRE ܠ6*genRxRstMgtClk_sync_s_regRWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#828BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__38 *Q $PRE 6*genRxRstMgtClk_s_reg )PRE 6*genRxRstMgtClk_sync_s_regSWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#838BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__39 *Q $PRE ϡ6*genRxRstMgtClk_s_reg )PRE С6*genRxRstMgtClk_sync_s_regTWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#848BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.% #.genRxRstMgtClk_s_i_1__4 *Q $PRE /*genRxRstMgtClk_s_reg )PRE /*genRxRstMgtClk_sync_s_regUWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#858BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__40 *Q $PRE 6*genRxRstMgtClk_s_reg )PRE 6*genRxRstMgtClk_sync_s_regVWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#868BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__41 *Q $PRE Ѣ6*genRxRstMgtClk_s_reg )PRE Ң6*genRxRstMgtClk_sync_s_regWWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#878BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__42 *Q $PRE 6*genRxRstMgtClk_s_reg )PRE 6*genRxRstMgtClk_sync_s_regXWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#888BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__43 *Q $PRE ţ6*genRxRstMgtClk_s_reg )PRE ƣ6*genRxRstMgtClk_sync_s_regYWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#898BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__44 *Q $PRE 6*genRxRstMgtClk_s_reg )PRE 6*genRxRstMgtClk_sync_s_regZWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#908BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__45 *Q $PRE 6*genRxRstMgtClk_s_reg )PRE 6*genRxRstMgtClk_sync_s_reg[Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#918BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.& $.genRxRstMgtClk_s_i_1__46 *Q $PRE 6*genRxRstMgtClk_s_reg )PRE 6*genRxRstMgtClk_sync_s_reg\Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#928BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.% #.genRxRstMgtClk_s_i_1__5 *Q $PRE /*genRxRstMgtClk_s_reg )PRE /*genRxRstMgtClk_sync_s_reg]Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#938BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.% #.genRxRstMgtClk_s_i_1__6 *Q $PRE /*genRxRstMgtClk_s_reg )PRE /*genRxRstMgtClk_sync_s_reg^Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#948BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.% #.genRxRstMgtClk_s_i_1__7 *Q $PRE /*genRxRstMgtClk_s_reg )PRE /*genRxRstMgtClk_sync_s_reg_Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#958BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.% #.genRxRstMgtClk_s_i_1__8 *Q $PRE /*genRxRstMgtClk_s_reg )PRE /*genRxRstMgtClk_sync_s_reg`Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#968BLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/genRxRstMgtClk_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.% #.genRxRstMgtClk_s_i_1__9 *Q $PRE /*genRxRstMgtClk_s_reg )PRE /*genRxRstMgtClk_sync_s_reg{JaWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#978B LUT cell ctrl_regs_inst/generalRstProcess.timer[0]_i_3__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[19]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/CLR (the first 15 of 324 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell ctrl_regs_inst/generalRstProcess.timer[0]_i_3__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[19]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/CLR, g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/CLR (the first 15 of 324 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.0 .."generalRstProcess.timer[0]_i_3__43 *y .CLR /*generalRstProcess.timer_reg[0] /CLR /*generalRstProcess.timer_reg[10] /CLR /*generalRstProcess.timer_reg[11] /CLR /*generalRstProcess.timer_reg[12] /CLR /*generalRstProcess.timer_reg[13] /CLR /*generalRstProcess.timer_reg[14] /CLR /*generalRstProcess.timer_reg[15] /CLR /*generalRstProcess.timer_reg[16] /CLR /*generalRstProcess.timer_reg[17] /CLR /*generalRstProcess.timer_reg[18] /CLR /*generalRstProcess.timer_reg[19] .CLR /*generalRstProcess.timer_reg[1] /CLR /*generalRstProcess.timer_reg[20] /CLR /*generalRstProcess.timer_reg[21] /CLR /*generalRstProcess.timer_reg[22] /CLR /*generalRstProcess.timer_reg[23] /CLR /*generalRstProcess.timer_reg[24] /CLR /*generalRstProcess.timer_reg[25] .CLR /*generalRstProcess.timer_reg[2] .CLR /*generalRstProcess.timer_reg[3] .CLR /*generalRstProcess.timer_reg[4] .CLR /*generalRstProcess.timer_reg[5] .CLR /*generalRstProcess.timer_reg[6] .CLR /*generalRstProcess.timer_reg[7] .CLR /*generalRstProcess.timer_reg[8] .CLR /*generalRstProcess.timer_reg[9] PRE /*genReset_s_reg .CLR /*generalRstProcess.timer_reg[0] /CLR /*generalRstProcess.timer_reg[10] /CLR /*generalRstProcess.timer_reg[11] /CLR /*generalRstProcess.timer_reg[12] /CLR /*generalRstProcess.timer_reg[13] /CLR /*generalRstProcess.timer_reg[14] /CLR /*generalRstProcess.timer_reg[15] /CLR /*generalRstProcess.timer_reg[16] /CLR /*generalRstProcess.timer_reg[17] /CLR /*generalRstProcess.timer_reg[18] /CLR /*generalRstProcess.timer_reg[19] .CLR /*generalRstProcess.timer_reg[1] /CLR /*generalRstProcess.timer_reg[20] /CLR /*generalRstProcess.timer_reg[21] /CLR /*generalRstProcess.timer_reg[22] /CLR /*generalRstProcess.timer_reg[23] /CLR /*generalRstProcess.timer_reg[24] /CLR /*generalRstProcess.timer_reg[25] .CLR /*generalRstProcess.timer_reg[2] .CLR /*generalRstProcess.timer_reg[3] .CLR /*generalRstProcess.timer_reg[4] .CLR /*generalRstProcess.timer_reg[5] .CLR /*generalRstProcess.timer_reg[6] .CLR /*generalRstProcess.timer_reg[7] .CLR /*generalRstProcess.timer_reg[8] .CLR /*generalRstProcess.timer_reg[9] PRE /*genReset_s_reg .CLR /*generalRstProcess.timer_reg[0] /CLR /*generalRstProcess.timer_reg[10] /CLR /*generalRstProcess.timer_reg[11] /CLR /*generalRstProcess.timer_reg[12] /CLR /*generalRstProcess.timer_reg[13] /CLR /*generalRstProcess.timer_reg[14] /CLR /*generalRstProcess.timer_reg[15] /CLR /*generalRstProcess.timer_reg[16] /CLR /*generalRstProcess.timer_reg[17] /CLR /*generalRstProcess.timer_reg[18] /CLR /*generalRstProcess.timer_reg[19] .CLR /*generalRstProcess.timer_reg[1] /CLR /*generalRstProcess.timer_reg[20] /CLR /*generalRstProcess.timer_reg[21] /CLR /*generalRstProcess.timer_reg[22] /CLR /*generalRstProcess.timer_reg[23] /CLR /*generalRstProcess.timer_reg[24] /CLR /*generalRstProcess.timer_reg[25] .CLR /*generalRstProcess.timer_reg[2] .CLR /*generalRstProcess.timer_reg[3] .CLR /*generalRstProcess.timer_reg[4] .CLR /*generalRstProcess.timer_reg[5] .CLR /*generalRstProcess.timer_reg[6] .CLR /*generalRstProcess.timer_reg[7] .CLR /*generalRstProcess.timer_reg[8] .CLR /*generalRstProcess.timer_reg[9] PRE /*genReset_s_reg .CLR /*generalRstProcess.timer_reg[0] /CLR /*generalRstProcess.timer_reg[10] /CLR /*generalRstProcess.timer_reg[11] /CLR /*generalRstProcess.timer_reg[12] /CLR /*generalRstProcess.timer_reg[13] /CLR /*generalRstProcess.timer_reg[14] /CLR /*generalRstProcess.timer_reg[15] /CLR /*generalRstProcess.timer_reg[16] /CLR /*generalRstProcess.timer_reg[17] /CLR /*generalRstProcess.timer_reg[18] /CLR /*generalRstProcess.timer_reg[19] .CLR /*generalRstProcess.timer_reg[1] /CLR /*generalRstProcess.timer_reg[20] /CLR /*generalRstProcess.timer_reg[21] /CLR /*generalRstProcess.timer_reg[22] /CLR /*generalRstProcess.timer_reg[23] /CLR /*generalRstProcess.timer_reg[24] /CLR /*generalRstProcess.timer_reg[25] .CLR /*generalRstProcess.timer_reg[2] .CLR /*generalRstProcess.timer_reg[3] .CLR /*generalRstProcess.timer_reg[4] .CLR /*generalRstProcess.timer_reg[5] .CLR /*generalRstProcess.timer_reg[6] .CLR /*generalRstProcess.timer_reg[7] .CLR /*generalRstProcess.timer_reg[8] .CLR /*generalRstProcess.timer_reg[9] PRE /*genReset_s_reg .CLR /*generalRstProcess.timer_reg[0] /CLR /*generalRstProcess.timer_reg[10] /CLR /*generalRstProcess.timer_reg[11] /CLR /*generalRstProcess.timer_reg[12] /CLR /*generalRstProcess.timer_reg[13] /CLR /*generalRstProcess.timer_reg[14] /CLR /*generalRstProcess.timer_reg[15] /CLR /*generalRstProcess.timer_reg[16] /CLR /*generalRstProcess.timer_reg[17] /CLR /*generalRstProcess.timer_reg[18] /CLR /*generalRstProcess.timer_reg[19] .CLR /*generalRstProcess.timer_reg[1] /CLR /*generalRstProcess.timer_reg[20] /CLR /*generalRstProcess.timer_reg[21] /CLR /*generalRstProcess.timer_reg[22] /CLR /*generalRstProcess.timer_reg[23] /CLR /*generalRstProcess.timer_reg[24] /CLR /*generalRstProcess.timer_reg[25] .CLR /*generalRstProcess.timer_reg[2] .CLR /*generalRstProcess.timer_reg[3] .CLR /*generalRstProcess.timer_reg[4] .CLR /*generalRstProcess.timer_reg[5] .CLR /*generalRstProcess.timer_reg[6] .CLR /*generalRstProcess.timer_reg[7] .CLR /*generalRstProcess.timer_reg[8] .CLR /*generalRstProcess.timer_reg[9] PRE /*genReset_s_reg .CLR /*generalRstProcess.timer_reg[0] /CLR /*generalRstProcess.timer_reg[10] /CLR /*generalRstProcess.timer_reg[11] /CLR /*generalRstProcess.timer_reg[12] /CLR /*generalRstProcess.timer_reg[13] /CLR /*generalRstProcess.timer_reg[14] /CLR /*generalRstProcess.timer_reg[15] /CLR /*generalRstProcess.timer_reg[16] /CLR /*generalRstProcess.timer_reg[17] /CLR /*generalRstProcess.timer_reg[18] /CLR /*generalRstProcess.timer_reg[19] .CLR /*generalRstProcess.timer_reg[1] /CLR /*generalRstProcess.timer_reg[20] /CLR /*generalRstProcess.timer_reg[21] /CLR /*generalRstProcess.timer_reg[22] /CLR /*generalRstProcess.timer_reg[23] /CLR /*generalRstProcess.timer_reg[24] /CLR /*generalRstProcess.timer_reg[25] .CLR /*generalRstProcess.timer_reg[2] .CLR /*generalRstProcess.timer_reg[3] .CLR /*generalRstProcess.timer_reg[4] .CLR /*generalRstProcess.timer_reg[5] .CLR /*generalRstProcess.timer_reg[6] .CLR /*generalRstProcess.timer_reg[7] .CLR /*generalRstProcess.timer_reg[8] .CLR /*generalRstProcess.timer_reg[9] PRE /*genReset_s_reg .CLR /*generalRstProcess.timer_reg[0] /CLR /*generalRstProcess.timer_reg[10] /CLR /*generalRstProcess.timer_reg[11] /CLR /*generalRstProcess.timer_reg[12] /CLR /*generalRstProcess.timer_reg[13] /CLR /*generalRstProcess.timer_reg[14] /CLR /*generalRstProcess.timer_reg[15] /CLR /*generalRstProcess.timer_reg[16] /CLR /*generalRstProcess.timer_reg[17] /CLR /*generalRstProcess.timer_reg[18] /CLR /*generalRstProcess.timer_reg[19] .CLR /*generalRstProcess.timer_reg[1] /CLR /*generalRstProcess.timer_reg[20] /CLR /*generalRstProcess.timer_reg[21] /CLR /*generalRstProcess.timer_reg[22] /CLR /*generalRstProcess.timer_reg[23] /CLR /*generalRstProcess.timer_reg[24] /CLR /*generalRstProcess.timer_reg[25] .CLR /*generalRstProcess.timer_reg[2] .CLR /*generalRstProcess.timer_reg[3] .CLR /*generalRstProcess.timer_reg[4] .CLR /*generalRstProcess.timer_reg[5] .CLR /*generalRstProcess.timer_reg[6] .CLR /*generalRstProcess.timer_reg[7] .CLR /*generalRstProcess.timer_reg[8] .CLR /*generalRstProcess.timer_reg[9] PRE /*genReset_s_reg .CLR /*generalRstProcess.timer_reg[0] /CLR /*generalRstProcess.timer_reg[10] /CLR /*generalRstProcess.timer_reg[11] /CLR /*generalRstProcess.timer_reg[12] /CLR /*generalRstProcess.timer_reg[13] /CLR /*generalRstProcess.timer_reg[14] /CLR /*generalRstProcess.timer_reg[15] /CLR /*generalRstProcess.timer_reg[16] /CLR /*generalRstProcess.timer_reg[17] /CLR /*generalRstProcess.timer_reg[18] /CLR /*generalRstProcess.timer_reg[19] .CLR /*generalRstProcess.timer_reg[1] /CLR /*generalRstProcess.timer_reg[20] /CLR /*generalRstProcess.timer_reg[21] /CLR /*generalRstProcess.timer_reg[22] /CLR /*generalRstProcess.timer_reg[23] /CLR /*generalRstProcess.timer_reg[24] /CLR /*generalRstProcess.timer_reg[25] .CLR /*generalRstProcess.timer_reg[2] .CLR /*generalRstProcess.timer_reg[3] .CLR /*generalRstProcess.timer_reg[4] .CLR /*generalRstProcess.timer_reg[5] .CLR /*generalRstProcess.timer_reg[6] .CLR /*generalRstProcess.timer_reg[7] .CLR /*generalRstProcess.timer_reg[8] .CLR /*generalRstProcess.timer_reg[9] PRE /*genReset_s_reg .CLR /*generalRstProcess.timer_reg[0] /CLR /*generalRstProcess.timer_reg[10] /CLR /*generalRstProcess.timer_reg[11] /CLR /*generalRstProcess.timer_reg[12] /CLR /*generalRstProcess.timer_reg[13] /CLR /*generalRstProcess.timer_reg[14] /CLR /*generalRstProcess.timer_reg[15] /CLR /*generalRstProcess.timer_reg[16] /CLR /*generalRstProcess.timer_reg[17] /CLR /*generalRstProcess.timer_reg[18] /CLR /*generalRstProcess.timer_reg[19] .CLR /*generalRstProcess.timer_reg[1] /CLR /*generalRstProcess.timer_reg[20] /CLR /*generalRstProcess.timer_reg[21] /CLR /*generalRstProcess.timer_reg[22] /CLR /*generalRstProcess.timer_reg[23] /CLR /*generalRstProcess.timer_reg[24] /CLR /*generalRstProcess.timer_reg[25] .CLR /*generalRstProcess.timer_reg[2] .CLR /*generalRstProcess.timer_reg[3] .CLR /*generalRstProcess.timer_reg[4] .CLR /*generalRstProcess.timer_reg[5] .CLR /*generalRstProcess.timer_reg[6] .CLR /*generalRstProcess.timer_reg[7] .CLR /*generalRstProcess.timer_reg[8] .CLR /*generalRstProcess.timer_reg[9] PRE /*genReset_s_reg .CLR /*generalRstProcess.timer_reg[0] /CLR /*generalRstProcess.timer_reg[10] /CLR /*generalRstProcess.timer_reg[11] /CLR /*generalRstProcess.timer_reg[12] /CLR /*generalRstProcess.timer_reg[13] /CLR /*generalRstProcess.timer_reg[14] /CLR /*generalRstProcess.timer_reg[15] /CLR /*generalRstProcess.timer_reg[16] /CLR /*generalRstProcess.timer_reg[17] /CLR /*generalRstProcess.timer_reg[18] /CLR /*generalRstProcess.timer_reg[19] .CLR /*generalRstProcess.timer_reg[1] /CLR /*generalRstProcess.timer_reg[20] /CLR /*generalRstProcess.timer_reg[21] /CLR /*generalRstProcess.timer_reg[22] /CLR /*generalRstProcess.timer_reg[23] /CLR /*generalRstProcess.timer_reg[24] /CLR /*generalRstProcess.timer_reg[25] .CLR /*generalRstProcess.timer_reg[2] .CLR /*generalRstProcess.timer_reg[3] .CLR /*generalRstProcess.timer_reg[4] .CLR /*generalRstProcess.timer_reg[5] .CLR /*generalRstProcess.timer_reg[6] .CLR /*generalRstProcess.timer_reg[7] .CLR /*generalRstProcess.timer_reg[8] .CLR /*generalRstProcess.timer_reg[9] PRE /*genReset_s_reg .CLR /*generalRstProcess.timer_reg[0] /CLR /*generalRstProcess.timer_reg[10] /CLR /*generalRstProcess.timer_reg[11] /CLR /*generalRstProcess.timer_reg[12] /CLR /*generalRstProcess.timer_reg[13] /CLR /*generalRstProcess.timer_reg[14] /CLR /*generalRstProcess.timer_reg[15] /CLR /*generalRstProcess.timer_reg[16] /CLR /*generalRstProcess.timer_reg[17] /CLR /*generalRstProcess.timer_reg[18] /CLR /*generalRstProcess.timer_reg[19] .CLR /*generalRstProcess.timer_reg[1] /CLR /*generalRstProcess.timer_reg[20] /CLR /*generalRstProcess.timer_reg[21] /CLR /*generalRstProcess.timer_reg[22] /CLR /*generalRstProcess.timer_reg[23] /CLR /*generalRstProcess.timer_reg[24] /CLR /*generalRstProcess.timer_reg[25] .CLR /*generalRstProcess.timer_reg[2] .CLR /*generalRstProcess.timer_reg[3] .CLR /*generalRstProcess.timer_reg[4] .CLR /*generalRstProcess.timer_reg[5] .CLR /*generalRstProcess.timer_reg[6] .CLR /*generalRstProcess.timer_reg[7] .CLR /*generalRstProcess.timer_reg[8] .CLR /*generalRstProcess.timer_reg[9] PRE /*genReset_s_reg .CLR /*generalRstProcess.timer_reg[0] /CLR /*generalRstProcess.timer_reg[10] /CLR /*generalRstProcess.timer_reg[11] /CLR /*generalRstProcess.timer_reg[12] /CLR /*generalRstProcess.timer_reg[13] /CLR /*generalRstProcess.timer_reg[14] /CLR /*generalRstProcess.timer_reg[15] /CLR /*generalRstProcess.timer_reg[16] /CLR /*generalRstProcess.timer_reg[17] /CLR /*generalRstProcess.timer_reg[18] /CLR /*generalRstProcess.timer_reg[19] .CLR /*generalRstProcess.timer_reg[1] /CLR /*generalRstProcess.timer_reg[20] /CLR /*generalRstProcess.timer_reg[21] /CLR /*generalRstProcess.timer_reg[22] /CLR /*generalRstProcess.timer_reg[23] /CLR /*generalRstProcess.timer_reg[24] /CLR /*generalRstProcess.timer_reg[25] .CLR /*generalRstProcess.timer_reg[2] .CLR /*generalRstProcess.timer_reg[3] .CLR /*generalRstProcess.timer_reg[4] .CLR /*generalRstProcess.timer_reg[5] .CLR /*generalRstProcess.timer_reg[6] .CLR /*generalRstProcess.timer_reg[7] .CLR /*generalRstProcess.timer_reg[8] .CLR /*generalRstProcess.timer_reg[9] PRE /*genReset_s_reg{JbWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#988B LUT cell ctrl_regs_inst/generalRstProcess.timer[0]_i_3__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[19]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/CLR (the first 15 of 324 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell ctrl_regs_inst/generalRstProcess.timer[0]_i_3__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[19]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/CLR, g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/CLR (the first 15 of 324 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.0 .."generalRstProcess.timer[0]_i_3__44 *y .CLR 1*generalRstProcess.timer_reg[0] /CLR 1*generalRstProcess.timer_reg[10] /CLR 1*generalRstProcess.timer_reg[11] /CLR 1*generalRstProcess.timer_reg[12] /CLR 1*generalRstProcess.timer_reg[13] /CLR 1*generalRstProcess.timer_reg[14] /CLR 1*generalRstProcess.timer_reg[15] /CLR 1*generalRstProcess.timer_reg[16] /CLR 1*generalRstProcess.timer_reg[17] /CLR 1*generalRstProcess.timer_reg[18] /CLR 1*generalRstProcess.timer_reg[19] .CLR 1*generalRstProcess.timer_reg[1] /CLR 1*generalRstProcess.timer_reg[20] /CLR 1*generalRstProcess.timer_reg[21] /CLR 1*generalRstProcess.timer_reg[22] /CLR 1*generalRstProcess.timer_reg[23] /CLR 1*generalRstProcess.timer_reg[24] /CLR 1*generalRstProcess.timer_reg[25] .CLR 1*generalRstProcess.timer_reg[2] .CLR 1*generalRstProcess.timer_reg[3] .CLR 1*generalRstProcess.timer_reg[4] .CLR 1*generalRstProcess.timer_reg[5] .CLR 1*generalRstProcess.timer_reg[6] .CLR 1*generalRstProcess.timer_reg[7] .CLR 1*generalRstProcess.timer_reg[8] .CLR 1*generalRstProcess.timer_reg[9] PRE 1*genReset_s_reg .CLR 1*generalRstProcess.timer_reg[0] /CLR 1*generalRstProcess.timer_reg[10] /CLR 1*generalRstProcess.timer_reg[11] /CLR 1*generalRstProcess.timer_reg[12] /CLR 1*generalRstProcess.timer_reg[13] /CLR 1*generalRstProcess.timer_reg[14] /CLR 1*generalRstProcess.timer_reg[15] /CLR 1*generalRstProcess.timer_reg[16] /CLR 1*generalRstProcess.timer_reg[17] /CLR 1*generalRstProcess.timer_reg[18] /CLR 1*generalRstProcess.timer_reg[19] .CLR 1*generalRstProcess.timer_reg[1] /CLR 1*generalRstProcess.timer_reg[20] /CLR 1*generalRstProcess.timer_reg[21] /CLR 1*generalRstProcess.timer_reg[22] /CLR 1*generalRstProcess.timer_reg[23] /CLR 1*generalRstProcess.timer_reg[24] /CLR 1*generalRstProcess.timer_reg[25] .CLR 1*generalRstProcess.timer_reg[2] .CLR 1*generalRstProcess.timer_reg[3] .CLR 1*generalRstProcess.timer_reg[4] .CLR 1*generalRstProcess.timer_reg[5] .CLR 1*generalRstProcess.timer_reg[6] .CLR 1*generalRstProcess.timer_reg[7] .CLR 1*generalRstProcess.timer_reg[8] .CLR 1*generalRstProcess.timer_reg[9] PRE 1*genReset_s_reg .CLR 1*generalRstProcess.timer_reg[0] /CLR 1*generalRstProcess.timer_reg[10] /CLR 1*generalRstProcess.timer_reg[11] /CLR 1*generalRstProcess.timer_reg[12] /CLR 1*generalRstProcess.timer_reg[13] /CLR 1*generalRstProcess.timer_reg[14] /CLR 1*generalRstProcess.timer_reg[15] /CLR 1*generalRstProcess.timer_reg[16] /CLR 1*generalRstProcess.timer_reg[17] /CLR 1*generalRstProcess.timer_reg[18] /CLR 1*generalRstProcess.timer_reg[19] .CLR 1*generalRstProcess.timer_reg[1] /CLR 1*generalRstProcess.timer_reg[20] /CLR 1*generalRstProcess.timer_reg[21] /CLR 1*generalRstProcess.timer_reg[22] /CLR 1*generalRstProcess.timer_reg[23] /CLR 1*generalRstProcess.timer_reg[24] /CLR 1*generalRstProcess.timer_reg[25] .CLR 1*generalRstProcess.timer_reg[2] .CLR 1*generalRstProcess.timer_reg[3] .CLR 1*generalRstProcess.timer_reg[4] .CLR 1*generalRstProcess.timer_reg[5] .CLR 1*generalRstProcess.timer_reg[6] .CLR 1*generalRstProcess.timer_reg[7] .CLR 1*generalRstProcess.timer_reg[8] .CLR 1*generalRstProcess.timer_reg[9] PRE 1*genReset_s_reg .CLR 1*generalRstProcess.timer_reg[0] /CLR 1*generalRstProcess.timer_reg[10] /CLR 1*generalRstProcess.timer_reg[11] /CLR 1*generalRstProcess.timer_reg[12] /CLR 1*generalRstProcess.timer_reg[13] /CLR 1*generalRstProcess.timer_reg[14] /CLR 1*generalRstProcess.timer_reg[15] /CLR 1*generalRstProcess.timer_reg[16] /CLR 1*generalRstProcess.timer_reg[17] /CLR 1*generalRstProcess.timer_reg[18] /CLR 1*generalRstProcess.timer_reg[19] .CLR 1*generalRstProcess.timer_reg[1] /CLR 1*generalRstProcess.timer_reg[20] /CLR 1*generalRstProcess.timer_reg[21] /CLR 1*generalRstProcess.timer_reg[22] /CLR 1*generalRstProcess.timer_reg[23] /CLR 1*generalRstProcess.timer_reg[24] /CLR 1*generalRstProcess.timer_reg[25] .CLR 1*generalRstProcess.timer_reg[2] .CLR 1*generalRstProcess.timer_reg[3] .CLR 1*generalRstProcess.timer_reg[4] .CLR 1*generalRstProcess.timer_reg[5] .CLR 1*generalRstProcess.timer_reg[6] .CLR 1*generalRstProcess.timer_reg[7] .CLR 1*generalRstProcess.timer_reg[8] .CLR 1*generalRstProcess.timer_reg[9] PRE 1*genReset_s_reg .CLR 1*generalRstProcess.timer_reg[0] /CLR 1*generalRstProcess.timer_reg[10] /CLR 1*generalRstProcess.timer_reg[11] /CLR 1*generalRstProcess.timer_reg[12] /CLR 1*generalRstProcess.timer_reg[13] /CLR 1*generalRstProcess.timer_reg[14] /CLR 1*generalRstProcess.timer_reg[15] /CLR 1*generalRstProcess.timer_reg[16] /CLR 1*generalRstProcess.timer_reg[17] /CLR 1*generalRstProcess.timer_reg[18] /CLR 1*generalRstProcess.timer_reg[19] .CLR 1*generalRstProcess.timer_reg[1] /CLR 1*generalRstProcess.timer_reg[20] /CLR 1*generalRstProcess.timer_reg[21] /CLR 1*generalRstProcess.timer_reg[22] /CLR 1*generalRstProcess.timer_reg[23] /CLR 1*generalRstProcess.timer_reg[24] /CLR 1*generalRstProcess.timer_reg[25] .CLR 1*generalRstProcess.timer_reg[2] .CLR 1*generalRstProcess.timer_reg[3] .CLR 1*generalRstProcess.timer_reg[4] .CLR 1*generalRstProcess.timer_reg[5] .CLR 1*generalRstProcess.timer_reg[6] .CLR 1*generalRstProcess.timer_reg[7] .CLR 1*generalRstProcess.timer_reg[8] .CLR 1*generalRstProcess.timer_reg[9] PRE 1*genReset_s_reg .CLR 1*generalRstProcess.timer_reg[0] /CLR 1*generalRstProcess.timer_reg[10] /CLR 1*generalRstProcess.timer_reg[11] /CLR 1*generalRstProcess.timer_reg[12] /CLR 1*generalRstProcess.timer_reg[13] /CLR 1*generalRstProcess.timer_reg[14] /CLR 1*generalRstProcess.timer_reg[15] /CLR 1*generalRstProcess.timer_reg[16] /CLR 1*generalRstProcess.timer_reg[17] /CLR 1*generalRstProcess.timer_reg[18] /CLR 1*generalRstProcess.timer_reg[19] .CLR 1*generalRstProcess.timer_reg[1] /CLR 1*generalRstProcess.timer_reg[20] /CLR 1*generalRstProcess.timer_reg[21] /CLR 1*generalRstProcess.timer_reg[22] /CLR 1*generalRstProcess.timer_reg[23] /CLR 1*generalRstProcess.timer_reg[24] /CLR 1*generalRstProcess.timer_reg[25] .CLR 1*generalRstProcess.timer_reg[2] .CLR 1*generalRstProcess.timer_reg[3] .CLR 1*generalRstProcess.timer_reg[4] .CLR 1*generalRstProcess.timer_reg[5] .CLR 1*generalRstProcess.timer_reg[6] .CLR 1*generalRstProcess.timer_reg[7] .CLR 1*generalRstProcess.timer_reg[8] .CLR 1*generalRstProcess.timer_reg[9] PRE 1*genReset_s_reg .CLR 1*generalRstProcess.timer_reg[0] /CLR 1*generalRstProcess.timer_reg[10] /CLR 1*generalRstProcess.timer_reg[11] /CLR 1*generalRstProcess.timer_reg[12] /CLR 1*generalRstProcess.timer_reg[13] /CLR 1*generalRstProcess.timer_reg[14] /CLR 1*generalRstProcess.timer_reg[15] /CLR 1*generalRstProcess.timer_reg[16] /CLR 1*generalRstProcess.timer_reg[17] /CLR 1*generalRstProcess.timer_reg[18] /CLR 1*generalRstProcess.timer_reg[19] .CLR 1*generalRstProcess.timer_reg[1] /CLR 1*generalRstProcess.timer_reg[20] /CLR 1*generalRstProcess.timer_reg[21] /CLR 1*generalRstProcess.timer_reg[22] /CLR 1*generalRstProcess.timer_reg[23] /CLR 1*generalRstProcess.timer_reg[24] /CLR 1*generalRstProcess.timer_reg[25] .CLR 1*generalRstProcess.timer_reg[2] .CLR 1*generalRstProcess.timer_reg[3] .CLR 1*generalRstProcess.timer_reg[4] .CLR 1*generalRstProcess.timer_reg[5] .CLR 1*generalRstProcess.timer_reg[6] .CLR 1*generalRstProcess.timer_reg[7] .CLR 1*generalRstProcess.timer_reg[8] .CLR 1*generalRstProcess.timer_reg[9] PRE 1*genReset_s_reg .CLR 1*generalRstProcess.timer_reg[0] /CLR 1*generalRstProcess.timer_reg[10] /CLR 1*generalRstProcess.timer_reg[11] /CLR 1*generalRstProcess.timer_reg[12] /CLR 1*generalRstProcess.timer_reg[13] /CLR 1*generalRstProcess.timer_reg[14] /CLR 1*generalRstProcess.timer_reg[15] /CLR 1*generalRstProcess.timer_reg[16] /CLR 1*generalRstProcess.timer_reg[17] /CLR 1*generalRstProcess.timer_reg[18] /CLR 1*generalRstProcess.timer_reg[19] .CLR 1*generalRstProcess.timer_reg[1] /CLR 1*generalRstProcess.timer_reg[20] /CLR 1*generalRstProcess.timer_reg[21] /CLR 1*generalRstProcess.timer_reg[22] /CLR 1*generalRstProcess.timer_reg[23] /CLR 1*generalRstProcess.timer_reg[24] /CLR 1*generalRstProcess.timer_reg[25] .CLR 1*generalRstProcess.timer_reg[2] .CLR 1*generalRstProcess.timer_reg[3] .CLR 1*generalRstProcess.timer_reg[4] .CLR 1*generalRstProcess.timer_reg[5] .CLR 1*generalRstProcess.timer_reg[6] .CLR 1*generalRstProcess.timer_reg[7] .CLR 1*generalRstProcess.timer_reg[8] .CLR 1*generalRstProcess.timer_reg[9] PRE 1*genReset_s_reg .CLR 1*generalRstProcess.timer_reg[0] /CLR 1*generalRstProcess.timer_reg[10] /CLR 1*generalRstProcess.timer_reg[11] /CLR 1*generalRstProcess.timer_reg[12] /CLR 1*generalRstProcess.timer_reg[13] /CLR 1*generalRstProcess.timer_reg[14] /CLR 1*generalRstProcess.timer_reg[15] /CLR 1*generalRstProcess.timer_reg[16] /CLR 1*generalRstProcess.timer_reg[17] /CLR 1*generalRstProcess.timer_reg[18] /CLR 1*generalRstProcess.timer_reg[19] .CLR 1*generalRstProcess.timer_reg[1] /CLR 1*generalRstProcess.timer_reg[20] /CLR 1*generalRstProcess.timer_reg[21] /CLR 1*generalRstProcess.timer_reg[22] /CLR 1*generalRstProcess.timer_reg[23] /CLR 1*generalRstProcess.timer_reg[24] /CLR 1*generalRstProcess.timer_reg[25] .CLR 1*generalRstProcess.timer_reg[2] .CLR 1*generalRstProcess.timer_reg[3] .CLR 1*generalRstProcess.timer_reg[4] .CLR 1*generalRstProcess.timer_reg[5] .CLR 1*generalRstProcess.timer_reg[6] .CLR 1*generalRstProcess.timer_reg[7] .CLR 1*generalRstProcess.timer_reg[8] .CLR 1*generalRstProcess.timer_reg[9] PRE 1*genReset_s_reg .CLR 2*generalRstProcess.timer_reg[0] /CLR 2*generalRstProcess.timer_reg[10] /CLR 2*generalRstProcess.timer_reg[11] /CLR 2*generalRstProcess.timer_reg[12] /CLR 2*generalRstProcess.timer_reg[13] /CLR 2*generalRstProcess.timer_reg[14] /CLR 2*generalRstProcess.timer_reg[15] /CLR 2*generalRstProcess.timer_reg[16] /CLR 2*generalRstProcess.timer_reg[17] /CLR 2*generalRstProcess.timer_reg[18] /CLR 2*generalRstProcess.timer_reg[19] .CLR 2*generalRstProcess.timer_reg[1] /CLR 2*generalRstProcess.timer_reg[20] /CLR 2*generalRstProcess.timer_reg[21] /CLR 2*generalRstProcess.timer_reg[22] /CLR 2*generalRstProcess.timer_reg[23] /CLR 2*generalRstProcess.timer_reg[24] /CLR 2*generalRstProcess.timer_reg[25] .CLR 2*generalRstProcess.timer_reg[2] .CLR 2*generalRstProcess.timer_reg[3] .CLR 2*generalRstProcess.timer_reg[4] .CLR 2*generalRstProcess.timer_reg[5] .CLR 2*generalRstProcess.timer_reg[6] .CLR 2*generalRstProcess.timer_reg[7] .CLR 2*generalRstProcess.timer_reg[8] .CLR 2*generalRstProcess.timer_reg[9] PRE 2*genReset_s_reg .CLR €2*generalRstProcess.timer_reg[0] /CLR ̀2*generalRstProcess.timer_reg[10] /CLR ̀2*generalRstProcess.timer_reg[11] /CLR ΀2*generalRstProcess.timer_reg[12] /CLR π2*generalRstProcess.timer_reg[13] /CLR Ѐ2*generalRstProcess.timer_reg[14] /CLR р2*generalRstProcess.timer_reg[15] /CLR Ҁ2*generalRstProcess.timer_reg[16] /CLR Ӏ2*generalRstProcess.timer_reg[17] /CLR Ԁ2*generalRstProcess.timer_reg[18] /CLR Հ2*generalRstProcess.timer_reg[19] .CLR À2*generalRstProcess.timer_reg[1] /CLR ր2*generalRstProcess.timer_reg[20] /CLR ׀2*generalRstProcess.timer_reg[21] /CLR ؀2*generalRstProcess.timer_reg[22] /CLR ـ2*generalRstProcess.timer_reg[23] /CLR ڀ2*generalRstProcess.timer_reg[24] /CLR ۀ2*generalRstProcess.timer_reg[25] .CLR Ā2*generalRstProcess.timer_reg[2] .CLR ŀ2*generalRstProcess.timer_reg[3] .CLR ƀ2*generalRstProcess.timer_reg[4] .CLR ǀ2*generalRstProcess.timer_reg[5] .CLR Ȁ2*generalRstProcess.timer_reg[6] .CLR ɀ2*generalRstProcess.timer_reg[7] .CLR ʀ2*generalRstProcess.timer_reg[8] .CLR ˀ2*generalRstProcess.timer_reg[9] PRE 2*genReset_s_reg .CLR 2*generalRstProcess.timer_reg[0] /CLR 2*generalRstProcess.timer_reg[10] /CLR 2*generalRstProcess.timer_reg[11] /CLR 2*generalRstProcess.timer_reg[12] /CLR 2*generalRstProcess.timer_reg[13] /CLR 2*generalRstProcess.timer_reg[14] /CLR 2*generalRstProcess.timer_reg[15] /CLR 2*generalRstProcess.timer_reg[16] /CLR 2*generalRstProcess.timer_reg[17] /CLR 2*generalRstProcess.timer_reg[18] /CLR 2*generalRstProcess.timer_reg[19] .CLR 2*generalRstProcess.timer_reg[1] /CLR 2*generalRstProcess.timer_reg[20] /CLR 2*generalRstProcess.timer_reg[21] /CLR 2*generalRstProcess.timer_reg[22] /CLR 2*generalRstProcess.timer_reg[23] /CLR 2*generalRstProcess.timer_reg[24] /CLR 2*generalRstProcess.timer_reg[25] .CLR 2*generalRstProcess.timer_reg[2] .CLR 2*generalRstProcess.timer_reg[3] .CLR 2*generalRstProcess.timer_reg[4] .CLR 2*generalRstProcess.timer_reg[5] .CLR 2*generalRstProcess.timer_reg[6] .CLR 2*generalRstProcess.timer_reg[7] .CLR 2*generalRstProcess.timer_reg[8] .CLR 2*generalRstProcess.timer_reg[9] PRE 2*genReset_s_reg{JcWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#998B LUT cell ctrl_regs_inst/generalRstProcess.timer[0]_i_3__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[19]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/CLR (the first 15 of 324 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell ctrl_regs_inst/generalRstProcess.timer[0]_i_3__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[19]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/CLR, g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/CLR (the first 15 of 324 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.0 .."generalRstProcess.timer[0]_i_3__45 *y .CLR 4*generalRstProcess.timer_reg[0] /CLR 4*generalRstProcess.timer_reg[10] /CLR 4*generalRstProcess.timer_reg[11] /CLR 4*generalRstProcess.timer_reg[12] /CLR Í4*generalRstProcess.timer_reg[13] /CLR č4*generalRstProcess.timer_reg[14] /CLR ō4*generalRstProcess.timer_reg[15] /CLR ƍ4*generalRstProcess.timer_reg[16] /CLR Ǎ4*generalRstProcess.timer_reg[17] /CLR ȍ4*generalRstProcess.timer_reg[18] /CLR ɍ4*generalRstProcess.timer_reg[19] .CLR 4*generalRstProcess.timer_reg[1] /CLR ʍ4*generalRstProcess.timer_reg[20] /CLR ˍ4*generalRstProcess.timer_reg[21] /CLR ̍4*generalRstProcess.timer_reg[22] /CLR ͍4*generalRstProcess.timer_reg[23] /CLR ΍4*generalRstProcess.timer_reg[24] /CLR ύ4*generalRstProcess.timer_reg[25] .CLR 4*generalRstProcess.timer_reg[2] .CLR 4*generalRstProcess.timer_reg[3] .CLR 4*generalRstProcess.timer_reg[4] .CLR 4*generalRstProcess.timer_reg[5] .CLR 4*generalRstProcess.timer_reg[6] .CLR 4*generalRstProcess.timer_reg[7] .CLR 4*generalRstProcess.timer_reg[8] .CLR 4*generalRstProcess.timer_reg[9] PRE 4*genReset_s_reg .CLR 4*generalRstProcess.timer_reg[0] /CLR 4*generalRstProcess.timer_reg[10] /CLR 4*generalRstProcess.timer_reg[11] /CLR 4*generalRstProcess.timer_reg[12] /CLR 4*generalRstProcess.timer_reg[13] /CLR 4*generalRstProcess.timer_reg[14] /CLR 4*generalRstProcess.timer_reg[15] /CLR 4*generalRstProcess.timer_reg[16] /CLR 4*generalRstProcess.timer_reg[17] /CLR 4*generalRstProcess.timer_reg[18] /CLR 4*generalRstProcess.timer_reg[19] .CLR 4*generalRstProcess.timer_reg[1] /CLR 4*generalRstProcess.timer_reg[20] /CLR 4*generalRstProcess.timer_reg[21] /CLR 4*generalRstProcess.timer_reg[22] /CLR 4*generalRstProcess.timer_reg[23] /CLR 4*generalRstProcess.timer_reg[24] /CLR 4*generalRstProcess.timer_reg[25] .CLR 4*generalRstProcess.timer_reg[2] .CLR 4*generalRstProcess.timer_reg[3] .CLR 4*generalRstProcess.timer_reg[4] .CLR 4*generalRstProcess.timer_reg[5] .CLR 4*generalRstProcess.timer_reg[6] .CLR 4*generalRstProcess.timer_reg[7] .CLR 4*generalRstProcess.timer_reg[8] .CLR 4*generalRstProcess.timer_reg[9] PRE 4*genReset_s_reg .CLR 4*generalRstProcess.timer_reg[0] /CLR 4*generalRstProcess.timer_reg[10] /CLR 4*generalRstProcess.timer_reg[11] /CLR 4*generalRstProcess.timer_reg[12] /CLR 4*generalRstProcess.timer_reg[13] /CLR 4*generalRstProcess.timer_reg[14] /CLR 4*generalRstProcess.timer_reg[15] /CLR 4*generalRstProcess.timer_reg[16] /CLR 4*generalRstProcess.timer_reg[17] /CLR 4*generalRstProcess.timer_reg[18] /CLR 4*generalRstProcess.timer_reg[19] .CLR 4*generalRstProcess.timer_reg[1] /CLR 4*generalRstProcess.timer_reg[20] /CLR 4*generalRstProcess.timer_reg[21] /CLR Ž4*generalRstProcess.timer_reg[22] /CLR Î4*generalRstProcess.timer_reg[23] /CLR Ď4*generalRstProcess.timer_reg[24] /CLR Ŏ4*generalRstProcess.timer_reg[25] .CLR 4*generalRstProcess.timer_reg[2] .CLR 4*generalRstProcess.timer_reg[3] .CLR 4*generalRstProcess.timer_reg[4] .CLR 4*generalRstProcess.timer_reg[5] .CLR 4*generalRstProcess.timer_reg[6] .CLR 4*generalRstProcess.timer_reg[7] .CLR 4*generalRstProcess.timer_reg[8] .CLR 4*generalRstProcess.timer_reg[9] PRE ێ4*genReset_s_reg .CLR 4*generalRstProcess.timer_reg[0] /CLR 4*generalRstProcess.timer_reg[10] /CLR 4*generalRstProcess.timer_reg[11] /CLR 4*generalRstProcess.timer_reg[12] /CLR 4*generalRstProcess.timer_reg[13] /CLR 4*generalRstProcess.timer_reg[14] /CLR 4*generalRstProcess.timer_reg[15] /CLR 4*generalRstProcess.timer_reg[16] /CLR 4*generalRstProcess.timer_reg[17] /CLR 4*generalRstProcess.timer_reg[18] /CLR 4*generalRstProcess.timer_reg[19] .CLR 4*generalRstProcess.timer_reg[1] /CLR 4*generalRstProcess.timer_reg[20] /CLR 4*generalRstProcess.timer_reg[21] /CLR 4*generalRstProcess.timer_reg[22] /CLR 4*generalRstProcess.timer_reg[23] /CLR 4*generalRstProcess.timer_reg[24] /CLR 4*generalRstProcess.timer_reg[25] .CLR 4*generalRstProcess.timer_reg[2] .CLR 4*generalRstProcess.timer_reg[3] .CLR 4*generalRstProcess.timer_reg[4] .CLR 4*generalRstProcess.timer_reg[5] .CLR 4*generalRstProcess.timer_reg[6] .CLR 4*generalRstProcess.timer_reg[7] .CLR 4*generalRstProcess.timer_reg[8] .CLR 4*generalRstProcess.timer_reg[9] PRE 4*genReset_s_reg .CLR 4*generalRstProcess.timer_reg[0] /CLR 4*generalRstProcess.timer_reg[10] /CLR 4*generalRstProcess.timer_reg[11] /CLR 4*generalRstProcess.timer_reg[12] /CLR 4*generalRstProcess.timer_reg[13] /CLR 4*generalRstProcess.timer_reg[14] /CLR 4*generalRstProcess.timer_reg[15] /CLR 4*generalRstProcess.timer_reg[16] /CLR 4*generalRstProcess.timer_reg[17] /CLR 4*generalRstProcess.timer_reg[18] /CLR 4*generalRstProcess.timer_reg[19] .CLR 4*generalRstProcess.timer_reg[1] /CLR 4*generalRstProcess.timer_reg[20] /CLR 4*generalRstProcess.timer_reg[21] /CLR 4*generalRstProcess.timer_reg[22] /CLR 4*generalRstProcess.timer_reg[23] /CLR 4*generalRstProcess.timer_reg[24] /CLR 4*generalRstProcess.timer_reg[25] .CLR 4*generalRstProcess.timer_reg[2] .CLR 4*generalRstProcess.timer_reg[3] .CLR 4*generalRstProcess.timer_reg[4] .CLR 4*generalRstProcess.timer_reg[5] .CLR 4*generalRstProcess.timer_reg[6] .CLR 4*generalRstProcess.timer_reg[7] .CLR 4*generalRstProcess.timer_reg[8] .CLR 4*generalRstProcess.timer_reg[9] PRE Ϗ4*genReset_s_reg .CLR ڏ4*generalRstProcess.timer_reg[0] /CLR 4*generalRstProcess.timer_reg[10] /CLR 4*generalRstProcess.timer_reg[11] /CLR 4*generalRstProcess.timer_reg[12] /CLR 4*generalRstProcess.timer_reg[13] /CLR 4*generalRstProcess.timer_reg[14] /CLR 4*generalRstProcess.timer_reg[15] /CLR 4*generalRstProcess.timer_reg[16] /CLR 4*generalRstProcess.timer_reg[17] /CLR 4*generalRstProcess.timer_reg[18] /CLR 4*generalRstProcess.timer_reg[19] .CLR ۏ4*generalRstProcess.timer_reg[1] /CLR 4*generalRstProcess.timer_reg[20] /CLR 4*generalRstProcess.timer_reg[21] /CLR 4*generalRstProcess.timer_reg[22] /CLR 4*generalRstProcess.timer_reg[23] /CLR 4*generalRstProcess.timer_reg[24] /CLR 4*generalRstProcess.timer_reg[25] .CLR ܏4*generalRstProcess.timer_reg[2] .CLR ݏ4*generalRstProcess.timer_reg[3] .CLR ޏ4*generalRstProcess.timer_reg[4] .CLR ߏ4*generalRstProcess.timer_reg[5] .CLR 4*generalRstProcess.timer_reg[6] .CLR 4*generalRstProcess.timer_reg[7] .CLR 4*generalRstProcess.timer_reg[8] .CLR 4*generalRstProcess.timer_reg[9] PRE 4*genReset_s_reg .CLR 4*generalRstProcess.timer_reg[0] /CLR 4*generalRstProcess.timer_reg[10] /CLR 4*generalRstProcess.timer_reg[11] /CLR 4*generalRstProcess.timer_reg[12] /CLR 4*generalRstProcess.timer_reg[13] /CLR 4*generalRstProcess.timer_reg[14] /CLR 4*generalRstProcess.timer_reg[15] /CLR 4*generalRstProcess.timer_reg[16] /CLR 4*generalRstProcess.timer_reg[17] /CLR 4*generalRstProcess.timer_reg[18] /CLR 4*generalRstProcess.timer_reg[19] .CLR 4*generalRstProcess.timer_reg[1] /CLR 4*generalRstProcess.timer_reg[20] /CLR 4*generalRstProcess.timer_reg[21] /CLR 4*generalRstProcess.timer_reg[22] /CLR 4*generalRstProcess.timer_reg[23] /CLR 4*generalRstProcess.timer_reg[24] /CLR 4*generalRstProcess.timer_reg[25] .CLR 4*generalRstProcess.timer_reg[2] .CLR 4*generalRstProcess.timer_reg[3] .CLR 4*generalRstProcess.timer_reg[4] .CLR 4*generalRstProcess.timer_reg[5] .CLR 4*generalRstProcess.timer_reg[6] .CLR 4*generalRstProcess.timer_reg[7] .CLR 4*generalRstProcess.timer_reg[8] .CLR 4*generalRstProcess.timer_reg[9] PRE Ð4*genReset_s_reg .CLR ΐ4*generalRstProcess.timer_reg[0] /CLR ؐ4*generalRstProcess.timer_reg[10] /CLR ِ4*generalRstProcess.timer_reg[11] /CLR ڐ4*generalRstProcess.timer_reg[12] /CLR ې4*generalRstProcess.timer_reg[13] /CLR ܐ4*generalRstProcess.timer_reg[14] /CLR ݐ4*generalRstProcess.timer_reg[15] /CLR ސ4*generalRstProcess.timer_reg[16] /CLR ߐ4*generalRstProcess.timer_reg[17] /CLR 4*generalRstProcess.timer_reg[18] /CLR 4*generalRstProcess.timer_reg[19] .CLR ϐ4*generalRstProcess.timer_reg[1] /CLR 4*generalRstProcess.timer_reg[20] /CLR 4*generalRstProcess.timer_reg[21] /CLR 4*generalRstProcess.timer_reg[22] /CLR 4*generalRstProcess.timer_reg[23] /CLR 4*generalRstProcess.timer_reg[24] /CLR 4*generalRstProcess.timer_reg[25] .CLR А4*generalRstProcess.timer_reg[2] .CLR ѐ4*generalRstProcess.timer_reg[3] .CLR Ґ4*generalRstProcess.timer_reg[4] .CLR Ӑ4*generalRstProcess.timer_reg[5] .CLR Ԑ4*generalRstProcess.timer_reg[6] .CLR Ր4*generalRstProcess.timer_reg[7] .CLR ֐4*generalRstProcess.timer_reg[8] .CLR א4*generalRstProcess.timer_reg[9] PRE 4*genReset_s_reg .CLR 4*generalRstProcess.timer_reg[0] /CLR 4*generalRstProcess.timer_reg[10] /CLR 4*generalRstProcess.timer_reg[11] /CLR 4*generalRstProcess.timer_reg[12] /CLR 4*generalRstProcess.timer_reg[13] /CLR 4*generalRstProcess.timer_reg[14] /CLR 4*generalRstProcess.timer_reg[15] /CLR 4*generalRstProcess.timer_reg[16] /CLR 4*generalRstProcess.timer_reg[17] /CLR 4*generalRstProcess.timer_reg[18] /CLR 4*generalRstProcess.timer_reg[19] .CLR 4*generalRstProcess.timer_reg[1] /CLR 4*generalRstProcess.timer_reg[20] /CLR 4*generalRstProcess.timer_reg[21] /CLR 4*generalRstProcess.timer_reg[22] /CLR 4*generalRstProcess.timer_reg[23] /CLR 4*generalRstProcess.timer_reg[24] /CLR 4*generalRstProcess.timer_reg[25] .CLR 4*generalRstProcess.timer_reg[2] .CLR 4*generalRstProcess.timer_reg[3] .CLR 4*generalRstProcess.timer_reg[4] .CLR 4*generalRstProcess.timer_reg[5] .CLR 4*generalRstProcess.timer_reg[6] .CLR 4*generalRstProcess.timer_reg[7] .CLR 4*generalRstProcess.timer_reg[8] .CLR 4*generalRstProcess.timer_reg[9] PRE ő4*genReset_s_reg .CLR Б4*generalRstProcess.timer_reg[0] /CLR ڑ4*generalRstProcess.timer_reg[10] /CLR ۑ4*generalRstProcess.timer_reg[11] /CLR ܑ4*generalRstProcess.timer_reg[12] /CLR ݑ4*generalRstProcess.timer_reg[13] /CLR ޑ4*generalRstProcess.timer_reg[14] /CLR ߑ4*generalRstProcess.timer_reg[15] /CLR 4*generalRstProcess.timer_reg[16] /CLR 4*generalRstProcess.timer_reg[17] /CLR 4*generalRstProcess.timer_reg[18] /CLR 4*generalRstProcess.timer_reg[19] .CLR ё4*generalRstProcess.timer_reg[1] /CLR 4*generalRstProcess.timer_reg[20] /CLR 4*generalRstProcess.timer_reg[21] /CLR 4*generalRstProcess.timer_reg[22] /CLR 4*generalRstProcess.timer_reg[23] /CLR 4*generalRstProcess.timer_reg[24] /CLR 4*generalRstProcess.timer_reg[25] .CLR ґ4*generalRstProcess.timer_reg[2] .CLR ӑ4*generalRstProcess.timer_reg[3] .CLR ԑ4*generalRstProcess.timer_reg[4] .CLR Ց4*generalRstProcess.timer_reg[5] .CLR ֑4*generalRstProcess.timer_reg[6] .CLR ב4*generalRstProcess.timer_reg[7] .CLR ؑ4*generalRstProcess.timer_reg[8] .CLR ّ4*generalRstProcess.timer_reg[9] PRE 4*genReset_s_reg .CLR 4*generalRstProcess.timer_reg[0] /CLR 4*generalRstProcess.timer_reg[10] /CLR 4*generalRstProcess.timer_reg[11] /CLR 4*generalRstProcess.timer_reg[12] /CLR 4*generalRstProcess.timer_reg[13] /CLR 4*generalRstProcess.timer_reg[14] /CLR 4*generalRstProcess.timer_reg[15] /CLR 4*generalRstProcess.timer_reg[16] /CLR 4*generalRstProcess.timer_reg[17] /CLR 4*generalRstProcess.timer_reg[18] /CLR 4*generalRstProcess.timer_reg[19] .CLR 4*generalRstProcess.timer_reg[1] /CLR 4*generalRstProcess.timer_reg[20] /CLR 4*generalRstProcess.timer_reg[21] /CLR 4*generalRstProcess.timer_reg[22] /CLR 4*generalRstProcess.timer_reg[23] /CLR 4*generalRstProcess.timer_reg[24] /CLR 4*generalRstProcess.timer_reg[25] .CLR 4*generalRstProcess.timer_reg[2] .CLR 4*generalRstProcess.timer_reg[3] .CLR 4*generalRstProcess.timer_reg[4] .CLR 4*generalRstProcess.timer_reg[5] .CLR 4*generalRstProcess.timer_reg[6] .CLR 4*generalRstProcess.timer_reg[7] .CLR 4*generalRstProcess.timer_reg[8] .CLR 4*generalRstProcess.timer_reg[9] PRE 4*genReset_s_reg .CLR Ē4*generalRstProcess.timer_reg[0] /CLR Β4*generalRstProcess.timer_reg[10] /CLR ϒ4*generalRstProcess.timer_reg[11] /CLR В4*generalRstProcess.timer_reg[12] /CLR ђ4*generalRstProcess.timer_reg[13] /CLR Ғ4*generalRstProcess.timer_reg[14] /CLR Ӓ4*generalRstProcess.timer_reg[15] /CLR Ԓ4*generalRstProcess.timer_reg[16] /CLR Ւ4*generalRstProcess.timer_reg[17] /CLR ֒4*generalRstProcess.timer_reg[18] /CLR ג4*generalRstProcess.timer_reg[19] .CLR Œ4*generalRstProcess.timer_reg[1] /CLR ؒ4*generalRstProcess.timer_reg[20] /CLR ْ4*generalRstProcess.timer_reg[21] /CLR ڒ4*generalRstProcess.timer_reg[22] /CLR ے4*generalRstProcess.timer_reg[23] /CLR ܒ4*generalRstProcess.timer_reg[24] /CLR ݒ4*generalRstProcess.timer_reg[25] .CLR ƒ4*generalRstProcess.timer_reg[2] .CLR ǒ4*generalRstProcess.timer_reg[3] .CLR Ȓ4*generalRstProcess.timer_reg[4] .CLR ɒ4*generalRstProcess.timer_reg[5] .CLR ʒ4*generalRstProcess.timer_reg[6] .CLR ˒4*generalRstProcess.timer_reg[7] .CLR ̒4*generalRstProcess.timer_reg[8] .CLR ͒4*generalRstProcess.timer_reg[9] PRE 4*genReset_s_reg|JdWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1008B LUT cell ctrl_regs_inst/generalRstProcess.timer[0]_i_3__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[19]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/CLR (the first 15 of 324 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell ctrl_regs_inst/generalRstProcess.timer[0]_i_3__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[10]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[11]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[12]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[13]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[14]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[15]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[16]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[17]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[18]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[19]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[20]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[21]/CLR, g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/generalRstProcess.timer_reg[22]/CLR (the first 15 of 324 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.0 .."generalRstProcess.timer[0]_i_3__46 *y .CLR Ğ6*generalRstProcess.timer_reg[0] /CLR Ξ6*generalRstProcess.timer_reg[10] /CLR Ϟ6*generalRstProcess.timer_reg[11] /CLR О6*generalRstProcess.timer_reg[12] /CLR ў6*generalRstProcess.timer_reg[13] /CLR Ҟ6*generalRstProcess.timer_reg[14] /CLR Ӟ6*generalRstProcess.timer_reg[15] /CLR Ԟ6*generalRstProcess.timer_reg[16] /CLR ՞6*generalRstProcess.timer_reg[17] /CLR ֞6*generalRstProcess.timer_reg[18] /CLR מ6*generalRstProcess.timer_reg[19] .CLR Ş6*generalRstProcess.timer_reg[1] /CLR ؞6*generalRstProcess.timer_reg[20] /CLR ٞ6*generalRstProcess.timer_reg[21] /CLR ڞ6*generalRstProcess.timer_reg[22] /CLR ۞6*generalRstProcess.timer_reg[23] /CLR ܞ6*generalRstProcess.timer_reg[24] /CLR ݞ6*generalRstProcess.timer_reg[25] .CLR ƞ6*generalRstProcess.timer_reg[2] .CLR Ǟ6*generalRstProcess.timer_reg[3] .CLR Ȟ6*generalRstProcess.timer_reg[4] .CLR ɞ6*generalRstProcess.timer_reg[5] .CLR ʞ6*generalRstProcess.timer_reg[6] .CLR ˞6*generalRstProcess.timer_reg[7] .CLR ̞6*generalRstProcess.timer_reg[8] .CLR ͞6*generalRstProcess.timer_reg[9] PRE 6*genReset_s_reg .CLR 6*generalRstProcess.timer_reg[0] /CLR 6*generalRstProcess.timer_reg[10] /CLR 6*generalRstProcess.timer_reg[11] /CLR 6*generalRstProcess.timer_reg[12] /CLR 6*generalRstProcess.timer_reg[13] /CLR 6*generalRstProcess.timer_reg[14] /CLR 6*generalRstProcess.timer_reg[15] /CLR 6*generalRstProcess.timer_reg[16] /CLR 6*generalRstProcess.timer_reg[17] /CLR 6*generalRstProcess.timer_reg[18] /CLR 6*generalRstProcess.timer_reg[19] .CLR 6*generalRstProcess.timer_reg[1] /CLR 6*generalRstProcess.timer_reg[20] /CLR 6*generalRstProcess.timer_reg[21] /CLR 6*generalRstProcess.timer_reg[22] /CLR 6*generalRstProcess.timer_reg[23] /CLR 6*generalRstProcess.timer_reg[24] /CLR 6*generalRstProcess.timer_reg[25] .CLR 6*generalRstProcess.timer_reg[2] .CLR 6*generalRstProcess.timer_reg[3] .CLR 6*generalRstProcess.timer_reg[4] .CLR 6*generalRstProcess.timer_reg[5] .CLR 6*generalRstProcess.timer_reg[6] .CLR 6*generalRstProcess.timer_reg[7] .CLR 6*generalRstProcess.timer_reg[8] .CLR 6*generalRstProcess.timer_reg[9] PRE 6*genReset_s_reg .CLR 6*generalRstProcess.timer_reg[0] /CLR ğ6*generalRstProcess.timer_reg[10] /CLR ş6*generalRstProcess.timer_reg[11] /CLR Ɵ6*generalRstProcess.timer_reg[12] /CLR ǟ6*generalRstProcess.timer_reg[13] /CLR ȟ6*generalRstProcess.timer_reg[14] /CLR ɟ6*generalRstProcess.timer_reg[15] /CLR ʟ6*generalRstProcess.timer_reg[16] /CLR ˟6*generalRstProcess.timer_reg[17] /CLR ̟6*generalRstProcess.timer_reg[18] /CLR ͟6*generalRstProcess.timer_reg[19] .CLR 6*generalRstProcess.timer_reg[1] /CLR Ο6*generalRstProcess.timer_reg[20] /CLR ϟ6*generalRstProcess.timer_reg[21] /CLR П6*generalRstProcess.timer_reg[22] /CLR џ6*generalRstProcess.timer_reg[23] /CLR ҟ6*generalRstProcess.timer_reg[24] /CLR ӟ6*generalRstProcess.timer_reg[25] .CLR 6*generalRstProcess.timer_reg[2] .CLR 6*generalRstProcess.timer_reg[3] .CLR 6*generalRstProcess.timer_reg[4] .CLR 6*generalRstProcess.timer_reg[5] .CLR 6*generalRstProcess.timer_reg[6] .CLR 6*generalRstProcess.timer_reg[7] .CLR Ÿ6*generalRstProcess.timer_reg[8] .CLR ß6*generalRstProcess.timer_reg[9] PRE 6*genReset_s_reg .CLR 6*generalRstProcess.timer_reg[0] /CLR 6*generalRstProcess.timer_reg[10] /CLR 6*generalRstProcess.timer_reg[11] /CLR 6*generalRstProcess.timer_reg[12] /CLR 6*generalRstProcess.timer_reg[13] /CLR 6*generalRstProcess.timer_reg[14] /CLR 6*generalRstProcess.timer_reg[15] /CLR 6*generalRstProcess.timer_reg[16] /CLR 6*generalRstProcess.timer_reg[17] /CLR 6*generalRstProcess.timer_reg[18] /CLR 6*generalRstProcess.timer_reg[19] .CLR 6*generalRstProcess.timer_reg[1] /CLR 6*generalRstProcess.timer_reg[20] /CLR 6*generalRstProcess.timer_reg[21] /CLR 6*generalRstProcess.timer_reg[22] /CLR 6*generalRstProcess.timer_reg[23] /CLR 6*generalRstProcess.timer_reg[24] /CLR 6*generalRstProcess.timer_reg[25] .CLR 6*generalRstProcess.timer_reg[2] .CLR 6*generalRstProcess.timer_reg[3] .CLR 6*generalRstProcess.timer_reg[4] .CLR 6*generalRstProcess.timer_reg[5] .CLR 6*generalRstProcess.timer_reg[6] .CLR 6*generalRstProcess.timer_reg[7] .CLR 6*generalRstProcess.timer_reg[8] .CLR 6*generalRstProcess.timer_reg[9] PRE 6*genReset_s_reg .CLR 6*generalRstProcess.timer_reg[0] /CLR 6*generalRstProcess.timer_reg[10] /CLR 6*generalRstProcess.timer_reg[11] /CLR 6*generalRstProcess.timer_reg[12] /CLR 6*generalRstProcess.timer_reg[13] /CLR 6*generalRstProcess.timer_reg[14] /CLR 6*generalRstProcess.timer_reg[15] /CLR 6*generalRstProcess.timer_reg[16] /CLR 6*generalRstProcess.timer_reg[17] /CLR 6*generalRstProcess.timer_reg[18] /CLR 6*generalRstProcess.timer_reg[19] .CLR 6*generalRstProcess.timer_reg[1] /CLR  6*generalRstProcess.timer_reg[20] /CLR à6*generalRstProcess.timer_reg[21] /CLR Ġ6*generalRstProcess.timer_reg[22] /CLR Š6*generalRstProcess.timer_reg[23] /CLR Ơ6*generalRstProcess.timer_reg[24] /CLR Ǡ6*generalRstProcess.timer_reg[25] .CLR 6*generalRstProcess.timer_reg[2] .CLR 6*generalRstProcess.timer_reg[3] .CLR 6*generalRstProcess.timer_reg[4] .CLR 6*generalRstProcess.timer_reg[5] .CLR 6*generalRstProcess.timer_reg[6] .CLR 6*generalRstProcess.timer_reg[7] .CLR 6*generalRstProcess.timer_reg[8] .CLR 6*generalRstProcess.timer_reg[9] PRE ݠ6*genReset_s_reg .CLR 6*generalRstProcess.timer_reg[0] /CLR 6*generalRstProcess.timer_reg[10] /CLR 6*generalRstProcess.timer_reg[11] /CLR 6*generalRstProcess.timer_reg[12] /CLR 6*generalRstProcess.timer_reg[13] /CLR 6*generalRstProcess.timer_reg[14] /CLR 6*generalRstProcess.timer_reg[15] /CLR 6*generalRstProcess.timer_reg[16] /CLR 6*generalRstProcess.timer_reg[17] /CLR 6*generalRstProcess.timer_reg[18] /CLR 6*generalRstProcess.timer_reg[19] .CLR 6*generalRstProcess.timer_reg[1] /CLR 6*generalRstProcess.timer_reg[20] /CLR 6*generalRstProcess.timer_reg[21] /CLR 6*generalRstProcess.timer_reg[22] /CLR 6*generalRstProcess.timer_reg[23] /CLR 6*generalRstProcess.timer_reg[24] /CLR 6*generalRstProcess.timer_reg[25] .CLR 6*generalRstProcess.timer_reg[2] .CLR 6*generalRstProcess.timer_reg[3] .CLR 6*generalRstProcess.timer_reg[4] .CLR 6*generalRstProcess.timer_reg[5] .CLR 6*generalRstProcess.timer_reg[6] .CLR 6*generalRstProcess.timer_reg[7] .CLR 6*generalRstProcess.timer_reg[8] .CLR 6*generalRstProcess.timer_reg[9] PRE 6*genReset_s_reg .CLR 6*generalRstProcess.timer_reg[0] /CLR 6*generalRstProcess.timer_reg[10] /CLR 6*generalRstProcess.timer_reg[11] /CLR 6*generalRstProcess.timer_reg[12] /CLR 6*generalRstProcess.timer_reg[13] /CLR 6*generalRstProcess.timer_reg[14] /CLR 6*generalRstProcess.timer_reg[15] /CLR 6*generalRstProcess.timer_reg[16] /CLR 6*generalRstProcess.timer_reg[17] /CLR 6*generalRstProcess.timer_reg[18] /CLR 6*generalRstProcess.timer_reg[19] .CLR 6*generalRstProcess.timer_reg[1] /CLR 6*generalRstProcess.timer_reg[20] /CLR 6*generalRstProcess.timer_reg[21] /CLR 6*generalRstProcess.timer_reg[22] /CLR 6*generalRstProcess.timer_reg[23] /CLR 6*generalRstProcess.timer_reg[24] /CLR 6*generalRstProcess.timer_reg[25] .CLR 6*generalRstProcess.timer_reg[2] .CLR 6*generalRstProcess.timer_reg[3] .CLR 6*generalRstProcess.timer_reg[4] .CLR 6*generalRstProcess.timer_reg[5] .CLR 6*generalRstProcess.timer_reg[6] .CLR 6*generalRstProcess.timer_reg[7] .CLR 6*generalRstProcess.timer_reg[8] .CLR 6*generalRstProcess.timer_reg[9] PRE ѡ6*genReset_s_reg .CLR ܡ6*generalRstProcess.timer_reg[0] /CLR 6*generalRstProcess.timer_reg[10] /CLR 6*generalRstProcess.timer_reg[11] /CLR 6*generalRstProcess.timer_reg[12] /CLR 6*generalRstProcess.timer_reg[13] /CLR 6*generalRstProcess.timer_reg[14] /CLR 6*generalRstProcess.timer_reg[15] /CLR 6*generalRstProcess.timer_reg[16] /CLR 6*generalRstProcess.timer_reg[17] /CLR 6*generalRstProcess.timer_reg[18] /CLR 6*generalRstProcess.timer_reg[19] .CLR ݡ6*generalRstProcess.timer_reg[1] /CLR 6*generalRstProcess.timer_reg[20] /CLR 6*generalRstProcess.timer_reg[21] /CLR 6*generalRstProcess.timer_reg[22] /CLR 6*generalRstProcess.timer_reg[23] /CLR 6*generalRstProcess.timer_reg[24] /CLR 6*generalRstProcess.timer_reg[25] .CLR ޡ6*generalRstProcess.timer_reg[2] .CLR ߡ6*generalRstProcess.timer_reg[3] .CLR 6*generalRstProcess.timer_reg[4] .CLR 6*generalRstProcess.timer_reg[5] .CLR 6*generalRstProcess.timer_reg[6] .CLR 6*generalRstProcess.timer_reg[7] .CLR 6*generalRstProcess.timer_reg[8] .CLR 6*generalRstProcess.timer_reg[9] PRE 6*genReset_s_reg .CLR 6*generalRstProcess.timer_reg[0] /CLR 6*generalRstProcess.timer_reg[10] /CLR 6*generalRstProcess.timer_reg[11] /CLR 6*generalRstProcess.timer_reg[12] /CLR 6*generalRstProcess.timer_reg[13] /CLR 6*generalRstProcess.timer_reg[14] /CLR 6*generalRstProcess.timer_reg[15] /CLR 6*generalRstProcess.timer_reg[16] /CLR 6*generalRstProcess.timer_reg[17] /CLR 6*generalRstProcess.timer_reg[18] /CLR 6*generalRstProcess.timer_reg[19] .CLR 6*generalRstProcess.timer_reg[1] /CLR 6*generalRstProcess.timer_reg[20] /CLR 6*generalRstProcess.timer_reg[21] /CLR 6*generalRstProcess.timer_reg[22] /CLR 6*generalRstProcess.timer_reg[23] /CLR 6*generalRstProcess.timer_reg[24] /CLR 6*generalRstProcess.timer_reg[25] .CLR 6*generalRstProcess.timer_reg[2] .CLR 6*generalRstProcess.timer_reg[3] .CLR 6*generalRstProcess.timer_reg[4] .CLR 6*generalRstProcess.timer_reg[5] .CLR 6*generalRstProcess.timer_reg[6] .CLR 6*generalRstProcess.timer_reg[7] .CLR 6*generalRstProcess.timer_reg[8] .CLR 6*generalRstProcess.timer_reg[9] PRE Ӣ6*genReset_s_reg .CLR ޢ6*generalRstProcess.timer_reg[0] /CLR 6*generalRstProcess.timer_reg[10] /CLR 6*generalRstProcess.timer_reg[11] /CLR 6*generalRstProcess.timer_reg[12] /CLR 6*generalRstProcess.timer_reg[13] /CLR 6*generalRstProcess.timer_reg[14] /CLR 6*generalRstProcess.timer_reg[15] /CLR 6*generalRstProcess.timer_reg[16] /CLR 6*generalRstProcess.timer_reg[17] /CLR 6*generalRstProcess.timer_reg[18] /CLR 6*generalRstProcess.timer_reg[19] .CLR ߢ6*generalRstProcess.timer_reg[1] /CLR 6*generalRstProcess.timer_reg[20] /CLR 6*generalRstProcess.timer_reg[21] /CLR 6*generalRstProcess.timer_reg[22] /CLR 6*generalRstProcess.timer_reg[23] /CLR 6*generalRstProcess.timer_reg[24] /CLR 6*generalRstProcess.timer_reg[25] .CLR 6*generalRstProcess.timer_reg[2] .CLR 6*generalRstProcess.timer_reg[3] .CLR 6*generalRstProcess.timer_reg[4] .CLR 6*generalRstProcess.timer_reg[5] .CLR 6*generalRstProcess.timer_reg[6] .CLR 6*generalRstProcess.timer_reg[7] .CLR 6*generalRstProcess.timer_reg[8] .CLR 6*generalRstProcess.timer_reg[9] PRE 6*genReset_s_reg .CLR 6*generalRstProcess.timer_reg[0] /CLR 6*generalRstProcess.timer_reg[10] /CLR 6*generalRstProcess.timer_reg[11] /CLR 6*generalRstProcess.timer_reg[12] /CLR 6*generalRstProcess.timer_reg[13] /CLR 6*generalRstProcess.timer_reg[14] /CLR 6*generalRstProcess.timer_reg[15] /CLR 6*generalRstProcess.timer_reg[16] /CLR 6*generalRstProcess.timer_reg[17] /CLR 6*generalRstProcess.timer_reg[18] /CLR 6*generalRstProcess.timer_reg[19] .CLR 6*generalRstProcess.timer_reg[1] /CLR 6*generalRstProcess.timer_reg[20] /CLR 6*generalRstProcess.timer_reg[21] /CLR 6*generalRstProcess.timer_reg[22] /CLR 6*generalRstProcess.timer_reg[23] /CLR 6*generalRstProcess.timer_reg[24] /CLR 6*generalRstProcess.timer_reg[25] .CLR 6*generalRstProcess.timer_reg[2] .CLR 6*generalRstProcess.timer_reg[3] .CLR 6*generalRstProcess.timer_reg[4] .CLR 6*generalRstProcess.timer_reg[5] .CLR 6*generalRstProcess.timer_reg[6] .CLR 6*generalRstProcess.timer_reg[7] .CLR 6*generalRstProcess.timer_reg[8] .CLR 6*generalRstProcess.timer_reg[9] PRE ǣ6*genReset_s_reg .CLR ң6*generalRstProcess.timer_reg[0] /CLR ܣ6*generalRstProcess.timer_reg[10] /CLR ݣ6*generalRstProcess.timer_reg[11] /CLR ޣ6*generalRstProcess.timer_reg[12] /CLR ߣ6*generalRstProcess.timer_reg[13] /CLR 6*generalRstProcess.timer_reg[14] /CLR 6*generalRstProcess.timer_reg[15] /CLR 6*generalRstProcess.timer_reg[16] /CLR 6*generalRstProcess.timer_reg[17] /CLR 6*generalRstProcess.timer_reg[18] /CLR 6*generalRstProcess.timer_reg[19] .CLR ӣ6*generalRstProcess.timer_reg[1] /CLR 6*generalRstProcess.timer_reg[20] /CLR 6*generalRstProcess.timer_reg[21] /CLR 6*generalRstProcess.timer_reg[22] /CLR 6*generalRstProcess.timer_reg[23] /CLR 6*generalRstProcess.timer_reg[24] /CLR 6*generalRstProcess.timer_reg[25] .CLR ԣ6*generalRstProcess.timer_reg[2] .CLR գ6*generalRstProcess.timer_reg[3] .CLR ֣6*generalRstProcess.timer_reg[4] .CLR ף6*generalRstProcess.timer_reg[5] .CLR أ6*generalRstProcess.timer_reg[6] .CLR ٣6*generalRstProcess.timer_reg[7] .CLR ڣ6*generalRstProcess.timer_reg[8] .CLR ۣ6*generalRstProcess.timer_reg[9] PRE 6*genReset_s_regeWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1018BLUT cell ctrl_regs_inst/resetOnEven_gen.resetDurationCnter_s[3]_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.resetDurationCnter_s_reg[0]/CLR, i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.resetDurationCnter_s_reg[1]/CLR, i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.resetDurationCnter_s_reg[2]/CLR, i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.resetDurationCnter_s_reg[3]/CLR, i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.rst_rstoneven_o_reg/CLR i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.sta_headerLocked_async_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell ctrl_regs_inst/resetOnEven_gen.resetDurationCnter_s[3]_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.resetDurationCnter_s_reg[0]/CLR, i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.resetDurationCnter_s_reg[1]/CLR, i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.resetDurationCnter_s_reg[2]/CLR, i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.resetDurationCnter_s_reg[3]/CLR, i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.rst_rstoneven_o_reg/CLR i_tcds2_if/cmp_lpgbtfpga_uplink/lpgbtfpga_framealigner_inst/resetOnEven_gen.sta_headerLocked_async_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 7.+resetOnEven_gen.resetDurationCnter_s[3]_i_3 * ;CLR 8*+resetOnEven_gen.resetDurationCnter_s_reg[0] ;CLR 8*+resetOnEven_gen.resetDurationCnter_s_reg[1] ;CLR 8*+resetOnEven_gen.resetDurationCnter_s_reg[2] ;CLR 8*+resetOnEven_gen.resetDurationCnter_s_reg[3] 3CLR 8*#resetOnEven_gen.rst_rstoneven_o_reg :CLR 8**resetOnEven_gen.sta_headerLocked_async_reg fWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1028B LUT cell ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell ctrl_regs_inst/reset_synchronizer_reset_all_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_mgt_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.3 1.%reset_synchronizer_reset_all_inst_i_1 * PRE 9*rst_in_meta_reg PRE 9*rst_in_out_reg PRE 9*rst_in_sync1_reg PRE 9*rst_in_sync2_reg PRE 9*rst_in_sync3_reg PRE 9*rst_in_meta_reg PRE 9*rst_in_out_reg PRE 9*rst_in_sync1_reg PRE 9*rst_in_sync2_reg PRE 9*rst_in_sync3_reg<gWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1038BLUT cell eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/MGT_RESET.RESET_INT_PIPE_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/MGT_RESET.RESET_INT_PIPE_reg/PRE eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/MGT_RESET.RESET_INT_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/MGT_RESET.RESET_INT_PIPE_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/MGT_RESET.RESET_INT_PIPE_reg/PRE eth/phy/U0/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/MGT_RESET.RESET_INT_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.* (<MGT_RESET.RESET_INT_PIPE_i_1 *W ,PRE <*MGT_RESET.RESET_INT_PIPE_reg 'PRE <*MGT_RESET.RESET_INT_regnhWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1048BLUT cell eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regiWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1058BLUT cell eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__0 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regwjWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1068BLUT cell eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_meta_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync1_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync2_reg/PRE eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_meta_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync1_reg/PRE, eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync2_reg/PRE eth/phy/U0/transceiver_inst/gig_ethernet_pcs_pma_0_gt_i/inst/gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regkWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1078BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. /gbtRxReset_s_i_1 *" PRE /*gbtRxReset_s_reglWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1088BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. /gbtTxReset_s_i_1 *" PRE /*gbtTxReset_s_regmWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1098BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. / mgtRxReset_s0 *" PRE /*mgtRxReset_s_regnWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1108BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtRxReset_s_i_1__9 *" PRE /*gbtRxReset_s_regoWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1118BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtTxReset_s_i_1__9 *" PRE /*gbtTxReset_s_reg pWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1128BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. / mgtRxReset_s0 *" PRE /*mgtRxReset_s_regqWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1138BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." /gbtRxReset_s_i_1__10 *" PRE /*gbtRxReset_s_regrWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1148BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." /gbtTxReset_s_i_1__10 *" PRE /*gbtTxReset_s_reg sWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1158BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. / mgtRxReset_s0 *" PRE /*mgtRxReset_s_regtWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1168BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtRxReset_s_i_1__0 *" PRE /*gbtRxReset_s_reguWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1178BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtTxReset_s_i_1__0 *" PRE /*gbtTxReset_s_regvWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1188BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. / mgtRxReset_s0 *" PRE /*mgtRxReset_s_regwWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1198BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtRxReset_s_i_1__1 *" PRE /*gbtRxReset_s_regxWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1208BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtTxReset_s_i_1__1 *" PRE /*gbtTxReset_s_regyWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1218BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. / mgtRxReset_s0 *" PRE /*mgtRxReset_s_regzWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1228BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtRxReset_s_i_1__2 *" PRE /*gbtRxReset_s_reg{Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1238BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtTxReset_s_i_1__2 *" PRE /*gbtTxReset_s_reg|Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1248BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. / mgtRxReset_s0 *" PRE /*mgtRxReset_s_reg}Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1258BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtRxReset_s_i_1__3 *" PRE /*gbtRxReset_s_reg~Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1268BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtTxReset_s_i_1__3 *" PRE /*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1278BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. / mgtRxReset_s0 *" PRE /*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1288BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtRxReset_s_i_1__4 *" PRE /*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1298BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtTxReset_s_i_1__4 *" PRE /*gbtTxReset_s_regyWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1308BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. / i_mgt_ip_i_2 * PRE 1*rst_in_meta_reg PRE 1*rst_in_out_reg PRE 1*rst_in_sync1_reg PRE 1*rst_in_sync2_reg PRE 1*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1318BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. /i_mgt_ip_i_2__0 * PRE 1*rst_in_meta_reg PRE 1*rst_in_out_reg PRE 1*rst_in_sync1_reg PRE 1*rst_in_sync2_reg PRE 1*rst_in_sync3_reg PRE ũ<*rst_in_meta_reg PRE Ʃ<*rst_in_out_reg PRE ǩ<*rst_in_sync1_reg PRE ȩ<*rst_in_sync2_reg PRE ɩ<*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1328BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. /i_mgt_ip_i_2__1 * PRE 1*rst_in_meta_reg PRE 1*rst_in_out_reg PRE 1*rst_in_sync1_reg PRE 1*rst_in_sync2_reg PRE 1*rst_in_sync3_reg PRE ߬<*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1338BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. /i_mgt_ip_i_2__2 * PRE 1*rst_in_meta_reg PRE 1*rst_in_out_reg PRE 1*rst_in_sync1_reg PRE 1*rst_in_sync2_reg PRE 1*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1348BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. /i_mgt_ip_i_2__3 * PRE 1*rst_in_meta_reg PRE 1*rst_in_out_reg PRE 1*rst_in_sync1_reg PRE 1*rst_in_sync2_reg PRE 1*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1358BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. /i_mgt_ip_i_2__4 * PRE 1*rst_in_meta_reg PRE 1*rst_in_out_reg PRE 1*rst_in_sync1_reg PRE 1*rst_in_sync2_reg PRE 1*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1368BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. /i_mgt_ip_i_2__5 * PRE 1*rst_in_meta_reg PRE 1*rst_in_out_reg PRE 1*rst_in_sync1_reg PRE 1*rst_in_sync2_reg PRE 1*rst_in_sync3_reg PRE ǹ<*rst_in_meta_reg PRE ȹ<*rst_in_out_reg PRE ɹ<*rst_in_sync1_reg PRE ʹ<*rst_in_sync2_reg PRE ˹<*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1378BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. /i_mgt_ip_i_2__6 * PRE 1*rst_in_meta_reg PRE 1*rst_in_out_reg PRE 1*rst_in_sync1_reg PRE 1*rst_in_sync2_reg PRE 1*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1388BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. /i_mgt_ip_i_2__7 * PRE 1*rst_in_meta_reg PRE 1*rst_in_out_reg PRE 1*rst_in_sync1_reg PRE 1*rst_in_sync2_reg PRE 1*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1398BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. /i_mgt_ip_i_2__8 * PRE 1*rst_in_meta_reg PRE 1*rst_in_out_reg PRE 1*rst_in_sync1_reg PRE 1*rst_in_sync2_reg PRE 1*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1408BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. /i_mgt_ip_i_2__9 * PRE 1*rst_in_meta_reg PRE 1*rst_in_out_reg PRE 1*rst_in_sync1_reg PRE 1*rst_in_sync2_reg PRE 1*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1418BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. / i_mgt_ip_i_3 * PRE 1*rst_in_meta_reg PRE 1*rst_in_out_reg PRE 1*rst_in_sync1_reg PRE 1*rst_in_sync2_reg PRE 1*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1428BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. / mgtRxReset_s0 *" PRE /*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1438BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. /mgtTxReset_s_i_1 *" PRE /*mgtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1448BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtRxReset_s_i_1__5 *" PRE /*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1458BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtTxReset_s_i_1__5 *" PRE /*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1468BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. / mgtRxReset_s0 *" PRE /*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1478BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtRxReset_s_i_1__6 *" PRE /*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1488BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtTxReset_s_i_1__6 *" PRE /*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1498BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. / mgtRxReset_s0 *" PRE /*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1508BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtRxReset_s_i_1__7 *" PRE /*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1518BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtTxReset_s_i_1__7 *" PRE /*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1528BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. / mgtRxReset_s0 *" PRE /*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1538BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtRxReset_s_i_1__8 *" PRE /*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1548BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! /gbtTxReset_s_i_1__8 *" PRE /*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1558BLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. / mgtRxReset_s0 *" PRE /*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1568BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. -rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1578BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg& Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1588B LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.6 41(gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2 * ;CLR 1*+gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0] 0CLR /* gbtBank_Clk_gen[0].cnt_reg[0][0] 0CLR /* gbtBank_Clk_gen[0].cnt_reg[0][1] 0CLR /* gbtBank_Clk_gen[0].cnt_reg[0][2] 0CLR /* gbtBank_Clk_gen[0].cnt_reg[0][3] 0CLR /* gbtBank_Clk_gen[0].cnt_reg[0][4] 0CLR /* gbtBank_Clk_gen[0].cnt_reg[0][5] 0CLR /* gbtBank_Clk_gen[0].cnt_reg[0][6] 0CLR /* gbtBank_Clk_gen[0].cnt_reg[0][7] 8CLR /*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0] 8CLR /*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1] 8CLR /*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2] 8CLR /*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3] 8CLR /*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4] 8CLR /*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5]Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1598BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1mgtRxReady_s_i_1 *I CLR /*mgtRxReady_s_reg %CLR /*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1608BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg,Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1618BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1628B LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.8 61*gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2 * =CLR 1*-gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10] 2CLR /*"gbtBank_Clk_gen[10].cnt_reg[10][0] 2CLR /*"gbtBank_Clk_gen[10].cnt_reg[10][1] 2CLR /*"gbtBank_Clk_gen[10].cnt_reg[10][2] 2CLR /*"gbtBank_Clk_gen[10].cnt_reg[10][3] 2CLR /*"gbtBank_Clk_gen[10].cnt_reg[10][4] 2CLR /*"gbtBank_Clk_gen[10].cnt_reg[10][5] 2CLR /*"gbtBank_Clk_gen[10].cnt_reg[10][6] 2CLR /*"gbtBank_Clk_gen[10].cnt_reg[10][7] :CLR /**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0] :CLR /**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1] :CLR /**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2] :CLR /**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3] :CLR /**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4] :CLR /**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1638BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! 1mgtRxReady_s_i_1__9 *I CLR /*mgtRxReady_s_reg %CLR /*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1648BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg,Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1658BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE ¦<*rst_in_out_reg PRE æ<*rst_in_sync1_reg PRE Ħ<*rst_in_sync2_reg PRE Ŧ<*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1668B LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.8 61*gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2 * =CLR 1*-gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11] 2CLR /*"gbtBank_Clk_gen[11].cnt_reg[11][0] 2CLR /*"gbtBank_Clk_gen[11].cnt_reg[11][1] 2CLR /*"gbtBank_Clk_gen[11].cnt_reg[11][2] 2CLR /*"gbtBank_Clk_gen[11].cnt_reg[11][3] 2CLR /*"gbtBank_Clk_gen[11].cnt_reg[11][4] 2CLR /*"gbtBank_Clk_gen[11].cnt_reg[11][5] 2CLR /*"gbtBank_Clk_gen[11].cnt_reg[11][6] 2CLR /*"gbtBank_Clk_gen[11].cnt_reg[11][7] :CLR /**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0] :CLR /**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1] :CLR /**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2] :CLR /**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3] :CLR /**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4] :CLR /**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1678BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1mgtRxReady_s_i_1__10 *I CLR /*mgtRxReady_s_reg %CLR /*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1688BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1rst_in_meta_i_1__1 * PRE ѩ<*rst_in_meta_reg PRE ҩ<*rst_in_out_reg PRE ө<*rst_in_sync1_reg PRE ԩ<*rst_in_sync2_reg PRE թ<*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1698BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. ک<rst_in_meta_i_1__3 * PRE ۩<*rst_in_meta_reg PRE ܩ<*rst_in_out_reg PRE ݩ<*rst_in_sync1_reg PRE ީ<*rst_in_sync2_reg PRE ߩ<*rst_in_sync3_reg& Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1708B LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.6 41(gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2 * ;CLR 1*+gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1] 0CLR /* gbtBank_Clk_gen[1].cnt_reg[1][0] 0CLR /* gbtBank_Clk_gen[1].cnt_reg[1][1] 0CLR /* gbtBank_Clk_gen[1].cnt_reg[1][2] 0CLR /* gbtBank_Clk_gen[1].cnt_reg[1][3] 0CLR /* gbtBank_Clk_gen[1].cnt_reg[1][4] 0CLR /* gbtBank_Clk_gen[1].cnt_reg[1][5] 0CLR /* gbtBank_Clk_gen[1].cnt_reg[1][6] 0CLR /* gbtBank_Clk_gen[1].cnt_reg[1][7] 8CLR /*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] 8CLR /*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1] 8CLR /*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2] 8CLR /*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3] 8CLR /*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4] 8CLR /*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1718BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! 1mgtRxReady_s_i_1__0 *I CLR /*mgtRxReady_s_reg %CLR /*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1728BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1738BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg& Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1748B LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.6 41(gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2 * ;CLR 1*+gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2] 0CLR /* gbtBank_Clk_gen[2].cnt_reg[2][0] 0CLR /* gbtBank_Clk_gen[2].cnt_reg[2][1] 0CLR /* gbtBank_Clk_gen[2].cnt_reg[2][2] 0CLR /* gbtBank_Clk_gen[2].cnt_reg[2][3] 0CLR /* gbtBank_Clk_gen[2].cnt_reg[2][4] 0CLR /* gbtBank_Clk_gen[2].cnt_reg[2][5] 0CLR /* gbtBank_Clk_gen[2].cnt_reg[2][6] 0CLR /* gbtBank_Clk_gen[2].cnt_reg[2][7] 8CLR /*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] 8CLR /*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1] 8CLR /*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2] 8CLR /*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3] 8CLR /*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4] 8CLR /*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1758BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! 1mgtRxReady_s_i_1__1 *I CLR /*mgtRxReady_s_reg %CLR /*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1768BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1778BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg& Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1788B LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.6 41(gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2 * ;CLR 1*+gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3] 0CLR /* gbtBank_Clk_gen[3].cnt_reg[3][0] 0CLR /* gbtBank_Clk_gen[3].cnt_reg[3][1] 0CLR /* gbtBank_Clk_gen[3].cnt_reg[3][2] 0CLR /* gbtBank_Clk_gen[3].cnt_reg[3][3] 0CLR /* gbtBank_Clk_gen[3].cnt_reg[3][4] 0CLR /* gbtBank_Clk_gen[3].cnt_reg[3][5] 0CLR /* gbtBank_Clk_gen[3].cnt_reg[3][6] 0CLR /* gbtBank_Clk_gen[3].cnt_reg[3][7] 8CLR /*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0] 8CLR /*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1] 8CLR /*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2] 8CLR /*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3] 8CLR /*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4] 8CLR /*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1798BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! 1mgtRxReady_s_i_1__2 *I CLR /*mgtRxReady_s_reg %CLR /*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1808BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1818BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg& Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1828B LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.6 41(gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2 * ;CLR 1*+gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4] 0CLR /* gbtBank_Clk_gen[4].cnt_reg[4][0] 0CLR /* gbtBank_Clk_gen[4].cnt_reg[4][1] 0CLR /* gbtBank_Clk_gen[4].cnt_reg[4][2] 0CLR /* gbtBank_Clk_gen[4].cnt_reg[4][3] 0CLR /* gbtBank_Clk_gen[4].cnt_reg[4][4] 0CLR /* gbtBank_Clk_gen[4].cnt_reg[4][5] 0CLR /* gbtBank_Clk_gen[4].cnt_reg[4][6] 0CLR /* gbtBank_Clk_gen[4].cnt_reg[4][7] 8CLR /*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0] 8CLR /*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1] 8CLR /*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2] 8CLR /*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3] 8CLR /*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4] 8CLR /*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1838BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! 1mgtRxReady_s_i_1__3 *I CLR /*mgtRxReady_s_reg %CLR /*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1848BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1858BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. ¶<rst_in_meta_i_1__3 * PRE ö<*rst_in_meta_reg PRE Ķ<*rst_in_out_reg PRE Ŷ<*rst_in_sync1_reg PRE ƶ<*rst_in_sync2_reg PRE Ƕ<*rst_in_sync3_reg& Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1868B LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.6 41(gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2 * ;CLR 1*+gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5] 0CLR /* gbtBank_Clk_gen[5].cnt_reg[5][0] 0CLR /* gbtBank_Clk_gen[5].cnt_reg[5][1] 0CLR /* gbtBank_Clk_gen[5].cnt_reg[5][2] 0CLR /* gbtBank_Clk_gen[5].cnt_reg[5][3] 0CLR /* gbtBank_Clk_gen[5].cnt_reg[5][4] 0CLR /* gbtBank_Clk_gen[5].cnt_reg[5][5] 0CLR /* gbtBank_Clk_gen[5].cnt_reg[5][6] 0CLR /* gbtBank_Clk_gen[5].cnt_reg[5][7] 8CLR /*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0] 8CLR /*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1] 8CLR /*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2] 8CLR /*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3] 8CLR /*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4] 8CLR /*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1878BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! 1mgtRxReady_s_i_1__4 *I CLR /*mgtRxReady_s_reg %CLR /*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1888BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1rst_in_meta_i_1__1 * PRE ӹ<*rst_in_meta_reg PRE Թ<*rst_in_out_reg PRE չ<*rst_in_sync1_reg PRE ֹ<*rst_in_sync2_reg PRE ׹<*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1898BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. ܹ<rst_in_meta_i_1__3 * PRE ݹ<*rst_in_meta_reg PRE ޹<*rst_in_out_reg PRE ߹<*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg& Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1908B LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.6 41(gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2 * ;CLR 1*+gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6] 0CLR /* gbtBank_Clk_gen[6].cnt_reg[6][0] 0CLR /* gbtBank_Clk_gen[6].cnt_reg[6][1] 0CLR /* gbtBank_Clk_gen[6].cnt_reg[6][2] 0CLR /* gbtBank_Clk_gen[6].cnt_reg[6][3] 0CLR /* gbtBank_Clk_gen[6].cnt_reg[6][4] 0CLR /* gbtBank_Clk_gen[6].cnt_reg[6][5] 0CLR /* gbtBank_Clk_gen[6].cnt_reg[6][6] 0CLR /* gbtBank_Clk_gen[6].cnt_reg[6][7] 8CLR /*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0] 8CLR /*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1] 8CLR /*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2] 8CLR /*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3] 8CLR /*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4] 8CLR /*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1918BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! 1mgtRxReady_s_i_1__5 *I CLR /*mgtRxReady_s_reg %CLR /*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1928BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1938BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg& Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1948B LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.6 41(gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2 * ;CLR 1*+gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7] 0CLR /* gbtBank_Clk_gen[7].cnt_reg[7][0] 0CLR /* gbtBank_Clk_gen[7].cnt_reg[7][1] 0CLR /* gbtBank_Clk_gen[7].cnt_reg[7][2] 0CLR /* gbtBank_Clk_gen[7].cnt_reg[7][3] 0CLR /* gbtBank_Clk_gen[7].cnt_reg[7][4] 0CLR /* gbtBank_Clk_gen[7].cnt_reg[7][5] 0CLR /* gbtBank_Clk_gen[7].cnt_reg[7][6] 0CLR /* gbtBank_Clk_gen[7].cnt_reg[7][7] 8CLR /*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0] 8CLR /*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1] 8CLR /*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2] 8CLR /*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3] 8CLR /*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4] 8CLR /*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1958BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! 1mgtRxReady_s_i_1__6 *I CLR /*mgtRxReady_s_reg %CLR /*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1968BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1978BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg& Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1988B LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.6 41(gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2 * ;CLR 1*+gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8] 0CLR /* gbtBank_Clk_gen[8].cnt_reg[8][0] 0CLR /* gbtBank_Clk_gen[8].cnt_reg[8][1] 0CLR /* gbtBank_Clk_gen[8].cnt_reg[8][2] 0CLR /* gbtBank_Clk_gen[8].cnt_reg[8][3] 0CLR /* gbtBank_Clk_gen[8].cnt_reg[8][4] 0CLR /* gbtBank_Clk_gen[8].cnt_reg[8][5] 0CLR /* gbtBank_Clk_gen[8].cnt_reg[8][6] 0CLR /* gbtBank_Clk_gen[8].cnt_reg[8][7] 8CLR /*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0] 8CLR /*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1] 8CLR /*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2] 8CLR /*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3] 8CLR /*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4] 8CLR /*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#1998BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! 1mgtRxReady_s_i_1__7 *I CLR /*mgtRxReady_s_reg %CLR /*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2008BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2018BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg& Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2028B LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR, g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR g_gbt_bank[0].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.6 41(gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2 * ;CLR 1*+gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9] 0CLR /* gbtBank_Clk_gen[9].cnt_reg[9][0] 0CLR /* gbtBank_Clk_gen[9].cnt_reg[9][1] 0CLR /* gbtBank_Clk_gen[9].cnt_reg[9][2] 0CLR /* gbtBank_Clk_gen[9].cnt_reg[9][3] 0CLR /* gbtBank_Clk_gen[9].cnt_reg[9][4] 0CLR /* gbtBank_Clk_gen[9].cnt_reg[9][5] 0CLR /* gbtBank_Clk_gen[9].cnt_reg[9][6] 0CLR /* gbtBank_Clk_gen[9].cnt_reg[9][7] 8CLR /*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0] 8CLR /*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1] 8CLR /*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2] 8CLR /*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3] 8CLR /*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4] 8CLR /*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2038BLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[0].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! 1mgtRxReady_s_i_1__8 *I CLR /*mgtRxReady_s_reg %CLR /*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2048BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_i_1__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_i_1__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtRxReset_s_i_1__11 *" PRE 1*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2058BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_i_1__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_i_1__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtTxReset_s_i_1__11 *" PRE 1*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2068BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1 mgtRxReset_s0 *" PRE 1*mgtRxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2078BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_i_1__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_i_1__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtRxReset_s_i_1__21 *" PRE 1*gbtRxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2088BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_i_1__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_i_1__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtTxReset_s_i_1__21 *" PRE 1*gbtTxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2098BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1 mgtRxReset_s0 *" PRE 1*mgtRxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2108BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_i_1__22, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_i_1__22, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtRxReset_s_i_1__22 *" PRE 1*gbtRxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2118BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_i_1__22, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_i_1__22, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtTxReset_s_i_1__22 *" PRE 1*gbtTxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2128BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1 mgtRxReset_s0 *" PRE 1*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2138BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtRxReset_s_i_1__12 *" PRE 1*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2148BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_i_1__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_i_1__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtTxReset_s_i_1__12 *" PRE 1*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2158BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1 mgtRxReset_s0 *" PRE 1*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2168BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_i_1__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_i_1__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtRxReset_s_i_1__13 *" PRE 1*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2178BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_i_1__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_i_1__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtTxReset_s_i_1__13 *" PRE 1*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2188BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1 mgtRxReset_s0 *" PRE 1*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2198BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_i_1__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_i_1__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtRxReset_s_i_1__14 *" PRE 1*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2208BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_i_1__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_i_1__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtTxReset_s_i_1__14 *" PRE 1*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2218BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1 mgtRxReset_s0 *" PRE 1*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2228BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_i_1__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_i_1__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtRxReset_s_i_1__15 *" PRE 1*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2238BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_i_1__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_i_1__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtTxReset_s_i_1__15 *" PRE 1*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2248BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1 mgtRxReset_s0 *" PRE 1*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2258BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_i_1__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_i_1__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtRxReset_s_i_1__16 *" PRE 1*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2268BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_i_1__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_i_1__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtTxReset_s_i_1__16 *" PRE 1*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2278BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1i_mgt_ip_i_2__11 * PRE 3*rst_in_meta_reg PRE 3*rst_in_out_reg PRE 3*rst_in_sync1_reg PRE 3*rst_in_sync2_reg PRE 3*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2288BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1i_mgt_ip_i_2__12 * PRE 3*rst_in_meta_reg PRE 3*rst_in_out_reg PRE 3*rst_in_sync1_reg PRE 3*rst_in_sync2_reg PRE 3*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2298BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1i_mgt_ip_i_2__13 * PRE 3*rst_in_meta_reg PRE 3*rst_in_out_reg PRE 3*rst_in_sync1_reg PRE 3*rst_in_sync2_reg PRE 3*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2308BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1i_mgt_ip_i_2__14 * PRE 3*rst_in_meta_reg PRE 3*rst_in_out_reg PRE 3*rst_in_sync1_reg PRE 3*rst_in_sync2_reg PRE 3*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2318BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1i_mgt_ip_i_2__15 * PRE 3*rst_in_meta_reg PRE 3*rst_in_out_reg PRE 3*rst_in_sync1_reg PRE 3*rst_in_sync2_reg PRE 3*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2328BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1i_mgt_ip_i_2__16 * PRE 3*rst_in_meta_reg PRE 3*rst_in_out_reg PRE 3*rst_in_sync1_reg PRE 3*rst_in_sync2_reg PRE 3*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2338BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1i_mgt_ip_i_2__17 * PRE 3*rst_in_meta_reg PRE 3*rst_in_out_reg PRE 3*rst_in_sync1_reg PRE 3*rst_in_sync2_reg PRE 3*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2348BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1i_mgt_ip_i_2__18 * PRE 3*rst_in_meta_reg PRE 3*rst_in_out_reg PRE 3*rst_in_sync1_reg PRE 3*rst_in_sync2_reg PRE 3*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2358BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1i_mgt_ip_i_2__19 * PRE Â4*rst_in_meta_reg PRE ǂ4*rst_in_out_reg PRE Ă4*rst_in_sync1_reg PRE ł4*rst_in_sync2_reg PRE Ƃ4*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2368BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1i_mgt_ip_i_2__20 * PRE 4*rst_in_meta_reg PRE 4*rst_in_out_reg PRE 4*rst_in_sync1_reg PRE 4*rst_in_sync2_reg PRE 4*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2378BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1i_mgt_ip_i_2__21 * PRE 3*rst_in_meta_reg PRE 3*rst_in_out_reg PRE 3*rst_in_sync1_reg PRE 3*rst_in_sync2_reg PRE 3*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2388BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1i_mgt_ip_i_3__11 * PRE 3*rst_in_meta_reg PRE 3*rst_in_out_reg PRE 3*rst_in_sync1_reg PRE 3*rst_in_sync2_reg PRE 3*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2398BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1 mgtRxReset_s0 *" PRE 1*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2408BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! 1mgtTxReset_s_i_1__0 *" PRE 1*mgtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2418BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_i_1__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_i_1__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtRxReset_s_i_1__17 *" PRE 1*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2428BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_i_1__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_i_1__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 1gbtTxReset_s_i_1__17 *" PRE 1*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2438BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1 mgtRxReset_s0 *" PRE 1*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2448BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_i_1__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_i_1__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 2gbtRxReset_s_i_1__18 *" PRE 2*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2458BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_i_1__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_i_1__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 2gbtTxReset_s_i_1__18 *" PRE 2*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2468BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 2 mgtRxReset_s0 *" PRE 2*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2478BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_i_1__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_i_1__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 2gbtRxReset_s_i_1__19 *" PRE 2*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2488BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_i_1__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_i_1__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 2gbtTxReset_s_i_1__19 *" PRE 2*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2498BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 2 mgtRxReset_s0 *" PRE 2*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2508BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_i_1__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_i_1__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 2gbtRxReset_s_i_1__20 *" PRE 2*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2518BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_i_1__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_i_1__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 2gbtTxReset_s_i_1__20 *" PRE 2*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2528BLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 2 mgtRxReset_s0 *" PRE 2*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2538BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 1rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2548BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2558B LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 73+gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__0 * ;CLR 4*+gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0] 0CLR 1* gbtBank_Clk_gen[0].cnt_reg[0][0] 0CLR 1* gbtBank_Clk_gen[0].cnt_reg[0][1] 0CLR 1* gbtBank_Clk_gen[0].cnt_reg[0][2] 0CLR 1* gbtBank_Clk_gen[0].cnt_reg[0][3] 0CLR 1* gbtBank_Clk_gen[0].cnt_reg[0][4] 0CLR 1* gbtBank_Clk_gen[0].cnt_reg[0][5] 0CLR 1* gbtBank_Clk_gen[0].cnt_reg[0][6] 0CLR 1* gbtBank_Clk_gen[0].cnt_reg[0][7] 8CLR 1*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0] 8CLR 1*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1] 8CLR 1*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2] 8CLR 1*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3] 8CLR 1*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4] 8CLR 1*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2568BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 3mgtRxReady_s_i_1__11 *I CLR 1*mgtRxReady_s_reg %CLR 1*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2578BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 3rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg,Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2588BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2598B LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.; 93-gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__0 * =CLR 4*-gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10] 2CLR 1*"gbtBank_Clk_gen[10].cnt_reg[10][0] 2CLR 1*"gbtBank_Clk_gen[10].cnt_reg[10][1] 2CLR 1*"gbtBank_Clk_gen[10].cnt_reg[10][2] 2CLR 1*"gbtBank_Clk_gen[10].cnt_reg[10][3] 2CLR 1*"gbtBank_Clk_gen[10].cnt_reg[10][4] 2CLR 1*"gbtBank_Clk_gen[10].cnt_reg[10][5] 2CLR 1*"gbtBank_Clk_gen[10].cnt_reg[10][6] 2CLR 1*"gbtBank_Clk_gen[10].cnt_reg[10][7] :CLR 1**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0] :CLR 1**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1] :CLR 1**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2] :CLR 1**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3] :CLR 1**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4] :CLR 1**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2608BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__21, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 3mgtRxReady_s_i_1__21 *I CLR 1*mgtRxReady_s_reg %CLR 1*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2618BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 3rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg,Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2628BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2638B LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.; 93-gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__0 * =CLR 4*-gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11] 2CLR 1*"gbtBank_Clk_gen[11].cnt_reg[11][0] 2CLR 1*"gbtBank_Clk_gen[11].cnt_reg[11][1] 2CLR 1*"gbtBank_Clk_gen[11].cnt_reg[11][2] 2CLR 1*"gbtBank_Clk_gen[11].cnt_reg[11][3] 2CLR 1*"gbtBank_Clk_gen[11].cnt_reg[11][4] 2CLR 1*"gbtBank_Clk_gen[11].cnt_reg[11][5] 2CLR 1*"gbtBank_Clk_gen[11].cnt_reg[11][6] 2CLR 1*"gbtBank_Clk_gen[11].cnt_reg[11][7] :CLR 1**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0] :CLR 1**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1] :CLR 1**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2] :CLR 1**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3] :CLR 1**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4] :CLR 1**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2648BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__22, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__22, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 3mgtRxReady_s_i_1__22 *I CLR 1*mgtRxReady_s_reg %CLR 1*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2658BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 3rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2668BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2678B LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 73+gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0 * ;CLR 4*+gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1] 0CLR 1* gbtBank_Clk_gen[1].cnt_reg[1][0] 0CLR 1* gbtBank_Clk_gen[1].cnt_reg[1][1] 0CLR 1* gbtBank_Clk_gen[1].cnt_reg[1][2] 0CLR 1* gbtBank_Clk_gen[1].cnt_reg[1][3] 0CLR 1* gbtBank_Clk_gen[1].cnt_reg[1][4] 0CLR 1* gbtBank_Clk_gen[1].cnt_reg[1][5] 0CLR 1* gbtBank_Clk_gen[1].cnt_reg[1][6] 0CLR 1* gbtBank_Clk_gen[1].cnt_reg[1][7] 8CLR 1*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] 8CLR 1*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1] 8CLR 1*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2] 8CLR 1*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3] 8CLR 1*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4] 8CLR 1*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2688BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__12, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 3mgtRxReady_s_i_1__12 *I CLR 1*mgtRxReady_s_reg %CLR 1*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2698BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 3rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2708BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2718B LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 73+gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0 * ;CLR 4*+gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2] 0CLR 1* gbtBank_Clk_gen[2].cnt_reg[2][0] 0CLR 1* gbtBank_Clk_gen[2].cnt_reg[2][1] 0CLR 1* gbtBank_Clk_gen[2].cnt_reg[2][2] 0CLR 1* gbtBank_Clk_gen[2].cnt_reg[2][3] 0CLR 1* gbtBank_Clk_gen[2].cnt_reg[2][4] 0CLR 1* gbtBank_Clk_gen[2].cnt_reg[2][5] 0CLR 1* gbtBank_Clk_gen[2].cnt_reg[2][6] 0CLR 1* gbtBank_Clk_gen[2].cnt_reg[2][7] 8CLR 1*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] 8CLR 1*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1] 8CLR 1*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2] 8CLR 1*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3] 8CLR 1*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4] 8CLR 1*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2728BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__13, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 3mgtRxReady_s_i_1__13 *I CLR 1*mgtRxReady_s_reg %CLR 1*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2738BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 3rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2748BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2758B LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 73+gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0 * ;CLR 4*+gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3] 0CLR 1* gbtBank_Clk_gen[3].cnt_reg[3][0] 0CLR 1* gbtBank_Clk_gen[3].cnt_reg[3][1] 0CLR 1* gbtBank_Clk_gen[3].cnt_reg[3][2] 0CLR 1* gbtBank_Clk_gen[3].cnt_reg[3][3] 0CLR 1* gbtBank_Clk_gen[3].cnt_reg[3][4] 0CLR 1* gbtBank_Clk_gen[3].cnt_reg[3][5] 0CLR 1* gbtBank_Clk_gen[3].cnt_reg[3][6] 0CLR 1* gbtBank_Clk_gen[3].cnt_reg[3][7] 8CLR 1*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0] 8CLR 1*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1] 8CLR 1*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2] 8CLR 1*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3] 8CLR 1*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4] 8CLR 1*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2768BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__14, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 3mgtRxReady_s_i_1__14 *I CLR 1*mgtRxReady_s_reg %CLR 1*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2778BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 3rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2788BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2798B LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 73+gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__0 * ;CLR 4*+gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4] 0CLR 1* gbtBank_Clk_gen[4].cnt_reg[4][0] 0CLR 1* gbtBank_Clk_gen[4].cnt_reg[4][1] 0CLR 1* gbtBank_Clk_gen[4].cnt_reg[4][2] 0CLR 1* gbtBank_Clk_gen[4].cnt_reg[4][3] 0CLR 1* gbtBank_Clk_gen[4].cnt_reg[4][4] 0CLR 1* gbtBank_Clk_gen[4].cnt_reg[4][5] 0CLR 1* gbtBank_Clk_gen[4].cnt_reg[4][6] 0CLR 1* gbtBank_Clk_gen[4].cnt_reg[4][7] 8CLR 1*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0] 8CLR 1*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1] 8CLR 1*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2] 8CLR 1*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3] 8CLR 1*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4] 8CLR 1*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2808BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__15, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 3mgtRxReady_s_i_1__15 *I CLR 1*mgtRxReady_s_reg %CLR 1*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2818BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 3rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2828BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2838B LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 73+gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__0 * ;CLR 4*+gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5] 0CLR 1* gbtBank_Clk_gen[5].cnt_reg[5][0] 0CLR 1* gbtBank_Clk_gen[5].cnt_reg[5][1] 0CLR 1* gbtBank_Clk_gen[5].cnt_reg[5][2] 0CLR 1* gbtBank_Clk_gen[5].cnt_reg[5][3] 0CLR 1* gbtBank_Clk_gen[5].cnt_reg[5][4] 0CLR 1* gbtBank_Clk_gen[5].cnt_reg[5][5] 0CLR 1* gbtBank_Clk_gen[5].cnt_reg[5][6] 0CLR 1* gbtBank_Clk_gen[5].cnt_reg[5][7] 8CLR 1*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0] 8CLR 1*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1] 8CLR 1*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2] 8CLR 1*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3] 8CLR 1*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4] 8CLR 1*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2848BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__16, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 3mgtRxReady_s_i_1__16 *I CLR 1*mgtRxReady_s_reg %CLR 1*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2858BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 3rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2868BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2878B LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 73+gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__0 * ;CLR 4*+gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6] 0CLR 1* gbtBank_Clk_gen[6].cnt_reg[6][0] 0CLR 1* gbtBank_Clk_gen[6].cnt_reg[6][1] 0CLR 1* gbtBank_Clk_gen[6].cnt_reg[6][2] 0CLR 1* gbtBank_Clk_gen[6].cnt_reg[6][3] 0CLR 1* gbtBank_Clk_gen[6].cnt_reg[6][4] 0CLR 1* gbtBank_Clk_gen[6].cnt_reg[6][5] 0CLR 1* gbtBank_Clk_gen[6].cnt_reg[6][6] 0CLR 1* gbtBank_Clk_gen[6].cnt_reg[6][7] 8CLR 1*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0] 8CLR 1*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1] 8CLR 1*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2] 8CLR 1*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3] 8CLR 1*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4] 8CLR 1*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2888BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__17, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 3mgtRxReady_s_i_1__17 *I CLR 1*mgtRxReady_s_reg %CLR 1*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2898BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 3rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2908BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2918B LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 74+gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__0 * ;CLR 4*+gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7] 0CLR 1* gbtBank_Clk_gen[7].cnt_reg[7][0] 0CLR 1* gbtBank_Clk_gen[7].cnt_reg[7][1] 0CLR 1* gbtBank_Clk_gen[7].cnt_reg[7][2] 0CLR 1* gbtBank_Clk_gen[7].cnt_reg[7][3] 0CLR 1* gbtBank_Clk_gen[7].cnt_reg[7][4] 0CLR 1* gbtBank_Clk_gen[7].cnt_reg[7][5] 0CLR 1* gbtBank_Clk_gen[7].cnt_reg[7][6] 0CLR 1* gbtBank_Clk_gen[7].cnt_reg[7][7] 8CLR 1*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0] 8CLR 1*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1] 8CLR 1*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2] 8CLR 1*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3] 8CLR 1*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4] 8CLR 1*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2928BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__18, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 3mgtRxReady_s_i_1__18 *I CLR 2*mgtRxReady_s_reg %CLR 2*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2938BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2948BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2958B LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 7ӄ4+gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__0 * ;CLR 4*+gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8] 0CLR 1* gbtBank_Clk_gen[8].cnt_reg[8][0] 0CLR 1* gbtBank_Clk_gen[8].cnt_reg[8][1] 0CLR 1* gbtBank_Clk_gen[8].cnt_reg[8][2] 0CLR 1* gbtBank_Clk_gen[8].cnt_reg[8][3] 0CLR 1* gbtBank_Clk_gen[8].cnt_reg[8][4] 0CLR 1* gbtBank_Clk_gen[8].cnt_reg[8][5] 0CLR 1* gbtBank_Clk_gen[8].cnt_reg[8][6] 0CLR 1* gbtBank_Clk_gen[8].cnt_reg[8][7] 8CLR 1*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0] 8CLR 1*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1] 8CLR 1*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2] 8CLR 1*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3] 8CLR 1*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4] 8CLR 1*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2968BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__19, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4mgtRxReady_s_i_1__19 *I CLR 2*mgtRxReady_s_reg %CLR 2*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2978BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2988BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#2998B LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR, g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR g_gbt_bank[1].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 74+gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__0 * ;CLR 4*+gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9] 0CLR 1* gbtBank_Clk_gen[9].cnt_reg[9][0] 0CLR 1* gbtBank_Clk_gen[9].cnt_reg[9][1] 0CLR 1* gbtBank_Clk_gen[9].cnt_reg[9][2] 0CLR 1* gbtBank_Clk_gen[9].cnt_reg[9][3] 0CLR 1* gbtBank_Clk_gen[9].cnt_reg[9][4] 0CLR 1* gbtBank_Clk_gen[9].cnt_reg[9][5] 0CLR 1* gbtBank_Clk_gen[9].cnt_reg[9][6] 0CLR 1* gbtBank_Clk_gen[9].cnt_reg[9][7] 8CLR 1*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0] 8CLR 1*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1] 8CLR 1*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2] 8CLR 1*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3] 8CLR 1*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4] 8CLR 1*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3008BLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__20, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[1].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4mgtRxReady_s_i_1__20 *I CLR 2*mgtRxReady_s_reg %CLR 2*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3018BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_i_1__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_i_1__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." ߍ4gbtRxReset_s_i_1__23 *" PRE 4*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3028BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_i_1__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_i_1__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." ލ4gbtTxReset_s_i_1__23 *" PRE 4*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3038BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4 mgtRxReset_s0 *" PRE 4*mgtRxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3048BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_i_1__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_i_1__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtRxReset_s_i_1__33 *" PRE 4*gbtRxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3058BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_i_1__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_i_1__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtTxReset_s_i_1__33 *" PRE 4*gbtTxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3068BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4 mgtRxReset_s0 *" PRE 4*mgtRxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3078BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_i_1__34, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_i_1__34, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." Վ4gbtRxReset_s_i_1__34 *" PRE 4*gbtRxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3088BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_i_1__34, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_i_1__34, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." Ԏ4gbtTxReset_s_i_1__34 *" PRE 4*gbtTxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3098BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4 mgtRxReset_s0 *" PRE ֎4*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3108BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtRxReset_s_i_1__24 *" PRE 4*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3118BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_i_1__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_i_1__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtTxReset_s_i_1__24 *" PRE ߎ4*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3128BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4 mgtRxReset_s0 *" PRE 4*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3138BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_i_1__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_i_1__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." ɏ4gbtRxReset_s_i_1__25 *" PRE 4*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3148BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_i_1__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_i_1__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." ȏ4gbtTxReset_s_i_1__25 *" PRE 4*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3158BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4 mgtRxReset_s0 *" PRE ʏ4*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3168BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_i_1__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_i_1__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtRxReset_s_i_1__26 *" PRE ԏ4*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3178BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_i_1__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_i_1__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtTxReset_s_i_1__26 *" PRE ӏ4*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3188BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. ُ4 mgtRxReset_s0 *" PRE 4*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3198BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_i_1__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_i_1__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtRxReset_s_i_1__27 *" PRE 4*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3208BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_i_1__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_i_1__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtTxReset_s_i_1__27 *" PRE 4*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3218BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4 mgtRxReset_s0 *" PRE 4*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3228BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_i_1__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_i_1__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtRxReset_s_i_1__28 *" PRE Ȑ4*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3238BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_i_1__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_i_1__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtTxReset_s_i_1__28 *" PRE ǐ4*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3248BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4i_mgt_ip_i_2__23 * PRE 5*rst_in_meta_reg PRE 5*rst_in_out_reg PRE 5*rst_in_sync1_reg PRE 5*rst_in_sync2_reg PRE 5*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3258BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4i_mgt_ip_i_2__24 * PRE 5*rst_in_meta_reg PRE 5*rst_in_out_reg PRE 5*rst_in_sync1_reg PRE 5*rst_in_sync2_reg PRE 5*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3268BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4i_mgt_ip_i_2__25 * PRE 5*rst_in_meta_reg PRE 5*rst_in_out_reg PRE 5*rst_in_sync1_reg PRE 5*rst_in_sync2_reg PRE 5*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3278BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4i_mgt_ip_i_2__26 * PRE 6*rst_in_meta_reg PRE 6*rst_in_out_reg PRE 6*rst_in_sync1_reg PRE 6*rst_in_sync2_reg PRE 6*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3288BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4i_mgt_ip_i_2__27 * PRE 6*rst_in_meta_reg PRE 6*rst_in_out_reg PRE 6*rst_in_sync1_reg PRE 6*rst_in_sync2_reg PRE 6*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3298BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4i_mgt_ip_i_2__28 * PRE ׈6*rst_in_meta_reg PRE ۈ6*rst_in_out_reg PRE ؈6*rst_in_sync1_reg PRE و6*rst_in_sync2_reg PRE ڈ6*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3308BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4i_mgt_ip_i_2__29 * PRE 6*rst_in_meta_reg PRE 6*rst_in_out_reg PRE 6*rst_in_sync1_reg PRE 6*rst_in_sync2_reg PRE 6*rst_in_sync3_reg PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3318BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4i_mgt_ip_i_2__30 * PRE 6*rst_in_meta_reg PRE 6*rst_in_out_reg PRE 6*rst_in_sync1_reg PRE 6*rst_in_sync2_reg PRE 6*rst_in_sync3_reg PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3328BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4i_mgt_ip_i_2__31 * PRE 6*rst_in_meta_reg PRE 6*rst_in_out_reg PRE 6*rst_in_sync1_reg PRE 6*rst_in_sync2_reg PRE 6*rst_in_sync3_reg PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3338BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4i_mgt_ip_i_2__32 * PRE 6*rst_in_meta_reg PRE 6*rst_in_out_reg PRE 6*rst_in_sync1_reg PRE 6*rst_in_sync2_reg PRE 6*rst_in_sync3_reg PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3348BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4i_mgt_ip_i_2__33 * PRE 5*rst_in_meta_reg PRE 5*rst_in_out_reg PRE 5*rst_in_sync1_reg PRE 5*rst_in_sync2_reg PRE 5*rst_in_sync3_reg PRE щ=*rst_in_meta_reg PRE ҉=*rst_in_out_reg PRE Ӊ=*rst_in_sync1_reg PRE ԉ=*rst_in_sync2_reg PRE Չ=*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3358BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4i_mgt_ip_i_3__23 * PRE 5*rst_in_meta_reg PRE 5*rst_in_out_reg PRE 5*rst_in_sync1_reg PRE 5*rst_in_sync2_reg PRE 5*rst_in_sync3_reg PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3368BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. ͐4 mgtRxReset_s0 *" PRE 4*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3378BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! 4mgtTxReset_s_i_1__1 *" PRE 4*mgtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3388BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_i_1__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_i_1__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtRxReset_s_i_1__29 *" PRE 4*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3398BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_i_1__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_i_1__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtTxReset_s_i_1__29 *" PRE 4*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3408BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4 mgtRxReset_s0 *" PRE 4*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3418BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_i_1__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_i_1__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtRxReset_s_i_1__30 *" PRE ʑ4*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3428BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_i_1__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_i_1__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtTxReset_s_i_1__30 *" PRE ɑ4*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3438BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. ϑ4 mgtRxReset_s0 *" PRE 4*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3448BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_i_1__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_i_1__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtRxReset_s_i_1__31 *" PRE 4*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3458BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_i_1__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_i_1__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtTxReset_s_i_1__31 *" PRE 4*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3468BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4 mgtRxReset_s0 *" PRE 4*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3478BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_i_1__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_i_1__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtRxReset_s_i_1__32 *" PRE 4*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3488BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_i_1__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_i_1__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 4gbtTxReset_s_i_1__32 *" PRE 4*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3498BLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Ò4 mgtRxReset_s0 *" PRE 4*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3508BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 4rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3518BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3528B LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 75+gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__1 * ;CLR 6*+gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0] 0CLR 4* gbtBank_Clk_gen[0].cnt_reg[0][0] 0CLR 4* gbtBank_Clk_gen[0].cnt_reg[0][1] 0CLR 4* gbtBank_Clk_gen[0].cnt_reg[0][2] 0CLR 4* gbtBank_Clk_gen[0].cnt_reg[0][3] 0CLR 4* gbtBank_Clk_gen[0].cnt_reg[0][4] 0CLR 4* gbtBank_Clk_gen[0].cnt_reg[0][5] 0CLR 4* gbtBank_Clk_gen[0].cnt_reg[0][6] 0CLR 4* gbtBank_Clk_gen[0].cnt_reg[0][7] 8CLR ʊ4*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0] 8CLR Ɋ4*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1] 8CLR Ȋ4*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2] 8CLR NJ4*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3] 8CLR Ɗ4*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4] 8CLR Ŋ4*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3538BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__23, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 5mgtRxReady_s_i_1__23 *I CLR 4*mgtRxReady_s_reg %CLR 4*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3548BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 5rst_in_meta_i_1__1 * PRE ݉=*rst_in_meta_reg PRE މ=*rst_in_out_reg PRE ߉=*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg,Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3558BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. =rst_in_meta_i_1__3 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3568B LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.; 95-gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__1 * =CLR 6*-gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10] 2CLR 4*"gbtBank_Clk_gen[10].cnt_reg[10][0] 2CLR 4*"gbtBank_Clk_gen[10].cnt_reg[10][1] 2CLR 4*"gbtBank_Clk_gen[10].cnt_reg[10][2] 2CLR 4*"gbtBank_Clk_gen[10].cnt_reg[10][3] 2CLR 4*"gbtBank_Clk_gen[10].cnt_reg[10][4] 2CLR ߋ4*"gbtBank_Clk_gen[10].cnt_reg[10][5] 2CLR ދ4*"gbtBank_Clk_gen[10].cnt_reg[10][6] 2CLR ݋4*"gbtBank_Clk_gen[10].cnt_reg[10][7] :CLR 4**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0] :CLR 4**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1] :CLR 4**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2] :CLR 4**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3] :CLR 4**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4] :CLR 4**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3578BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__33, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 5mgtRxReady_s_i_1__33 *I CLR 4*mgtRxReady_s_reg %CLR 4*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3588BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 5rst_in_meta_i_1__1 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg,Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3598BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. =rst_in_meta_i_1__3 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3608B LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.; 95-gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__1 * =CLR 6*-gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11] 2CLR 4*"gbtBank_Clk_gen[11].cnt_reg[11][0] 2CLR 4*"gbtBank_Clk_gen[11].cnt_reg[11][1] 2CLR 4*"gbtBank_Clk_gen[11].cnt_reg[11][2] 2CLR 4*"gbtBank_Clk_gen[11].cnt_reg[11][3] 2CLR 4*"gbtBank_Clk_gen[11].cnt_reg[11][4] 2CLR 4*"gbtBank_Clk_gen[11].cnt_reg[11][5] 2CLR 4*"gbtBank_Clk_gen[11].cnt_reg[11][6] 2CLR 4*"gbtBank_Clk_gen[11].cnt_reg[11][7] :CLR 4**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0] :CLR 4**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1] :CLR 4**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2] :CLR 4**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3] :CLR 4**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4] :CLR 4**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3618BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__34, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__34, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 5mgtRxReady_s_i_1__34 *I CLR 4*mgtRxReady_s_reg %CLR 4*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3628BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 5rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3638BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3648B LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 75+gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1 * ;CLR 6*+gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1] 0CLR 4* gbtBank_Clk_gen[1].cnt_reg[1][0] 0CLR 4* gbtBank_Clk_gen[1].cnt_reg[1][1] 0CLR 4* gbtBank_Clk_gen[1].cnt_reg[1][2] 0CLR 4* gbtBank_Clk_gen[1].cnt_reg[1][3] 0CLR 4* gbtBank_Clk_gen[1].cnt_reg[1][4] 0CLR 4* gbtBank_Clk_gen[1].cnt_reg[1][5] 0CLR 4* gbtBank_Clk_gen[1].cnt_reg[1][6] 0CLR 4* gbtBank_Clk_gen[1].cnt_reg[1][7] 8CLR Њ4*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] 8CLR ϊ4*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1] 8CLR Ί4*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2] 8CLR ͊4*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3] 8CLR ̊4*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4] 8CLR ˊ4*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3658BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__24, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 5mgtRxReady_s_i_1__24 *I CLR 4*mgtRxReady_s_reg %CLR 4*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3668BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 5rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3678BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3688B LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 75+gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__1 * ;CLR 6*+gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2] 0CLR 4* gbtBank_Clk_gen[2].cnt_reg[2][0] 0CLR 4* gbtBank_Clk_gen[2].cnt_reg[2][1] 0CLR 4* gbtBank_Clk_gen[2].cnt_reg[2][2] 0CLR 4* gbtBank_Clk_gen[2].cnt_reg[2][3] 0CLR 4* gbtBank_Clk_gen[2].cnt_reg[2][4] 0CLR 4* gbtBank_Clk_gen[2].cnt_reg[2][5] 0CLR 4* gbtBank_Clk_gen[2].cnt_reg[2][6] 0CLR 4* gbtBank_Clk_gen[2].cnt_reg[2][7] 8CLR ֊4*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] 8CLR Պ4*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1] 8CLR Ԋ4*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2] 8CLR ӊ4*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3] 8CLR Ҋ4*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4] 8CLR ъ4*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3698BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__25, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 5mgtRxReady_s_i_1__25 *I CLR 4*mgtRxReady_s_reg %CLR 4*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3708BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 5rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3718BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3728B LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 76+gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1 * ;CLR 6*+gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3] 0CLR 4* gbtBank_Clk_gen[3].cnt_reg[3][0] 0CLR 4* gbtBank_Clk_gen[3].cnt_reg[3][1] 0CLR 4* gbtBank_Clk_gen[3].cnt_reg[3][2] 0CLR 4* gbtBank_Clk_gen[3].cnt_reg[3][3] 0CLR 4* gbtBank_Clk_gen[3].cnt_reg[3][4] 0CLR 4* gbtBank_Clk_gen[3].cnt_reg[3][5] 0CLR 4* gbtBank_Clk_gen[3].cnt_reg[3][6] 0CLR 4* gbtBank_Clk_gen[3].cnt_reg[3][7] 8CLR ܊4*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0] 8CLR ۊ4*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1] 8CLR ڊ4*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2] 8CLR ي4*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3] 8CLR ؊4*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4] 8CLR ׊4*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3738BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__26, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6mgtRxReady_s_i_1__26 *I CLR ׏4*mgtRxReady_s_reg %CLR ؏4*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3748BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. ߂6rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3758BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3768B LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 76+gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__1 * ;CLR 6*+gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4] 0CLR 4* gbtBank_Clk_gen[4].cnt_reg[4][0] 0CLR 4* gbtBank_Clk_gen[4].cnt_reg[4][1] 0CLR 4* gbtBank_Clk_gen[4].cnt_reg[4][2] 0CLR 4* gbtBank_Clk_gen[4].cnt_reg[4][3] 0CLR 4* gbtBank_Clk_gen[4].cnt_reg[4][4] 0CLR 4* gbtBank_Clk_gen[4].cnt_reg[4][5] 0CLR 4* gbtBank_Clk_gen[4].cnt_reg[4][6] 0CLR 4* gbtBank_Clk_gen[4].cnt_reg[4][7] 8CLR 4*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0] 8CLR 4*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1] 8CLR 4*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2] 8CLR ߊ4*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3] 8CLR ފ4*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4] 8CLR ݊4*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3778BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__27, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." օ6mgtRxReady_s_i_1__27 *I CLR 4*mgtRxReady_s_reg %CLR 4*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3788BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. ņ6rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3798BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3808B LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 76+gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__1 * ;CLR 6*+gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5] 0CLR 4* gbtBank_Clk_gen[5].cnt_reg[5][0] 0CLR 4* gbtBank_Clk_gen[5].cnt_reg[5][1] 0CLR 4* gbtBank_Clk_gen[5].cnt_reg[5][2] 0CLR 4* gbtBank_Clk_gen[5].cnt_reg[5][3] 0CLR 4* gbtBank_Clk_gen[5].cnt_reg[5][4] 0CLR 4* gbtBank_Clk_gen[5].cnt_reg[5][5] 0CLR 4* gbtBank_Clk_gen[5].cnt_reg[5][6] 0CLR 4* gbtBank_Clk_gen[5].cnt_reg[5][7] 8CLR 4*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0] 8CLR 4*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1] 8CLR 4*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2] 8CLR 4*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3] 8CLR 4*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4] 8CLR 4*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3818BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__28, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6mgtRxReady_s_i_1__28 *I CLR ː4*mgtRxReady_s_reg %CLR ̐4*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3828BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6rst_in_meta_i_1__1 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3838BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. <rst_in_meta_i_1__3 * PRE <*rst_in_meta_reg PRE <*rst_in_out_reg PRE <*rst_in_sync1_reg PRE <*rst_in_sync2_reg PRE <*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3848B LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 7͎6+gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__1 * ;CLR 6*+gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6] 0CLR ċ4* gbtBank_Clk_gen[6].cnt_reg[6][0] 0CLR Ë4* gbtBank_Clk_gen[6].cnt_reg[6][1] 0CLR ‹4* gbtBank_Clk_gen[6].cnt_reg[6][2] 0CLR 4* gbtBank_Clk_gen[6].cnt_reg[6][3] 0CLR 4* gbtBank_Clk_gen[6].cnt_reg[6][4] 0CLR 4* gbtBank_Clk_gen[6].cnt_reg[6][5] 0CLR 4* gbtBank_Clk_gen[6].cnt_reg[6][6] 0CLR 4* gbtBank_Clk_gen[6].cnt_reg[6][7] 8CLR 4*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0] 8CLR 4*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1] 8CLR 4*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2] 8CLR 4*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3] 8CLR 4*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4] 8CLR 4*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3858BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__29, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6mgtRxReady_s_i_1__29 *I CLR 4*mgtRxReady_s_reg %CLR 4*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3868BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6rst_in_meta_i_1__1 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3878BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. =rst_in_meta_i_1__3 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3888B LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 76+gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__1 * ;CLR 6*+gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7] 0CLR ̋4* gbtBank_Clk_gen[7].cnt_reg[7][0] 0CLR ˋ4* gbtBank_Clk_gen[7].cnt_reg[7][1] 0CLR ʋ4* gbtBank_Clk_gen[7].cnt_reg[7][2] 0CLR ɋ4* gbtBank_Clk_gen[7].cnt_reg[7][3] 0CLR ȋ4* gbtBank_Clk_gen[7].cnt_reg[7][4] 0CLR Nj4* gbtBank_Clk_gen[7].cnt_reg[7][5] 0CLR Ƌ4* gbtBank_Clk_gen[7].cnt_reg[7][6] 0CLR ŋ4* gbtBank_Clk_gen[7].cnt_reg[7][7] 8CLR 4*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0] 8CLR 4*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1] 8CLR 4*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2] 8CLR 4*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3] 8CLR 4*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4] 8CLR 4*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3898BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__30, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6mgtRxReady_s_i_1__30 *I CLR ͑4*mgtRxReady_s_reg %CLR Α4*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3908BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6rst_in_meta_i_1__1 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3918BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. =rst_in_meta_i_1__3 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3928B LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 76+gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__1 * ;CLR 6*+gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8] 0CLR ԋ4* gbtBank_Clk_gen[8].cnt_reg[8][0] 0CLR Ӌ4* gbtBank_Clk_gen[8].cnt_reg[8][1] 0CLR ҋ4* gbtBank_Clk_gen[8].cnt_reg[8][2] 0CLR ы4* gbtBank_Clk_gen[8].cnt_reg[8][3] 0CLR Ћ4* gbtBank_Clk_gen[8].cnt_reg[8][4] 0CLR ϋ4* gbtBank_Clk_gen[8].cnt_reg[8][5] 0CLR ΋4* gbtBank_Clk_gen[8].cnt_reg[8][6] 0CLR ͋4* gbtBank_Clk_gen[8].cnt_reg[8][7] 8CLR 4*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0] 8CLR 4*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1] 8CLR 4*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2] 8CLR 4*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3] 8CLR 4*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4] 8CLR 4*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3938BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__31, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6mgtRxReady_s_i_1__31 *I CLR 4*mgtRxReady_s_reg %CLR 4*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3948BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. ݕ6rst_in_meta_i_1__1 * PRE Æ=*rst_in_meta_reg PRE Ć=*rst_in_out_reg PRE ņ=*rst_in_sync1_reg PRE Ɔ=*rst_in_sync2_reg PRE dž=*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3958BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. ̆=rst_in_meta_i_1__3 * PRE ͆=*rst_in_meta_reg PRE Ά=*rst_in_out_reg PRE φ=*rst_in_sync1_reg PRE І=*rst_in_sync2_reg PRE ц=*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3968B LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR, g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR g_gbt_bank[2].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 76+gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__1 * ;CLR 6*+gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9] 0CLR ܋4* gbtBank_Clk_gen[9].cnt_reg[9][0] 0CLR ۋ4* gbtBank_Clk_gen[9].cnt_reg[9][1] 0CLR ڋ4* gbtBank_Clk_gen[9].cnt_reg[9][2] 0CLR ً4* gbtBank_Clk_gen[9].cnt_reg[9][3] 0CLR ؋4* gbtBank_Clk_gen[9].cnt_reg[9][4] 0CLR ׋4* gbtBank_Clk_gen[9].cnt_reg[9][5] 0CLR ֋4* gbtBank_Clk_gen[9].cnt_reg[9][6] 0CLR Ջ4* gbtBank_Clk_gen[9].cnt_reg[9][7] 8CLR 4*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0] 8CLR 4*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1] 8CLR 4*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2] 8CLR 4*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3] 8CLR 4*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4] 8CLR 4*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3978BLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__32, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[2].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." Ԙ6mgtRxReady_s_i_1__32 *I CLR 4*mgtRxReady_s_reg %CLR ’4*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3988BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_i_1__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_i_1__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtRxReset_s_i_1__35 *" PRE ž6*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#3998BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_i_1__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_i_1__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtTxReset_s_i_1__35 *" PRE 6*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4008BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Þ6 mgtRxReset_s0 *" PRE 6*mgtRxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4018BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_i_1__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_i_1__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtRxReset_s_i_1__45 *" PRE 6*gbtRxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4028BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_i_1__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_i_1__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtTxReset_s_i_1__45 *" PRE 6*gbtTxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4038BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6 mgtRxReset_s0 *" PRE 6*mgtRxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4048BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_i_1__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_i_1__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtRxReset_s_i_1__46 *" PRE 6*gbtRxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4058BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_i_1__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_i_1__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtTxReset_s_i_1__46 *" PRE 6*gbtTxReset_s_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4068BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6 mgtRxReset_s0 *" PRE 6*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4078BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtRxReset_s_i_1__36 *" PRE 6*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4088BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_i_1__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_i_1__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtTxReset_s_i_1__36 *" PRE 6*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4098BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6 mgtRxReset_s0 *" PRE 6*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4108BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_i_1__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_i_1__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." נ6gbtRxReset_s_i_1__37 *" PRE 6*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4118BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_i_1__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_i_1__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." ֠6gbtTxReset_s_i_1__37 *" PRE 6*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4128BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6 mgtRxReset_s0 *" PRE ؠ6*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4138BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_i_1__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_i_1__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtRxReset_s_i_1__38 *" PRE 6*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4148BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_i_1__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_i_1__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtTxReset_s_i_1__38 *" PRE 6*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4158BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6 mgtRxReset_s0 *" PRE 6*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4168BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_i_1__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_i_1__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." ˡ6gbtRxReset_s_i_1__39 *" PRE 6*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4178BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_i_1__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_i_1__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." ʡ6gbtTxReset_s_i_1__39 *" PRE 6*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4188BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6 mgtRxReset_s0 *" PRE ̡6*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4198BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_i_1__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_i_1__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtRxReset_s_i_1__40 *" PRE ֡6*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4208BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_i_1__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_i_1__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtTxReset_s_i_1__40 *" PRE ա6*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4218BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6i_mgt_ip_i_2__35 * PRE 7*rst_in_meta_reg PRE 7*rst_in_out_reg PRE 7*rst_in_sync1_reg PRE 7*rst_in_sync2_reg PRE 7*rst_in_sync3_reg PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4228BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6i_mgt_ip_i_2__36 * PRE ʊ8*rst_in_meta_reg PRE Ί8*rst_in_out_reg PRE ˊ8*rst_in_sync1_reg PRE ̊8*rst_in_sync2_reg PRE ͊8*rst_in_sync3_reg PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4238BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6i_mgt_ip_i_2__37 * PRE 8*rst_in_meta_reg PRE 8*rst_in_out_reg PRE 8*rst_in_sync1_reg PRE 8*rst_in_sync2_reg PRE 8*rst_in_sync3_reg PRE ә=*rst_in_meta_reg PRE ԙ=*rst_in_out_reg PRE ՙ=*rst_in_sync1_reg PRE ֙=*rst_in_sync2_reg PRE י=*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4248BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6i_mgt_ip_i_2__38 * PRE 8*rst_in_meta_reg PRE 8*rst_in_out_reg PRE 8*rst_in_sync1_reg PRE 8*rst_in_sync2_reg PRE 8*rst_in_sync3_reg PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4258BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6i_mgt_ip_i_2__39 * PRE 8*rst_in_meta_reg PRE 8*rst_in_out_reg PRE 8*rst_in_sync1_reg PRE 8*rst_in_sync2_reg PRE 8*rst_in_sync3_reg PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4268BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6i_mgt_ip_i_2__40 * PRE 8*rst_in_meta_reg PRE 8*rst_in_out_reg PRE 8*rst_in_sync1_reg PRE 8*rst_in_sync2_reg PRE 8*rst_in_sync3_reg PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4278BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6i_mgt_ip_i_2__41 * PRE ȝ8*rst_in_meta_reg PRE ̝8*rst_in_out_reg PRE ɝ8*rst_in_sync1_reg PRE ʝ8*rst_in_sync2_reg PRE ˝8*rst_in_sync3_reg PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4288BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6i_mgt_ip_i_2__42 * PRE 8*rst_in_meta_reg PRE 8*rst_in_out_reg PRE 8*rst_in_sync1_reg PRE 8*rst_in_sync2_reg PRE 8*rst_in_sync3_reg PRE թ=*rst_in_meta_reg PRE ֩=*rst_in_out_reg PRE ש=*rst_in_sync1_reg PRE ة=*rst_in_sync2_reg PRE ٩=*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4298BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6i_mgt_ip_i_2__43 * PRE 8*rst_in_meta_reg PRE 8*rst_in_out_reg PRE 8*rst_in_sync1_reg PRE 8*rst_in_sync2_reg PRE 8*rst_in_sync3_reg PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4308BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6i_mgt_ip_i_2__44 * PRE 8*rst_in_meta_reg PRE 8*rst_in_out_reg PRE 8*rst_in_sync1_reg PRE 8*rst_in_sync2_reg PRE 8*rst_in_sync3_reg PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4318BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_2__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6i_mgt_ip_i_2__45 * PRE 8*rst_in_meta_reg PRE 8*rst_in_out_reg PRE 8*rst_in_sync1_reg PRE 8*rst_in_sync2_reg PRE 8*rst_in_sync3_reg PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4328BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/i_mgt_ip_i_3__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync2_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_init/reset_synchronizer_reset_all_inst/rst_in_sync3_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_all_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6i_mgt_ip_i_3__35 * PRE 8*rst_in_meta_reg PRE 8*rst_in_out_reg PRE 8*rst_in_sync1_reg PRE 8*rst_in_sync2_reg PRE 8*rst_in_sync3_reg PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4338BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. ۡ6 mgtRxReset_s0 *" PRE 6*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4348BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.! 6mgtTxReset_s_i_1__2 *" PRE 6*mgtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4358BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_i_1__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_i_1__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." ͢6gbtRxReset_s_i_1__41 *" PRE 6*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4368BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_i_1__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_i_1__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." ̢6gbtTxReset_s_i_1__41 *" PRE 6*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4378BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6 mgtRxReset_s0 *" PRE ΢6*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4388BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_i_1__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_i_1__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtRxReset_s_i_1__42 *" PRE آ6*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4398BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_i_1__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_i_1__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtTxReset_s_i_1__42 *" PRE ע6*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4408BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. ݢ6 mgtRxReset_s0 *" PRE 6*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4418BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_i_1__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_i_1__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtRxReset_s_i_1__43 *" PRE 6*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4428BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_i_1__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_i_1__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtTxReset_s_i_1__43 *" PRE 6*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4438BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 6 mgtRxReset_s0 *" PRE £6*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4448BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_i_1__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_i_1__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtRxReset_s_i_1__44 *" PRE ̣6*gbtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4458BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_i_1__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_i_1__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 6gbtTxReset_s_i_1__44 *" PRE ˣ6*gbtTxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4468BLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. ѣ6 mgtRxReset_s0 *" PRE 6*mgtRxReset_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4478BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Ù6rst_in_meta_i_1__1 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4488BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. =rst_in_meta_i_1__3 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4498B LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].cnt_reg[0][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 78+gbtBank_Clk_gen[0].rx_clken_sr[0][5]_i_2__2 * ;CLR 8*+gbtBank_Clk_gen[0].RX_FRAMECLK_RDY_i_reg[0] 0CLR ڜ6* gbtBank_Clk_gen[0].cnt_reg[0][0] 0CLR ٜ6* gbtBank_Clk_gen[0].cnt_reg[0][1] 0CLR ؜6* gbtBank_Clk_gen[0].cnt_reg[0][2] 0CLR ל6* gbtBank_Clk_gen[0].cnt_reg[0][3] 0CLR ֜6* gbtBank_Clk_gen[0].cnt_reg[0][4] 0CLR ՜6* gbtBank_Clk_gen[0].cnt_reg[0][5] 0CLR Ԝ6* gbtBank_Clk_gen[0].cnt_reg[0][6] 0CLR Ӝ6* gbtBank_Clk_gen[0].cnt_reg[0][7] 8CLR 6*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][0] 8CLR 6*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][1] 8CLR 6*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][2] 8CLR 6*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][3] 8CLR 6*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][4] 8CLR 6*(gbtBank_Clk_gen[0].rx_clken_sr_reg[0][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4508BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__35, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[0].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 7mgtRxReady_s_i_1__35 *I CLR 6*mgtRxReady_s_reg %CLR 6*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4518BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 8rst_in_meta_i_1__1 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg,Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4528BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. =rst_in_meta_i_1__3 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4538B LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].cnt_reg[10][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.; 98-gbtBank_Clk_gen[10].rx_clken_sr[10][5]_i_2__2 * =CLR 8*-gbtBank_Clk_gen[10].RX_FRAMECLK_RDY_i_reg[10] 2CLR 6*"gbtBank_Clk_gen[10].cnt_reg[10][0] 2CLR 6*"gbtBank_Clk_gen[10].cnt_reg[10][1] 2CLR 6*"gbtBank_Clk_gen[10].cnt_reg[10][2] 2CLR 6*"gbtBank_Clk_gen[10].cnt_reg[10][3] 2CLR 6*"gbtBank_Clk_gen[10].cnt_reg[10][4] 2CLR 6*"gbtBank_Clk_gen[10].cnt_reg[10][5] 2CLR 6*"gbtBank_Clk_gen[10].cnt_reg[10][6] 2CLR 6*"gbtBank_Clk_gen[10].cnt_reg[10][7] :CLR ̜6**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][0] :CLR ˜6**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][1] :CLR ʜ6**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][2] :CLR ɜ6**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][3] :CLR Ȝ6**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][4] :CLR ǜ6**gbtBank_Clk_gen[10].rx_clken_sr_reg[10][5]Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4548BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__45, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[10].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 8mgtRxReady_s_i_1__45 *I CLR 6*mgtRxReady_s_reg %CLR 6*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4558BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. ҄8rst_in_meta_i_1__1 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg,Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4568BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. =rst_in_meta_i_1__3 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4578B LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].cnt_reg[11][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.; 98-gbtBank_Clk_gen[11].rx_clken_sr[11][5]_i_2__2 * =CLR 8*-gbtBank_Clk_gen[11].RX_FRAMECLK_RDY_i_reg[11] 2CLR 6*"gbtBank_Clk_gen[11].cnt_reg[11][0] 2CLR 6*"gbtBank_Clk_gen[11].cnt_reg[11][1] 2CLR 6*"gbtBank_Clk_gen[11].cnt_reg[11][2] 2CLR 6*"gbtBank_Clk_gen[11].cnt_reg[11][3] 2CLR 6*"gbtBank_Clk_gen[11].cnt_reg[11][4] 2CLR 6*"gbtBank_Clk_gen[11].cnt_reg[11][5] 2CLR 6*"gbtBank_Clk_gen[11].cnt_reg[11][6] 2CLR 6*"gbtBank_Clk_gen[11].cnt_reg[11][7] :CLR Ҝ6**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][0] :CLR ќ6**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][1] :CLR М6**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][2] :CLR Ϝ6**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][3] :CLR Μ6**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][4] :CLR ͜6**gbtBank_Clk_gen[11].rx_clken_sr_reg[11][5]Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4588BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__46, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[11].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." ɇ8mgtRxReady_s_i_1__46 *I CLR 6*mgtRxReady_s_reg %CLR 6*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4598BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 8rst_in_meta_i_1__1 * PRE Ŗ=*rst_in_meta_reg PRE Ɩ=*rst_in_out_reg PRE ǖ=*rst_in_sync1_reg PRE Ȗ=*rst_in_sync2_reg PRE ɖ=*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4608BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Ζ=rst_in_meta_i_1__3 * PRE ϖ=*rst_in_meta_reg PRE Ж=*rst_in_out_reg PRE і=*rst_in_sync1_reg PRE Җ=*rst_in_sync2_reg PRE Ӗ=*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4618B LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].cnt_reg[1][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 7ڌ8+gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2 * ;CLR 8*+gbtBank_Clk_gen[1].RX_FRAMECLK_RDY_i_reg[1] 0CLR 6* gbtBank_Clk_gen[1].cnt_reg[1][0] 0CLR 6* gbtBank_Clk_gen[1].cnt_reg[1][1] 0CLR 6* gbtBank_Clk_gen[1].cnt_reg[1][2] 0CLR ߜ6* gbtBank_Clk_gen[1].cnt_reg[1][3] 0CLR ޜ6* gbtBank_Clk_gen[1].cnt_reg[1][4] 0CLR ݜ6* gbtBank_Clk_gen[1].cnt_reg[1][5] 0CLR ܜ6* gbtBank_Clk_gen[1].cnt_reg[1][6] 0CLR ۜ6* gbtBank_Clk_gen[1].cnt_reg[1][7] 8CLR 6*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] 8CLR 6*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1] 8CLR 6*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2] 8CLR 6*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3] 8CLR 6*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4] 8CLR 6*(gbtBank_Clk_gen[1].rx_clken_sr_reg[1][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4628BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__36, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 8mgtRxReady_s_i_1__36 *I CLR 6*mgtRxReady_s_reg %CLR 6*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4638BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 8rst_in_meta_i_1__1 * PRE ߙ=*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4648BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. =rst_in_meta_i_1__3 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4658B LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].cnt_reg[2][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 78+gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2 * ;CLR 8*+gbtBank_Clk_gen[2].RX_FRAMECLK_RDY_i_reg[2] 0CLR 6* gbtBank_Clk_gen[2].cnt_reg[2][0] 0CLR 6* gbtBank_Clk_gen[2].cnt_reg[2][1] 0CLR 6* gbtBank_Clk_gen[2].cnt_reg[2][2] 0CLR 6* gbtBank_Clk_gen[2].cnt_reg[2][3] 0CLR 6* gbtBank_Clk_gen[2].cnt_reg[2][4] 0CLR 6* gbtBank_Clk_gen[2].cnt_reg[2][5] 0CLR 6* gbtBank_Clk_gen[2].cnt_reg[2][6] 0CLR 6* gbtBank_Clk_gen[2].cnt_reg[2][7] 8CLR 6*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] 8CLR 6*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1] 8CLR 6*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2] 8CLR 6*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3] 8CLR 6*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4] 8CLR 6*(gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4668BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__37, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 8mgtRxReady_s_i_1__37 *I CLR 6*mgtRxReady_s_reg %CLR 6*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4678BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 8rst_in_meta_i_1__1 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4688BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. =rst_in_meta_i_1__3 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4698B LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].cnt_reg[3][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 78+gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__2 * ;CLR 8*+gbtBank_Clk_gen[3].RX_FRAMECLK_RDY_i_reg[3] 0CLR 6* gbtBank_Clk_gen[3].cnt_reg[3][0] 0CLR 6* gbtBank_Clk_gen[3].cnt_reg[3][1] 0CLR 6* gbtBank_Clk_gen[3].cnt_reg[3][2] 0CLR 6* gbtBank_Clk_gen[3].cnt_reg[3][3] 0CLR 6* gbtBank_Clk_gen[3].cnt_reg[3][4] 0CLR 6* gbtBank_Clk_gen[3].cnt_reg[3][5] 0CLR 6* gbtBank_Clk_gen[3].cnt_reg[3][6] 0CLR 6* gbtBank_Clk_gen[3].cnt_reg[3][7] 8CLR 6*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0] 8CLR 6*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1] 8CLR 6*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2] 8CLR 6*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3] 8CLR 6*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4] 8CLR 6*(gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4708BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__38, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 8mgtRxReady_s_i_1__38 *I CLR 6*mgtRxReady_s_reg %CLR 6*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4718BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 8rst_in_meta_i_1__1 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4728BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. =rst_in_meta_i_1__3 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4738B LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].cnt_reg[4][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 78+gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2__2 * ;CLR 8*+gbtBank_Clk_gen[4].RX_FRAMECLK_RDY_i_reg[4] 0CLR 6* gbtBank_Clk_gen[4].cnt_reg[4][0] 0CLR 6* gbtBank_Clk_gen[4].cnt_reg[4][1] 0CLR 6* gbtBank_Clk_gen[4].cnt_reg[4][2] 0CLR 6* gbtBank_Clk_gen[4].cnt_reg[4][3] 0CLR 6* gbtBank_Clk_gen[4].cnt_reg[4][4] 0CLR 6* gbtBank_Clk_gen[4].cnt_reg[4][5] 0CLR 6* gbtBank_Clk_gen[4].cnt_reg[4][6] 0CLR 6* gbtBank_Clk_gen[4].cnt_reg[4][7] 8CLR 6*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0] 8CLR 6*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1] 8CLR 6*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2] 8CLR 6*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3] 8CLR 6*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4] 8CLR 6*(gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4748BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__39, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 8mgtRxReady_s_i_1__39 *I CLR 6*mgtRxReady_s_reg %CLR 6*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4758BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. З8rst_in_meta_i_1__1 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4768BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. =rst_in_meta_i_1__3 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4778B LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].cnt_reg[5][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 78+gbtBank_Clk_gen[5].rx_clken_sr[5][5]_i_2__2 * ;CLR 8*+gbtBank_Clk_gen[5].RX_FRAMECLK_RDY_i_reg[5] 0CLR 6* gbtBank_Clk_gen[5].cnt_reg[5][0] 0CLR 6* gbtBank_Clk_gen[5].cnt_reg[5][1] 0CLR 6* gbtBank_Clk_gen[5].cnt_reg[5][2] 0CLR 6* gbtBank_Clk_gen[5].cnt_reg[5][3] 0CLR 6* gbtBank_Clk_gen[5].cnt_reg[5][4] 0CLR 6* gbtBank_Clk_gen[5].cnt_reg[5][5] 0CLR 6* gbtBank_Clk_gen[5].cnt_reg[5][6] 0CLR 6* gbtBank_Clk_gen[5].cnt_reg[5][7] 8CLR 6*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][0] 8CLR 6*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][1] 8CLR 6*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][2] 8CLR 6*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][3] 8CLR 6*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][4] 8CLR 6*(gbtBank_Clk_gen[5].rx_clken_sr_reg[5][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4788BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__40, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[5].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." ǚ8mgtRxReady_s_i_1__40 *I CLR ١6*mgtRxReady_s_reg %CLR ڡ6*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4798BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 8rst_in_meta_i_1__1 * PRE Ǧ=*rst_in_meta_reg PRE Ȧ=*rst_in_out_reg PRE ɦ=*rst_in_sync1_reg PRE ʦ=*rst_in_sync2_reg PRE ˦=*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4808BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Ц=rst_in_meta_i_1__3 * PRE Ѧ=*rst_in_meta_reg PRE Ҧ=*rst_in_out_reg PRE Ӧ=*rst_in_sync1_reg PRE Ԧ=*rst_in_sync2_reg PRE զ=*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4818B LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].cnt_reg[6][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 7؟8+gbtBank_Clk_gen[6].rx_clken_sr[6][5]_i_2__2 * ;CLR 8*+gbtBank_Clk_gen[6].RX_FRAMECLK_RDY_i_reg[6] 0CLR 6* gbtBank_Clk_gen[6].cnt_reg[6][0] 0CLR 6* gbtBank_Clk_gen[6].cnt_reg[6][1] 0CLR 6* gbtBank_Clk_gen[6].cnt_reg[6][2] 0CLR 6* gbtBank_Clk_gen[6].cnt_reg[6][3] 0CLR 6* gbtBank_Clk_gen[6].cnt_reg[6][4] 0CLR 6* gbtBank_Clk_gen[6].cnt_reg[6][5] 0CLR 6* gbtBank_Clk_gen[6].cnt_reg[6][6] 0CLR 6* gbtBank_Clk_gen[6].cnt_reg[6][7] 8CLR 6*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][0] 8CLR 6*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][1] 8CLR 6*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][2] 8CLR 6*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][3] 8CLR 6*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][4] 8CLR 6*(gbtBank_Clk_gen[6].rx_clken_sr_reg[6][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4828BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__41, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[6].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 8mgtRxReady_s_i_1__41 *I CLR 6*mgtRxReady_s_reg %CLR 6*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4838BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 8rst_in_meta_i_1__1 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4848BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. =rst_in_meta_i_1__3 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4858B LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].cnt_reg[7][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 78+gbtBank_Clk_gen[7].rx_clken_sr[7][5]_i_2__2 * ;CLR 8*+gbtBank_Clk_gen[7].RX_FRAMECLK_RDY_i_reg[7] 0CLR 6* gbtBank_Clk_gen[7].cnt_reg[7][0] 0CLR 6* gbtBank_Clk_gen[7].cnt_reg[7][1] 0CLR 6* gbtBank_Clk_gen[7].cnt_reg[7][2] 0CLR 6* gbtBank_Clk_gen[7].cnt_reg[7][3] 0CLR 6* gbtBank_Clk_gen[7].cnt_reg[7][4] 0CLR 6* gbtBank_Clk_gen[7].cnt_reg[7][5] 0CLR 6* gbtBank_Clk_gen[7].cnt_reg[7][6] 0CLR 6* gbtBank_Clk_gen[7].cnt_reg[7][7] 8CLR 6*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][0] 8CLR 6*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][1] 8CLR 6*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][2] 8CLR 6*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][3] 8CLR 6*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][4] 8CLR 6*(gbtBank_Clk_gen[7].rx_clken_sr_reg[7][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4868BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__42, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[7].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 8mgtRxReady_s_i_1__42 *I CLR ۢ6*mgtRxReady_s_reg %CLR ܢ6*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4878BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 8rst_in_meta_i_1__1 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4888BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. =rst_in_meta_i_1__3 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4898B LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].cnt_reg[8][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 78+gbtBank_Clk_gen[8].rx_clken_sr[8][5]_i_2__2 * ;CLR 8*+gbtBank_Clk_gen[8].RX_FRAMECLK_RDY_i_reg[8] 0CLR 6* gbtBank_Clk_gen[8].cnt_reg[8][0] 0CLR 6* gbtBank_Clk_gen[8].cnt_reg[8][1] 0CLR 6* gbtBank_Clk_gen[8].cnt_reg[8][2] 0CLR 6* gbtBank_Clk_gen[8].cnt_reg[8][3] 0CLR 6* gbtBank_Clk_gen[8].cnt_reg[8][4] 0CLR 6* gbtBank_Clk_gen[8].cnt_reg[8][5] 0CLR 6* gbtBank_Clk_gen[8].cnt_reg[8][6] 0CLR 6* gbtBank_Clk_gen[8].cnt_reg[8][7] 8CLR 6*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][0] 8CLR 6*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][1] 8CLR 6*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][2] 8CLR 6*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][3] 8CLR 6*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][4] 8CLR 6*(gbtBank_Clk_gen[8].rx_clken_sr_reg[8][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4908BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__43, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[8].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." 8mgtRxReady_s_i_1__43 *I CLR 6*mgtRxReady_s_reg %CLR 6*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4918BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. 8rst_in_meta_i_1__1 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4928BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_meta_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_out_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync1_reg/PRE, g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync2_reg/PRE g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst/reset_synchronizer_gtwiz_reset_rx_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. =rst_in_meta_i_1__3 * PRE =*rst_in_meta_reg PRE =*rst_in_out_reg PRE =*rst_in_sync1_reg PRE =*rst_in_sync2_reg PRE =*rst_in_sync3_reg/ Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4938B LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_tx_phase_aligner/cmp_tx_phase_aligner_fsm/gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][3]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][4]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][5]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][6]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].cnt_reg[9][7]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2]/CLR, g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3]/CLR g_gbt_bank[3].gbtbank/gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.9 78+gbtBank_Clk_gen[9].rx_clken_sr[9][5]_i_2__2 * ;CLR 8*+gbtBank_Clk_gen[9].RX_FRAMECLK_RDY_i_reg[9] 0CLR 6* gbtBank_Clk_gen[9].cnt_reg[9][0] 0CLR 6* gbtBank_Clk_gen[9].cnt_reg[9][1] 0CLR 6* gbtBank_Clk_gen[9].cnt_reg[9][2] 0CLR 6* gbtBank_Clk_gen[9].cnt_reg[9][3] 0CLR 6* gbtBank_Clk_gen[9].cnt_reg[9][4] 0CLR 6* gbtBank_Clk_gen[9].cnt_reg[9][5] 0CLR 6* gbtBank_Clk_gen[9].cnt_reg[9][6] 0CLR 6* gbtBank_Clk_gen[9].cnt_reg[9][7] 8CLR Ɯ6*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][0] 8CLR Ŝ6*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][1] 8CLR Ĝ6*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][2] 8CLR Ü6*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][3] 8CLR œ6*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][4] 8CLR 6*(gbtBank_Clk_gen[9].rx_clken_sr_reg[9][5] Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4948BLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/mgtRxReady_s_i_1__44, with 2 or more inputs, drives asynchronous preset/clear pin(s) g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR g_gbt_bank[3].gbtbank/gbtBank_rst_gen[9].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path." ߩ8mgtRxReady_s_i_1__44 *I CLR ϣ6*mgtRxReady_s_reg %CLR У6*mgtRxReady_sync_s_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4958BLUT cell i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync2_reg/PRE i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_any_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.< :Ɉ9.reset_synchronizer_gtwiz_reset_rx_any_inst_i_1 * PRE Ն9*rst_in_meta_reg PRE ن9*rst_in_out_reg PRE ֆ9*rst_in_sync1_reg PRE ׆9*rst_in_sync2_reg PRE ؆9*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4968BLUT cell i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_sync2_reg/PRE i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_sync2_reg/PRE i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.I Gʈ9;reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst_i_1 * PRE ݆9*rst_in_meta_reg PRE 9*rst_in_out_reg PRE ކ9*rst_in_sync1_reg PRE ߆9*rst_in_sync2_reg PRE 9*rst_in_sync3_reg Warning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4978B LUT cell i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync2_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync3_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_sync2_reg/PRE i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.J LUT cell i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync2_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_any_inst/rst_in_sync3_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_meta_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_out_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_sync1_reg/PRE, i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_sync2_reg/PRE i_tcds2_if/i_mgt_wrapper/i_reset_sm/reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst/rst_in_sync3_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.< :9.reset_synchronizer_gtwiz_reset_tx_any_inst_i_1 * PRE 9*rst_in_meta_reg PRE 9*rst_in_out_reg PRE 9*rst_in_sync1_reg PRE 9*rst_in_sync2_reg PRE 9*rst_in_sync3_reg PRE 9*rst_in_meta_reg PRE 9*rst_in_out_reg PRE 9*rst_in_sync1_reg PRE 9*rst_in_sync2_reg PRE 9*rst_in_sync3_regWarning"LUTAR-1*LUT drives async reset alert2 LUTAR-1#4988BLUT cell rst_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) timer_reg[0]/CLR, timer_reg[12]/CLR, timer_reg[14]/CLR, timer_reg[1]/CLR, timer_reg[20]/CLR, timer_reg[22]/CLR, timer_reg[23]/CLR, timer_reg[24]/CLR, timer_reg[25]/CLR, timer_reg[26]/CLR, timer_reg[27]/CLR, timer_reg[28]/CLR, timer_reg[29]/CLR, timer_reg[2]/CLR, timer_reg[30]/CLR (the first 15 of 34 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.JLUT cell rst_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) timer_reg[0]/CLR, timer_reg[12]/CLR, timer_reg[14]/CLR, timer_reg[1]/CLR, timer_reg[20]/CLR, timer_reg[22]/CLR, timer_reg[23]/CLR, timer_reg[24]/CLR, timer_reg[25]/CLR, timer_reg[26]/CLR, timer_reg[27]/CLR, timer_reg[28]/CLR, timer_reg[29]/CLR, timer_reg[2]/CLR, timer_reg[30]/CLR (the first 15 of 34 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. rst_i_2 * CLR +* timer_reg[0] CLR +* timer_reg[12] CLR +* timer_reg[14] CLR +* timer_reg[1] CLR +* timer_reg[20] CLR +* timer_reg[22] CLR +* timer_reg[23] CLR +* timer_reg[24] CLR +* timer_reg[25] CLR +* timer_reg[26] CLR +* timer_reg[27] CLR +* timer_reg[28] CLR +* timer_reg[29] CLR +* timer_reg[2] CLR +* timer_reg[30] CLR +* timer_reg[31] CLR +* timer_reg[4] CLR +* timer_reg[5] CLR +* timer_reg[6] CLR +* timer_reg[7] PRE ;* rst_dbl_reg PRE ;*rst_reg PRE +* timer_reg[10] PRE +* timer_reg[11] PRE +* timer_reg[13] PRE +* timer_reg[15] PRE +* timer_reg[16] PRE +* timer_reg[17] PRE +* timer_reg[18] PRE +* timer_reg[19] PRE +* timer_reg[21] PRE +* timer_reg[3] PRE +* timer_reg[8] PRE +* timer_reg[9]Warning"SYNTH-6**Timing of a RAM block might be sub-optimal2 SYNTH-6#18BThe timing for the instance ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.JThe timing for the instance ipb/udp_if/ipbus_rx_ram/ram2_reg_bram_1, implemented as a RAM block, might be sub-optimal as no output register was merged into the block. :ram2_reg_bram_1 *Warning"SYNTH-6**Timing of a RAM block might be sub-optimal2 SYNTH-6#28BThe timing for the instance ipb/udp_if/ipbus_tx_ram/ram_reg_bram_3, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.JThe timing for the instance ipb/udp_if/ipbus_tx_ram/ram_reg_bram_3, implemented as a RAM block, might be sub-optimal as no output register was merged into the block. :ram_reg_bram_3 *Warning"SYNTH-6**Timing of a RAM block might be sub-optimal2 SYNTH-6#38BThe timing for the instance ipb/udp_if/ipbus_tx_ram/ram_reg_bram_5, implemented as a RAM block, might be sub-optimal as no output register was merged into the block.JThe timing for the instance ipb/udp_if/ipbus_tx_ram/ram_reg_bram_5, implemented as a RAM block, might be sub-optimal as no output register was merged into the block. :ram_reg_bram_5 *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#18BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#28BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#38BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#48BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[0].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#58BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#68BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#78BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#88BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[1].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst * Warning"SYNTH-11*DSP output not registered2 SYNTH-11#98BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst * Warning"SYNTH-11*DSP output not registered2 SYNTH-11#108BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst * Warning"SYNTH-11*DSP output not registered2 SYNTH-11#118BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst * Warning"SYNTH-11*DSP output not registered2 SYNTH-11#128BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[2].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst * Warning"SYNTH-11*DSP output not registered2 SYNTH-11#138BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#148BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#158BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#168BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[3].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#178BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#188BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#198BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#208BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[4].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#218BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#228BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#238BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#248BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[5].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#258BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#268BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#278BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#288BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[6].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#298BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#308BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *Warning"SYNTH-11*DSP output not registered2 SYNTH-11#318BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst * Warning"SYNTH-11*DSP output not registered2 SYNTH-11#328BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[0].g_DSP_MUX_j[7].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *!Warning"SYNTH-11*DSP output not registered2 SYNTH-11#338BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *"Warning"SYNTH-11*DSP output not registered2 SYNTH-11#348BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *#Warning"SYNTH-11*DSP output not registered2 SYNTH-11#358BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *$Warning"SYNTH-11*DSP output not registered2 SYNTH-11#368BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[0].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *%Warning"SYNTH-11*DSP output not registered2 SYNTH-11#378BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *&Warning"SYNTH-11*DSP output not registered2 SYNTH-11#388BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[1].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *'Warning"SYNTH-11*DSP output not registered2 SYNTH-11#398BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *(Warning"SYNTH-11*DSP output not registered2 SYNTH-11#408BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *)Warning"SYNTH-11*DSP output not registered2 SYNTH-11#418BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst **Warning"SYNTH-11*DSP output not registered2 SYNTH-11#428BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[2].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *+Warning"SYNTH-11*DSP output not registered2 SYNTH-11#438BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *,Warning"SYNTH-11*DSP output not registered2 SYNTH-11#448BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *-Warning"SYNTH-11*DSP output not registered2 SYNTH-11#458BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *.Warning"SYNTH-11*DSP output not registered2 SYNTH-11#468BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[3].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst */Warning"SYNTH-11*DSP output not registered2 SYNTH-11#478BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *0Warning"SYNTH-11*DSP output not registered2 SYNTH-11#488BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *1Warning"SYNTH-11*DSP output not registered2 SYNTH-11#498BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *2Warning"SYNTH-11*DSP output not registered2 SYNTH-11#508BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[4].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *3Warning"SYNTH-11*DSP output not registered2 SYNTH-11#518BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *4Warning"SYNTH-11*DSP output not registered2 SYNTH-11#528BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *5Warning"SYNTH-11*DSP output not registered2 SYNTH-11#538BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[5].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *6Warning"SYNTH-11*DSP output not registered2 SYNTH-11#548BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *7Warning"SYNTH-11*DSP output not registered2 SYNTH-11#558BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *8Warning"SYNTH-11*DSP output not registered2 SYNTH-11#568BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *9Warning"SYNTH-11*DSP output not registered2 SYNTH-11#578BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[6].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *:Warning"SYNTH-11*DSP output not registered2 SYNTH-11#588BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *;Warning"SYNTH-11*DSP output not registered2 SYNTH-11#598BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *<Warning"SYNTH-11*DSP output not registered2 SYNTH-11#608BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *=Warning"SYNTH-11*DSP output not registered2 SYNTH-11#618BDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_cntr_k[1].g_DSP_MUX_j[7].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *>Warning"SYNTH-11*DSP output not registered2 SYNTH-11#628BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *?Warning"SYNTH-11*DSP output not registered2 SYNTH-11#638BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *@Warning"SYNTH-11*DSP output not registered2 SYNTH-11#648BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[0].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *~AWarning"SYNTH-11*DSP output not registered2 SYNTH-11#658BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[0].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[0].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *BWarning"SYNTH-11*DSP output not registered2 SYNTH-11#668BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *CWarning"SYNTH-11*DSP output not registered2 SYNTH-11#678BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *DWarning"SYNTH-11*DSP output not registered2 SYNTH-11#688BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[1].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *~EWarning"SYNTH-11*DSP output not registered2 SYNTH-11#698BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[1].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[1].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *FWarning"SYNTH-11*DSP output not registered2 SYNTH-11#708BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *GWarning"SYNTH-11*DSP output not registered2 SYNTH-11#718BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *HWarning"SYNTH-11*DSP output not registered2 SYNTH-11#728BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[2].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *~IWarning"SYNTH-11*DSP output not registered2 SYNTH-11#738BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[2].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[2].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *JWarning"SYNTH-11*DSP output not registered2 SYNTH-11#748BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *KWarning"SYNTH-11*DSP output not registered2 SYNTH-11#758BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *LWarning"SYNTH-11*DSP output not registered2 SYNTH-11#768BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[3].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *~MWarning"SYNTH-11*DSP output not registered2 SYNTH-11#778BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[3].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[3].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *NWarning"SYNTH-11*DSP output not registered2 SYNTH-11#788BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *OWarning"SYNTH-11*DSP output not registered2 SYNTH-11#798BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *PWarning"SYNTH-11*DSP output not registered2 SYNTH-11#808BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[4].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *~QWarning"SYNTH-11*DSP output not registered2 SYNTH-11#818BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[4].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[4].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *RWarning"SYNTH-11*DSP output not registered2 SYNTH-11#828BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *SWarning"SYNTH-11*DSP output not registered2 SYNTH-11#838BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *TWarning"SYNTH-11*DSP output not registered2 SYNTH-11#848BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[5].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *~UWarning"SYNTH-11*DSP output not registered2 SYNTH-11#858BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[5].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[5].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *VWarning"SYNTH-11*DSP output not registered2 SYNTH-11#868BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *WWarning"SYNTH-11*DSP output not registered2 SYNTH-11#878BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *XWarning"SYNTH-11*DSP output not registered2 SYNTH-11#888BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[6].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *~YWarning"SYNTH-11*DSP output not registered2 SYNTH-11#898BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[6].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[6].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *ZWarning"SYNTH-11*DSP output not registered2 SYNTH-11#908BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[1].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *[Warning"SYNTH-11*DSP output not registered2 SYNTH-11#918BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[2].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *\Warning"SYNTH-11*DSP output not registered2 SYNTH-11#928BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[7].g_DSP_MUX_i[3].i_DSP_MUX_C/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *~]Warning"SYNTH-11*DSP output not registered2 SYNTH-11#938BDSP instance stat_regs_inst/g_DSP_MUX_rate_k[7].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_MUX_rate_k[7].i_DSP_MUX_C_b/DSP48E2_inst is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst *y^Warning"SYNTH-11*DSP output not registered2 SYNTH-11#948BDSP instance stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}_Warning"SYNTH-11*DSP output not registered2 SYNTH-11#958BDSP instance stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}`Warning"SYNTH-11*DSP output not registered2 SYNTH-11#968BDSP instance stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}aWarning"SYNTH-11*DSP output not registered2 SYNTH-11#978BDSP instance stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}bWarning"SYNTH-11*DSP output not registered2 SYNTH-11#988BDSP instance stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}cWarning"SYNTH-11*DSP output not registered2 SYNTH-11#998BDSP instance stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~dWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1008BDSP instance stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~eWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1018BDSP instance stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~fWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1028BDSP instance stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~gWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1038BDSP instance stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~hWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1048BDSP instance stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *|iWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1058BDSP instance stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~jWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1068BDSP instance stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~kWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1078BDSP instance stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~lWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1088BDSP instance stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~mWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1098BDSP instance stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~nWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1108BDSP instance stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~oWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1118BDSP instance stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~pWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1128BDSP instance stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~qWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1138BDSP instance stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~rWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1148BDSP instance stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~sWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1158BDSP instance stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *|tWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1168BDSP instance stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~uWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1178BDSP instance stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~vWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1188BDSP instance stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~wWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1198BDSP instance stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~xWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1208BDSP instance stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~yWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1218BDSP instance stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~zWarning"SYNTH-11*DSP output not registered2 SYNTH-11#1228BDSP instance stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~{Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1238BDSP instance stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *~|Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1248BDSP instance stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *|}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1258BDSP instance stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *|~Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1268BDSP instance stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *|Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1278BDSP instance stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1288BDSP instance stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1298BDSP instance stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1308BDSP instance stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1318BDSP instance stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1328BDSP instance stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *{Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1338BDSP instance stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1348BDSP instance stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1358BDSP instance stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1368BDSP instance stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1378BDSP instance stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1388BDSP instance stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1398BDSP instance stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1408BDSP instance stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1418BDSP instance stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1428BDSP instance stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1438BDSP instance stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *{Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1448BDSP instance stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1458BDSP instance stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1468BDSP instance stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1478BDSP instance stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1488BDSP instance stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1498BDSP instance stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1508BDSP instance stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1518BDSP instance stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1528BDSP instance stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1538BDSP instance stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1548BDSP instance stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *{Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1558BDSP instance stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. : DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1568BDSP instance stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1578BDSP instance stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ̀; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1588BDSP instance stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1598BDSP instance stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1608BDSP instance stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1618BDSP instance stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1628BDSP instance stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1638BDSP instance stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1648BDSP instance stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ܃; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1658BDSP instance stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *{Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1668BDSP instance stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ΄; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1678BDSP instance stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1688BDSP instance stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1698BDSP instance stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1708BDSP instance stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1718BDSP instance stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1728BDSP instance stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1738BDSP instance stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ݇; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1748BDSP instance stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1758BDSP instance stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ψ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1768BDSP instance stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *{Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1778BDSP instance stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1788BDSP instance stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1798BDSP instance stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1808BDSP instance stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1818BDSP instance stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1828BDSP instance stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ދ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1838BDSP instance stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1848BDSP instance stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Ќ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1858BDSP instance stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1868BDSP instance stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1878BDSP instance stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *{Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1888BDSP instance stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1898BDSP instance stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1908BDSP instance stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1918BDSP instance stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ߏ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1928BDSP instance stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1938BDSP instance stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ѐ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1948BDSP instance stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1958BDSP instance stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Ñ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1968BDSP instance stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1978BDSP instance stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1988BDSP instance stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *{Warning"SYNTH-11*DSP output not registered2 SYNTH-11#1998BDSP instance stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2008BDSP instance stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2018BDSP instance stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2028BDSP instance stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Ҕ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2038BDSP instance stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2048BDSP instance stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ĕ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2058BDSP instance stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2068BDSP instance stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2078BDSP instance stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2088BDSP instance stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2098BDSP instance stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *{Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2108BDSP instance stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2118BDSP instance stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Ә; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2128BDSP instance stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2138BDSP instance stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ř; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2148BDSP instance stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2158BDSP instance stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2168BDSP instance stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2178BDSP instance stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2188BDSP instance stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2198BDSP instance stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *}Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2208BDSP instance stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. Ԝ; DSP48E2_inst2 *{Warning"SYNTH-11*DSP output not registered2 SYNTH-11#2218BDSP instance stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst2 is not fully pipelined on the output side. MREG/PREG are not used. ; DSP48E2_inst2 *~Warning"SYNTH-12*DSP input not registered2 SYNTH-12#18BDSP instance g_clock_rate_din[0].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[0].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *~Warning"SYNTH-12*DSP input not registered2 SYNTH-12#28BDSP instance g_clock_rate_din[0].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[0].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *~Warning"SYNTH-12*DSP input not registered2 SYNTH-12#38BDSP instance g_clock_rate_din[0].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[0].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *vWarning"SYNTH-12*DSP input not registered2 SYNTH-12#48BDSP instance g_clock_rate_din[0].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[0].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#58BDSP instance g_clock_rate_din[10].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[10].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#68BDSP instance g_clock_rate_din[10].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[10].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#78BDSP instance g_clock_rate_din[10].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[10].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *xWarning"SYNTH-12*DSP input not registered2 SYNTH-12#88BDSP instance g_clock_rate_din[10].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[10].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst * Warning"SYNTH-12*DSP input not registered2 SYNTH-12#98BDSP instance g_clock_rate_din[11].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[11].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst * Warning"SYNTH-12*DSP input not registered2 SYNTH-12#108BDSP instance g_clock_rate_din[11].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[11].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst * Warning"SYNTH-12*DSP input not registered2 SYNTH-12#118BDSP instance g_clock_rate_din[11].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[11].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *y Warning"SYNTH-12*DSP input not registered2 SYNTH-12#128BDSP instance g_clock_rate_din[11].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[11].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst * Warning"SYNTH-12*DSP input not registered2 SYNTH-12#138BDSP instance g_clock_rate_din[12].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[12].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#148BDSP instance g_clock_rate_din[12].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[12].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#158BDSP instance g_clock_rate_din[12].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[12].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *yWarning"SYNTH-12*DSP input not registered2 SYNTH-12#168BDSP instance g_clock_rate_din[12].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[12].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#178BDSP instance g_clock_rate_din[13].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[13].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#188BDSP instance g_clock_rate_din[13].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[13].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#198BDSP instance g_clock_rate_din[13].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[13].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *yWarning"SYNTH-12*DSP input not registered2 SYNTH-12#208BDSP instance g_clock_rate_din[13].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[13].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#218BDSP instance g_clock_rate_din[14].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[14].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#228BDSP instance g_clock_rate_din[14].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[14].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#238BDSP instance g_clock_rate_din[14].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[14].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *yWarning"SYNTH-12*DSP input not registered2 SYNTH-12#248BDSP instance g_clock_rate_din[14].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[14].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#258BDSP instance g_clock_rate_din[15].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[15].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#268BDSP instance g_clock_rate_din[15].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[15].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#278BDSP instance g_clock_rate_din[15].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[15].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *yWarning"SYNTH-12*DSP input not registered2 SYNTH-12#288BDSP instance g_clock_rate_din[15].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[15].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#298BDSP instance g_clock_rate_din[16].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[16].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#308BDSP instance g_clock_rate_din[16].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[16].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#318BDSP instance g_clock_rate_din[16].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[16].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *y Warning"SYNTH-12*DSP input not registered2 SYNTH-12#328BDSP instance g_clock_rate_din[16].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[16].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *!Warning"SYNTH-12*DSP input not registered2 SYNTH-12#338BDSP instance g_clock_rate_din[17].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[17].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *"Warning"SYNTH-12*DSP input not registered2 SYNTH-12#348BDSP instance g_clock_rate_din[17].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[17].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *#Warning"SYNTH-12*DSP input not registered2 SYNTH-12#358BDSP instance g_clock_rate_din[17].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[17].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *y$Warning"SYNTH-12*DSP input not registered2 SYNTH-12#368BDSP instance g_clock_rate_din[17].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[17].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *%Warning"SYNTH-12*DSP input not registered2 SYNTH-12#378BDSP instance g_clock_rate_din[18].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[18].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *&Warning"SYNTH-12*DSP input not registered2 SYNTH-12#388BDSP instance g_clock_rate_din[18].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[18].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *'Warning"SYNTH-12*DSP input not registered2 SYNTH-12#398BDSP instance g_clock_rate_din[18].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[18].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *y(Warning"SYNTH-12*DSP input not registered2 SYNTH-12#408BDSP instance g_clock_rate_din[18].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[18].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *)Warning"SYNTH-12*DSP input not registered2 SYNTH-12#418BDSP instance g_clock_rate_din[19].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[19].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst **Warning"SYNTH-12*DSP input not registered2 SYNTH-12#428BDSP instance g_clock_rate_din[19].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[19].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *+Warning"SYNTH-12*DSP input not registered2 SYNTH-12#438BDSP instance g_clock_rate_din[19].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[19].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *y,Warning"SYNTH-12*DSP input not registered2 SYNTH-12#448BDSP instance g_clock_rate_din[19].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[19].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *-Warning"SYNTH-12*DSP input not registered2 SYNTH-12#458BDSP instance g_clock_rate_din[1].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[1].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *.Warning"SYNTH-12*DSP input not registered2 SYNTH-12#468BDSP instance g_clock_rate_din[1].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[1].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst */Warning"SYNTH-12*DSP input not registered2 SYNTH-12#478BDSP instance g_clock_rate_din[1].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[1].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *w0Warning"SYNTH-12*DSP input not registered2 SYNTH-12#488BDSP instance g_clock_rate_din[1].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[1].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *1Warning"SYNTH-12*DSP input not registered2 SYNTH-12#498BDSP instance g_clock_rate_din[20].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[20].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *2Warning"SYNTH-12*DSP input not registered2 SYNTH-12#508BDSP instance g_clock_rate_din[20].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[20].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *3Warning"SYNTH-12*DSP input not registered2 SYNTH-12#518BDSP instance g_clock_rate_din[20].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[20].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *y4Warning"SYNTH-12*DSP input not registered2 SYNTH-12#528BDSP instance g_clock_rate_din[20].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[20].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *5Warning"SYNTH-12*DSP input not registered2 SYNTH-12#538BDSP instance g_clock_rate_din[21].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[21].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *6Warning"SYNTH-12*DSP input not registered2 SYNTH-12#548BDSP instance g_clock_rate_din[21].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[21].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *7Warning"SYNTH-12*DSP input not registered2 SYNTH-12#558BDSP instance g_clock_rate_din[21].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[21].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *y8Warning"SYNTH-12*DSP input not registered2 SYNTH-12#568BDSP instance g_clock_rate_din[21].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[21].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *9Warning"SYNTH-12*DSP input not registered2 SYNTH-12#578BDSP instance g_clock_rate_din[22].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[22].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *:Warning"SYNTH-12*DSP input not registered2 SYNTH-12#588BDSP instance g_clock_rate_din[22].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[22].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *;Warning"SYNTH-12*DSP input not registered2 SYNTH-12#598BDSP instance g_clock_rate_din[22].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[22].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. . DSP48E2_inst *y<Warning"SYNTH-12*DSP input not registered2 SYNTH-12#608BDSP instance g_clock_rate_din[22].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[22].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *=Warning"SYNTH-12*DSP input not registered2 SYNTH-12#618BDSP instance g_clock_rate_din[23].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[23].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *>Warning"SYNTH-12*DSP input not registered2 SYNTH-12#628BDSP instance g_clock_rate_din[23].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[23].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ہ/ DSP48E2_inst *?Warning"SYNTH-12*DSP input not registered2 SYNTH-12#638BDSP instance g_clock_rate_din[23].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[23].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *y@Warning"SYNTH-12*DSP input not registered2 SYNTH-12#648BDSP instance g_clock_rate_din[23].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[23].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *AWarning"SYNTH-12*DSP input not registered2 SYNTH-12#658BDSP instance g_clock_rate_din[24].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[24].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *BWarning"SYNTH-12*DSP input not registered2 SYNTH-12#668BDSP instance g_clock_rate_din[24].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[24].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *CWarning"SYNTH-12*DSP input not registered2 SYNTH-12#678BDSP instance g_clock_rate_din[24].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[24].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Dž/ DSP48E2_inst *yDWarning"SYNTH-12*DSP input not registered2 SYNTH-12#688BDSP instance g_clock_rate_din[24].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[24].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Æ/ DSP48E2_inst *EWarning"SYNTH-12*DSP input not registered2 SYNTH-12#698BDSP instance g_clock_rate_din[25].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[25].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *FWarning"SYNTH-12*DSP input not registered2 SYNTH-12#708BDSP instance g_clock_rate_din[25].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[25].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *GWarning"SYNTH-12*DSP input not registered2 SYNTH-12#718BDSP instance g_clock_rate_din[25].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[25].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Ԉ/ DSP48E2_inst *yHWarning"SYNTH-12*DSP input not registered2 SYNTH-12#728BDSP instance g_clock_rate_din[25].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[25].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Љ/ DSP48E2_inst *IWarning"SYNTH-12*DSP input not registered2 SYNTH-12#738BDSP instance g_clock_rate_din[26].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[26].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Ŋ/ DSP48E2_inst *JWarning"SYNTH-12*DSP input not registered2 SYNTH-12#748BDSP instance g_clock_rate_din[26].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[26].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *KWarning"SYNTH-12*DSP input not registered2 SYNTH-12#758BDSP instance g_clock_rate_din[26].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[26].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *yLWarning"SYNTH-12*DSP input not registered2 SYNTH-12#768BDSP instance g_clock_rate_din[26].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[26].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ݌/ DSP48E2_inst *MWarning"SYNTH-12*DSP input not registered2 SYNTH-12#778BDSP instance g_clock_rate_din[27].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[27].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ҍ/ DSP48E2_inst *NWarning"SYNTH-12*DSP input not registered2 SYNTH-12#788BDSP instance g_clock_rate_din[27].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[27].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *OWarning"SYNTH-12*DSP input not registered2 SYNTH-12#798BDSP instance g_clock_rate_din[27].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[27].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *yPWarning"SYNTH-12*DSP input not registered2 SYNTH-12#808BDSP instance g_clock_rate_din[27].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[27].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *QWarning"SYNTH-12*DSP input not registered2 SYNTH-12#818BDSP instance g_clock_rate_din[28].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[28].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ߐ/ DSP48E2_inst *RWarning"SYNTH-12*DSP input not registered2 SYNTH-12#828BDSP instance g_clock_rate_din[28].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[28].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *SWarning"SYNTH-12*DSP input not registered2 SYNTH-12#838BDSP instance g_clock_rate_din[28].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[28].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *yTWarning"SYNTH-12*DSP input not registered2 SYNTH-12#848BDSP instance g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[28].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *UWarning"SYNTH-12*DSP input not registered2 SYNTH-12#858BDSP instance g_clock_rate_din[29].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[29].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *VWarning"SYNTH-12*DSP input not registered2 SYNTH-12#868BDSP instance g_clock_rate_din[29].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[29].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *WWarning"SYNTH-12*DSP input not registered2 SYNTH-12#878BDSP instance g_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[29].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *yXWarning"SYNTH-12*DSP input not registered2 SYNTH-12#888BDSP instance g_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[29].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *YWarning"SYNTH-12*DSP input not registered2 SYNTH-12#898BDSP instance g_clock_rate_din[2].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[2].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *ZWarning"SYNTH-12*DSP input not registered2 SYNTH-12#908BDSP instance g_clock_rate_din[2].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[2].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *[Warning"SYNTH-12*DSP input not registered2 SYNTH-12#918BDSP instance g_clock_rate_din[2].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[2].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *w\Warning"SYNTH-12*DSP input not registered2 SYNTH-12#928BDSP instance g_clock_rate_din[2].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[2].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *]Warning"SYNTH-12*DSP input not registered2 SYNTH-12#938BDSP instance g_clock_rate_din[30].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[30].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *^Warning"SYNTH-12*DSP input not registered2 SYNTH-12#948BDSP instance g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[30].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Ú/ DSP48E2_inst *_Warning"SYNTH-12*DSP input not registered2 SYNTH-12#958BDSP instance g_clock_rate_din[30].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[30].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *y`Warning"SYNTH-12*DSP input not registered2 SYNTH-12#968BDSP instance g_clock_rate_din[30].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[30].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *aWarning"SYNTH-12*DSP input not registered2 SYNTH-12#978BDSP instance g_clock_rate_din[31].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[31].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *bWarning"SYNTH-12*DSP input not registered2 SYNTH-12#988BDSP instance g_clock_rate_din[31].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[31].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Н/ DSP48E2_inst *cWarning"SYNTH-12*DSP input not registered2 SYNTH-12#998BDSP instance g_clock_rate_din[31].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[31].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *zdWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1008BDSP instance g_clock_rate_din[31].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[31].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *eWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1018BDSP instance g_clock_rate_din[32].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[32].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *fWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1028BDSP instance g_clock_rate_din[32].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[32].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ݠ/ DSP48E2_inst *gWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1038BDSP instance g_clock_rate_din[32].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[32].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *zhWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1048BDSP instance g_clock_rate_din[32].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[32].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *iWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1058BDSP instance g_clock_rate_din[33].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[33].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *jWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1068BDSP instance g_clock_rate_din[33].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[33].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *kWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1078BDSP instance g_clock_rate_din[33].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[33].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ɤ/ DSP48E2_inst *zlWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1088BDSP instance g_clock_rate_din[33].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[33].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ť/ DSP48E2_inst *mWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1098BDSP instance g_clock_rate_din[34].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[34].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *nWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1108BDSP instance g_clock_rate_din[34].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[34].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *oWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1118BDSP instance g_clock_rate_din[34].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[34].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ֧/ DSP48E2_inst *zpWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1128BDSP instance g_clock_rate_din[34].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[34].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Ҩ/ DSP48E2_inst *qWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1138BDSP instance g_clock_rate_din[35].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[35].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ǩ/ DSP48E2_inst *rWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1148BDSP instance g_clock_rate_din[35].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[35].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *sWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1158BDSP instance g_clock_rate_din[35].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[35].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *ztWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1168BDSP instance g_clock_rate_din[35].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[35].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ߫/ DSP48E2_inst *uWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1178BDSP instance g_clock_rate_din[36].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[36].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Ԭ/ DSP48E2_inst *vWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1188BDSP instance g_clock_rate_din[36].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[36].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *wWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1198BDSP instance g_clock_rate_din[36].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[36].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *zxWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1208BDSP instance g_clock_rate_din[36].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[36].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *yWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1218BDSP instance g_clock_rate_din[37].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[37].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *zWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1228BDSP instance g_clock_rate_din[37].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[37].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *{Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1238BDSP instance g_clock_rate_din[37].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[37].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *z|Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1248BDSP instance g_clock_rate_din[37].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[37].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *}Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1258BDSP instance g_clock_rate_din[38].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[38].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *~Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1268BDSP instance g_clock_rate_din[38].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[38].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1278BDSP instance g_clock_rate_din[38].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[38].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *{Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1288BDSP instance g_clock_rate_din[38].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[38].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1298BDSP instance g_clock_rate_din[39].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[39].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1308BDSP instance g_clock_rate_din[39].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[39].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1318BDSP instance g_clock_rate_din[39].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[39].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *{Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1328BDSP instance g_clock_rate_din[39].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[39].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1338BDSP instance g_clock_rate_din[3].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[3].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1348BDSP instance g_clock_rate_din[3].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[3].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Ź/ DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1358BDSP instance g_clock_rate_din[3].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[3].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *yWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1368BDSP instance g_clock_rate_din[3].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[3].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1378BDSP instance g_clock_rate_din[40].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[40].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1388BDSP instance g_clock_rate_din[40].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[40].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Ҽ/ DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1398BDSP instance g_clock_rate_din[40].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[40].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *{Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1408BDSP instance g_clock_rate_din[40].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[40].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1418BDSP instance g_clock_rate_din[41].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[41].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1428BDSP instance g_clock_rate_din[41].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[41].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ߿/ DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1438BDSP instance g_clock_rate_din[41].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[41].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *{Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1448BDSP instance g_clock_rate_din[41].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[41].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1458BDSP instance g_clock_rate_din[42].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[42].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1468BDSP instance g_clock_rate_din[42].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[42].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1478BDSP instance g_clock_rate_din[42].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[42].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *{Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1488BDSP instance g_clock_rate_din[42].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[42].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1498BDSP instance g_clock_rate_din[43].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[43].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1508BDSP instance g_clock_rate_din[43].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[43].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1518BDSP instance g_clock_rate_din[43].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[43].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *{Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1528BDSP instance g_clock_rate_din[43].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[43].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1538BDSP instance g_clock_rate_din[44].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[44].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1548BDSP instance g_clock_rate_din[44].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[44].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1558BDSP instance g_clock_rate_din[44].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[44].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *{Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1568BDSP instance g_clock_rate_din[44].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[44].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1578BDSP instance g_clock_rate_din[45].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[45].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1588BDSP instance g_clock_rate_din[45].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[45].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1598BDSP instance g_clock_rate_din[45].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[45].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *{Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1608BDSP instance g_clock_rate_din[45].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[45].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1618BDSP instance g_clock_rate_din[46].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[46].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1628BDSP instance g_clock_rate_din[46].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[46].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1638BDSP instance g_clock_rate_din[46].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[46].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *{Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1648BDSP instance g_clock_rate_din[46].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[46].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1658BDSP instance g_clock_rate_din[47].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[47].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1668BDSP instance g_clock_rate_din[47].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[47].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1678BDSP instance g_clock_rate_din[47].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[47].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *{Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1688BDSP instance g_clock_rate_din[47].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[47].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1698BDSP instance g_clock_rate_din[4].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[4].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1708BDSP instance g_clock_rate_din[4].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[4].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1718BDSP instance g_clock_rate_din[4].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[4].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *yWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1728BDSP instance g_clock_rate_din[4].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[4].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1738BDSP instance g_clock_rate_din[5].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[5].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1748BDSP instance g_clock_rate_din[5].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[5].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1758BDSP instance g_clock_rate_din[5].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[5].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *yWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1768BDSP instance g_clock_rate_din[5].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[5].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1778BDSP instance g_clock_rate_din[6].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[6].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1788BDSP instance g_clock_rate_din[6].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[6].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1798BDSP instance g_clock_rate_din[6].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[6].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *yWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1808BDSP instance g_clock_rate_din[6].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[6].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1818BDSP instance g_clock_rate_din[7].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[7].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1828BDSP instance g_clock_rate_din[7].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[7].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1838BDSP instance g_clock_rate_din[7].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[7].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *yWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1848BDSP instance g_clock_rate_din[7].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[7].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1858BDSP instance g_clock_rate_din[8].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[8].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1868BDSP instance g_clock_rate_din[8].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[8].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1878BDSP instance g_clock_rate_din[8].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[8].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *yWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1888BDSP instance g_clock_rate_din[8].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[8].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1898BDSP instance g_clock_rate_din[9].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[9].i_rate_ngccm_status0/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1908BDSP instance g_clock_rate_din[9].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[9].i_rate_ngccm_status1/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1918BDSP instance g_clock_rate_din[9].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[9].i_rate_ngccm_status2/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *yWarning"SYNTH-12*DSP input not registered2 SYNTH-12#1928BDSP instance g_clock_rate_din[9].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance g_clock_rate_din[9].i_rate_test_comm/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. / DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1938BDSP instance stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[0].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1948BDSP instance stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[100].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1958BDSP instance stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[101].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1968BDSP instance stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[102].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1978BDSP instance stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[103].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1988BDSP instance stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[104].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#1998BDSP instance stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[105].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2008BDSP instance stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[106].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2018BDSP instance stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[107].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2028BDSP instance stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[108].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2038BDSP instance stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[109].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2048BDSP instance stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[10].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2058BDSP instance stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[110].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2068BDSP instance stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[111].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2078BDSP instance stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[112].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2088BDSP instance stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[113].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2098BDSP instance stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[114].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2108BDSP instance stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[115].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2118BDSP instance stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[116].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2128BDSP instance stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[117].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2138BDSP instance stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[118].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2148BDSP instance stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[119].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2158BDSP instance stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[11].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2168BDSP instance stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[120].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2178BDSP instance stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[121].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2188BDSP instance stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[122].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2198BDSP instance stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[123].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2208BDSP instance stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[124].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2218BDSP instance stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[125].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2228BDSP instance stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[126].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2238BDSP instance stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[127].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2248BDSP instance stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[12].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2258BDSP instance stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[13].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2268BDSP instance stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[14].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2278BDSP instance stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[15].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2288BDSP instance stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[16].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2298BDSP instance stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[17].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2308BDSP instance stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[18].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2318BDSP instance stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[19].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2328BDSP instance stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[1].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2338BDSP instance stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[20].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2348BDSP instance stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[21].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2358BDSP instance stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[22].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2368BDSP instance stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[23].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2378BDSP instance stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[24].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2388BDSP instance stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[25].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2398BDSP instance stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[26].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2408BDSP instance stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[27].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2418BDSP instance stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[28].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2428BDSP instance stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[29].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2438BDSP instance stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[2].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2448BDSP instance stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[30].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2458BDSP instance stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[31].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2468BDSP instance stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[32].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2478BDSP instance stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[33].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2488BDSP instance stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[34].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2498BDSP instance stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[35].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2508BDSP instance stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[36].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2518BDSP instance stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[37].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2528BDSP instance stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[38].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2538BDSP instance stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[39].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2548BDSP instance stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[3].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2558BDSP instance stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[40].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. : DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2568BDSP instance stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[41].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2578BDSP instance stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[42].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ΀; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2588BDSP instance stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[43].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2598BDSP instance stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[44].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2608BDSP instance stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[45].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2618BDSP instance stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[46].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2628BDSP instance stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[47].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2638BDSP instance stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[48].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2648BDSP instance stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[49].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ݃; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2658BDSP instance stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[4].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2668BDSP instance stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[50].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. τ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2678BDSP instance stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[51].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2688BDSP instance stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[52].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2698BDSP instance stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[53].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2708BDSP instance stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[54].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2718BDSP instance stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[55].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2728BDSP instance stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[56].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2738BDSP instance stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[57].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. އ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2748BDSP instance stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[58].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2758BDSP instance stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[59].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Ј; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2768BDSP instance stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[5].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2778BDSP instance stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[60].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ‰; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2788BDSP instance stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[61].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2798BDSP instance stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[62].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2808BDSP instance stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[63].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2818BDSP instance stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[64].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2828BDSP instance stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[65].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ߋ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2838BDSP instance stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[66].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2848BDSP instance stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[67].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ь; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2858BDSP instance stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[68].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2868BDSP instance stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[69].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Í; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2878BDSP instance stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[6].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2888BDSP instance stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[70].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2898BDSP instance stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[71].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2908BDSP instance stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[72].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2918BDSP instance stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[73].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2928BDSP instance stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[74].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2938BDSP instance stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[75].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Ґ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2948BDSP instance stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[76].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2958BDSP instance stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[77].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. đ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2968BDSP instance stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[78].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2978BDSP instance stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[79].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2988BDSP instance stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[7].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#2998BDSP instance stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[80].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3008BDSP instance stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[81].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3018BDSP instance stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[82].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3028BDSP instance stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[83].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Ӕ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3038BDSP instance stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[84].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3048BDSP instance stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[85].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ŕ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3058BDSP instance stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[86].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3068BDSP instance stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[87].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3078BDSP instance stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[88].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3088BDSP instance stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[89].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3098BDSP instance stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[8].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3108BDSP instance stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[90].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3118BDSP instance stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[91].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Ԙ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3128BDSP instance stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[92].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3138BDSP instance stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[93].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ƙ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3148BDSP instance stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[94].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3158BDSP instance stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[95].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3168BDSP instance stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[96].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3178BDSP instance stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[97].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3188BDSP instance stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[98].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3198BDSP instance stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[99].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3208BDSP instance stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_cntr[9].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ՜; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3218BDSP instance stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[0].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3228BDSP instance stat_regs_inst/g_DSP_rate[10].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[10].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Ɲ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3238BDSP instance stat_regs_inst/g_DSP_rate[11].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[11].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3248BDSP instance stat_regs_inst/g_DSP_rate[12].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[12].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3258BDSP instance stat_regs_inst/g_DSP_rate[13].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[13].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3268BDSP instance stat_regs_inst/g_DSP_rate[14].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[14].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ֞; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3278BDSP instance stat_regs_inst/g_DSP_rate[15].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[15].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3288BDSP instance stat_regs_inst/g_DSP_rate[16].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[16].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3298BDSP instance stat_regs_inst/g_DSP_rate[17].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[17].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Ÿ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3308BDSP instance stat_regs_inst/g_DSP_rate[18].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[18].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3318BDSP instance stat_regs_inst/g_DSP_rate[19].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[19].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3328BDSP instance stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[1].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3338BDSP instance stat_regs_inst/g_DSP_rate[20].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[20].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Ҡ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3348BDSP instance stat_regs_inst/g_DSP_rate[21].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[21].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3358BDSP instance stat_regs_inst/g_DSP_rate[22].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[22].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3368BDSP instance stat_regs_inst/g_DSP_rate[23].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[23].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3378BDSP instance stat_regs_inst/g_DSP_rate[24].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[24].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3388BDSP instance stat_regs_inst/g_DSP_rate[25].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[25].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3398BDSP instance stat_regs_inst/g_DSP_rate[26].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[26].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3408BDSP instance stat_regs_inst/g_DSP_rate[27].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[27].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ΢; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3418BDSP instance stat_regs_inst/g_DSP_rate[28].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[28].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3428BDSP instance stat_regs_inst/g_DSP_rate[29].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[29].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3438BDSP instance stat_regs_inst/g_DSP_rate[2].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[2].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3448BDSP instance stat_regs_inst/g_DSP_rate[30].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[30].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ޣ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3458BDSP instance stat_regs_inst/g_DSP_rate[31].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[31].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3468BDSP instance stat_regs_inst/g_DSP_rate[32].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[32].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3478BDSP instance stat_regs_inst/g_DSP_rate[33].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[33].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ʤ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3488BDSP instance stat_regs_inst/g_DSP_rate[34].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[34].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3498BDSP instance stat_regs_inst/g_DSP_rate[35].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[35].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3508BDSP instance stat_regs_inst/g_DSP_rate[36].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[36].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3518BDSP instance stat_regs_inst/g_DSP_rate[37].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[37].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ڥ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3528BDSP instance stat_regs_inst/g_DSP_rate[38].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[38].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3538BDSP instance stat_regs_inst/g_DSP_rate[39].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[39].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3548BDSP instance stat_regs_inst/g_DSP_rate[3].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[3].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Ʀ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3558BDSP instance stat_regs_inst/g_DSP_rate[40].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[40].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3568BDSP instance stat_regs_inst/g_DSP_rate[41].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[41].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3578BDSP instance stat_regs_inst/g_DSP_rate[42].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[42].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3588BDSP instance stat_regs_inst/g_DSP_rate[43].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[43].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ֧; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3598BDSP instance stat_regs_inst/g_DSP_rate[44].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[44].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3608BDSP instance stat_regs_inst/g_DSP_rate[45].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[45].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3618BDSP instance stat_regs_inst/g_DSP_rate[46].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[46].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ¨; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3628BDSP instance stat_regs_inst/g_DSP_rate[47].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[47].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3638BDSP instance stat_regs_inst/g_DSP_rate[48].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[48].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3648BDSP instance stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[49].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3658BDSP instance stat_regs_inst/g_DSP_rate[4].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[4].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ҩ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3668BDSP instance stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[50].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3678BDSP instance stat_regs_inst/g_DSP_rate[51].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[51].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3688BDSP instance stat_regs_inst/g_DSP_rate[52].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[52].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3698BDSP instance stat_regs_inst/g_DSP_rate[53].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[53].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3708BDSP instance stat_regs_inst/g_DSP_rate[54].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[54].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3718BDSP instance stat_regs_inst/g_DSP_rate[55].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[55].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3728BDSP instance stat_regs_inst/g_DSP_rate[56].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[56].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. Ϋ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3738BDSP instance stat_regs_inst/g_DSP_rate[57].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[57].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3748BDSP instance stat_regs_inst/g_DSP_rate[58].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[58].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3758BDSP instance stat_regs_inst/g_DSP_rate[59].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[59].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3768BDSP instance stat_regs_inst/g_DSP_rate[5].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[5].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ެ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3778BDSP instance stat_regs_inst/g_DSP_rate[60].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[60].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3788BDSP instance stat_regs_inst/g_DSP_rate[61].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[61].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3798BDSP instance stat_regs_inst/g_DSP_rate[62].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[62].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ʭ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3808BDSP instance stat_regs_inst/g_DSP_rate[63].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[63].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3818BDSP instance stat_regs_inst/g_DSP_rate[6].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[6].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3828BDSP instance stat_regs_inst/g_DSP_rate[7].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[7].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3838BDSP instance stat_regs_inst/g_DSP_rate[8].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[8].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ڮ; DSP48E2_inst *Warning"SYNTH-12*DSP input not registered2 SYNTH-12#3848BDSP instance stat_regs_inst/g_DSP_rate[9].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used.JDSP instance stat_regs_inst/g_DSP_rate[9].i_DSP_counterX4/DSP48E2_inst is not fully pipelined on the input side. AREG/BREG/CREG/DREG are not used. ; DSP48E2_inst *3Warning"SYNTH-13*combinational multiplier2 SYNTH-13#18BjDetected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst.JjDetected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr[1].i_DSP_MUX/DSP48E2_inst. : DSP48E2_inst *4Warning"SYNTH-13*combinational multiplier2 SYNTH-13#28BjDetected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst.JjDetected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr[2].i_DSP_MUX/DSP48E2_inst. : DSP48E2_inst *4Warning"SYNTH-13*combinational multiplier2 SYNTH-13#38BjDetected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst.JjDetected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr[3].i_DSP_MUX/DSP48E2_inst. : DSP48E2_inst *VWarning"SYNTH-13*combinational multiplier2 SYNTH-13#48B{Detected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst.J{Detected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[1].i_DSP_MUX/DSP48E2_inst. : DSP48E2_inst *VWarning"SYNTH-13*combinational multiplier2 SYNTH-13#58B{Detected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst.J{Detected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[2].i_DSP_MUX/DSP48E2_inst. : DSP48E2_inst *VWarning"SYNTH-13*combinational multiplier2 SYNTH-13#68B{Detected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst.J{Detected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr_j[0].g_DSP_MUX_i[3].i_DSP_MUX/DSP48E2_inst. : DSP48E2_inst *<Warning"SYNTH-13*combinational multiplier2 SYNTH-13#78BnDetected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst.JnDetected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_cntr_j[0].i_DSP_MUX_b/DSP48E2_inst. : DSP48E2_inst *8Warning"SYNTH-13*combinational multiplier2 SYNTH-13#88BlDetected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst.JlDetected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_rate_i[1].i_DSP_MUX/DSP48E2_inst. : DSP48E2_inst *8 Warning"SYNTH-13*combinational multiplier2 SYNTH-13#98BlDetected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst.JlDetected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_rate_i[2].i_DSP_MUX/DSP48E2_inst. : DSP48E2_inst *9 Warning"SYNTH-13*combinational multiplier2 SYNTH-13#108BlDetected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst.JlDetected combinational multiplier in DSP instance stat_regs_inst/g_DSP_MUX_rate_i[3].i_DSP_MUX/DSP48E2_inst. : DSP48E2_inst * Warning"SYNTH-13*combinational multiplier2 SYNTH-13#118B_Detected combinational multiplier in DSP instance stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst.J_Detected combinational multiplier in DSP instance stat_regs_inst/i_DSP_MUX_b_cntr/DSP48E2_inst. ; DSP48E2_inst * Warning"SYNTH-13*combinational multiplier2 SYNTH-13#128B_Detected combinational multiplier in DSP instance stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst.J_Detected combinational multiplier in DSP instance stat_regs_inst/i_DSP_MUX_b_rate/DSP48E2_inst. ; DSP48E2_inst *! Warning"SYNTH-13*combinational multiplier2 SYNTH-13#138B`Detected combinational multiplier in DSP instance stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst.J`Detected combinational multiplier in DSP instance stat_regs_inst/i_DSP_MUX_b_rate0/DSP48E2_inst. ; DSP48E2_inst *Warning"SYNTH-13*combinational multiplier2 SYNTH-13#148B^Detected combinational multiplier in DSP instance stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst.J^Detected combinational multiplier in DSP instance stat_regs_inst/i_DSP_MUX_rate1/DSP48E2_inst. ; DSP48E2_inst *Warning"SYNTH-13*combinational multiplier2 SYNTH-13#158BLDetected combinational multiplier in DSP instance stat_regs_inst/i_DSP_cntr.JLDetected combinational multiplier in DSP instance stat_regs_inst/i_DSP_cntr. ; i_DSP_cntr *Warning"SYNTH-13*combinational multiplier2 SYNTH-13#168BLDetected combinational multiplier in DSP instance stat_regs_inst/i_DSP_rate.JLDetected combinational multiplier in DSP instance stat_regs_inst/i_DSP_rate. : i_DSP_rate *lWarning"TIMING-9*Unknown CDC Logic2 TIMING-9#18BOne or more asynchronous Clock Domain Crossing has been detected between 2 clock domains through a set_false_path or a set_clock_groups or set_max_delay -datapath_only constraint but no double-registers logic synchronizer has been found on the side of the capture clock. It is recommended to run report_cdc for a complete and detailed CDC coverage. Please consider using XPM_CDC to avoid Critical severitiesJOne or more asynchronous Clock Domain Crossing has been detected between 2 clock domains through a set_false_path or a set_clock_groups or set_max_delay -datapath_only constraint but no double-registers logic synchronizer has been found on the side of the capture clock. It is recommended to run report_cdc for a complete and detailed CDC coverage. Please consider using XPM_CDC to avoid Critical severities1Warning" TIMING-10* Missing property on synchronizer2 TIMING-10#18BOne or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverageJOne or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverageWarning" TIMING-18*Missing input or output delay2 TIMING-18#18BKAn input delay is missing on FF_RX_PRESENTn[0] relative to clock(s) ipb_clkJKAn input delay is missing on FF_RX_PRESENTn[0] relative to clock(s) ipb_clkinput 6FF_RX_PRESENTn[0] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#28BKAn input delay is missing on FF_RX_PRESENTn[1] relative to clock(s) ipb_clkJKAn input delay is missing on FF_RX_PRESENTn[1] relative to clock(s) ipb_clkinput 5FF_RX_PRESENTn[1] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#38BKAn input delay is missing on FF_RX_PRESENTn[2] relative to clock(s) ipb_clkJKAn input delay is missing on FF_RX_PRESENTn[2] relative to clock(s) ipb_clkinput 4FF_RX_PRESENTn[2] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#48BKAn input delay is missing on FF_RX_PRESENTn[3] relative to clock(s) ipb_clkJKAn input delay is missing on FF_RX_PRESENTn[3] relative to clock(s) ipb_clkinput 3FF_RX_PRESENTn[3] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#58BFAn input delay is missing on FF_RX_SCL[0] relative to clock(s) ipb_clkJFAn input delay is missing on FF_RX_SCL[0] relative to clock(s) ipb_clkinput " FF_RX_SCL[0] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#68BFAn input delay is missing on FF_RX_SCL[1] relative to clock(s) ipb_clkJFAn input delay is missing on FF_RX_SCL[1] relative to clock(s) ipb_clkinput ! FF_RX_SCL[1] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#78BFAn input delay is missing on FF_RX_SCL[2] relative to clock(s) ipb_clkJFAn input delay is missing on FF_RX_SCL[2] relative to clock(s) ipb_clkinput   FF_RX_SCL[2] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#88BFAn input delay is missing on FF_RX_SCL[3] relative to clock(s) ipb_clkJFAn input delay is missing on FF_RX_SCL[3] relative to clock(s) ipb_clkinput  FF_RX_SCL[3] * Warning" TIMING-18*Missing input or output delay2 TIMING-18#98BFAn input delay is missing on FF_RX_SDA[0] relative to clock(s) ipb_clkJFAn input delay is missing on FF_RX_SDA[0] relative to clock(s) ipb_clkinput  FF_RX_SDA[0] * Warning" TIMING-18*Missing input or output delay2 TIMING-18#108BFAn input delay is missing on FF_RX_SDA[1] relative to clock(s) ipb_clkJFAn input delay is missing on FF_RX_SDA[1] relative to clock(s) ipb_clkinput  FF_RX_SDA[1] * Warning" TIMING-18*Missing input or output delay2 TIMING-18#118BFAn input delay is missing on FF_RX_SDA[2] relative to clock(s) ipb_clkJFAn input delay is missing on FF_RX_SDA[2] relative to clock(s) ipb_clkinput  FF_RX_SDA[2] * Warning" TIMING-18*Missing input or output delay2 TIMING-18#128BFAn input delay is missing on FF_RX_SDA[3] relative to clock(s) ipb_clkJFAn input delay is missing on FF_RX_SDA[3] relative to clock(s) ipb_clkinput  FF_RX_SDA[3] *  Warning" TIMING-18*Missing input or output delay2 TIMING-18#138BKAn input delay is missing on FF_TX_PRESENTn[0] relative to clock(s) ipb_clkJKAn input delay is missing on FF_TX_PRESENTn[0] relative to clock(s) ipb_clkinput 1FF_TX_PRESENTn[0] * Warning" TIMING-18*Missing input or output delay2 TIMING-18#148BKAn input delay is missing on FF_TX_PRESENTn[1] relative to clock(s) ipb_clkJKAn input delay is missing on FF_TX_PRESENTn[1] relative to clock(s) ipb_clkinput 0FF_TX_PRESENTn[1] * Warning" TIMING-18*Missing input or output delay2 TIMING-18#158BKAn input delay is missing on FF_TX_PRESENTn[2] relative to clock(s) ipb_clkJKAn input delay is missing on FF_TX_PRESENTn[2] relative to clock(s) ipb_clkinput /FF_TX_PRESENTn[2] * Warning" TIMING-18*Missing input or output delay2 TIMING-18#168BKAn input delay is missing on FF_TX_PRESENTn[3] relative to clock(s) ipb_clkJKAn input delay is missing on FF_TX_PRESENTn[3] relative to clock(s) ipb_clkinput .FF_TX_PRESENTn[3] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#178BFAn input delay is missing on FF_TX_SCL[0] relative to clock(s) ipb_clkJFAn input delay is missing on FF_TX_SCL[0] relative to clock(s) ipb_clkinput  FF_TX_SCL[0] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#188BFAn input delay is missing on FF_TX_SCL[1] relative to clock(s) ipb_clkJFAn input delay is missing on FF_TX_SCL[1] relative to clock(s) ipb_clkinput  FF_TX_SCL[1] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#198BFAn input delay is missing on FF_TX_SCL[2] relative to clock(s) ipb_clkJFAn input delay is missing on FF_TX_SCL[2] relative to clock(s) ipb_clkinput  FF_TX_SCL[2] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#208BFAn input delay is missing on FF_TX_SCL[3] relative to clock(s) ipb_clkJFAn input delay is missing on FF_TX_SCL[3] relative to clock(s) ipb_clkinput  FF_TX_SCL[3] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#218BFAn input delay is missing on FF_TX_SDA[0] relative to clock(s) ipb_clkJFAn input delay is missing on FF_TX_SDA[0] relative to clock(s) ipb_clkinput  FF_TX_SDA[0] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#228BFAn input delay is missing on FF_TX_SDA[1] relative to clock(s) ipb_clkJFAn input delay is missing on FF_TX_SDA[1] relative to clock(s) ipb_clkinput  FF_TX_SDA[1] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#238BFAn input delay is missing on FF_TX_SDA[2] relative to clock(s) ipb_clkJFAn input delay is missing on FF_TX_SDA[2] relative to clock(s) ipb_clkinput  FF_TX_SDA[2] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#248BFAn input delay is missing on FF_TX_SDA[3] relative to clock(s) ipb_clkJFAn input delay is missing on FF_TX_SDA[3] relative to clock(s) ipb_clkinput  FF_TX_SDA[3] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#258BIAn input delay is missing on Si_LOLb relative to clock(s) clk125, ipb_clkJIAn input delay is missing on Si_LOLb relative to clock(s) clk125, ipb_clkinput  Si_LOLb *Warning" TIMING-18*Missing input or output delay2 TIMING-18#268B@An input delay is missing on Si_SCL relative to clock(s) ipb_clkJ@An input delay is missing on Si_SCL relative to clock(s) ipb_clkinput  Si_SCL *Warning" TIMING-18*Missing input or output delay2 TIMING-18#278B@An input delay is missing on Si_SDA relative to clock(s) ipb_clkJ@An input delay is missing on Si_SDA relative to clock(s) ipb_clkinput  Si_SDA *Warning" TIMING-18*Missing input or output delay2 TIMING-18#288BMAn input delay is missing on board_id[0] relative to clock(s) clk125, ipb_clkJMAn input delay is missing on board_id[0] relative to clock(s) clk125, ipb_clkinput  board_id[0] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#298BMAn input delay is missing on board_id[1] relative to clock(s) clk125, ipb_clkJMAn input delay is missing on board_id[1] relative to clock(s) clk125, ipb_clkinput  board_id[1] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#308BMAn input delay is missing on board_id[2] relative to clock(s) clk125, ipb_clkJMAn input delay is missing on board_id[2] relative to clock(s) clk125, ipb_clkinput  board_id[2] *Warning" TIMING-18*Missing input or output delay2 TIMING-18#318BMAn input delay is missing on board_id[3] relative to clock(s) clk125, ipb_clkJMAn input delay is missing on board_id[3] relative to clock(s) clk125, ipb_clkinput  board_id[3] * Warning" TIMING-18*Missing input or output delay2 TIMING-18#328BMAn input delay is missing on board_id[4] relative to clock(s) clk125, ipb_clkJMAn input delay is missing on board_id[4] relative to clock(s) clk125, ipb_clkinput  board_id[4] *!Warning" TIMING-18*Missing input or output delay2 TIMING-18#338BMAn input delay is missing on board_id[5] relative to clock(s) clk125, ipb_clkJMAn input delay is missing on board_id[5] relative to clock(s) clk125, ipb_clkinput  board_id[5] *"Warning" TIMING-18*Missing input or output delay2 TIMING-18#348BMAn input delay is missing on board_id[6] relative to clock(s) clk125, ipb_clkJMAn input delay is missing on board_id[6] relative to clock(s) clk125, ipb_clkinput  board_id[6] *#Warning" TIMING-18*Missing input or output delay2 TIMING-18#358BIAn input delay is missing on rarp_en relative to clock(s) clk125, ipb_clkJIAn input delay is missing on rarp_en relative to clock(s) clk125, ipb_clkinput rarp_en *$Warning" TIMING-18*Missing input or output delay2 TIMING-18#368BJAn output delay is missing on FF_RX_RESETn[0] relative to clock(s) ipb_clkJJAn output delay is missing on FF_RX_RESETn[0] relative to clock(s) ipb_clkoutput ,FF_RX_RESETn[0] *%Warning" TIMING-18*Missing input or output delay2 TIMING-18#378BJAn output delay is missing on FF_RX_RESETn[1] relative to clock(s) ipb_clkJJAn output delay is missing on FF_RX_RESETn[1] relative to clock(s) ipb_clkoutput +FF_RX_RESETn[1] *&Warning" TIMING-18*Missing input or output delay2 TIMING-18#388BJAn output delay is missing on FF_RX_RESETn[2] relative to clock(s) ipb_clkJJAn output delay is missing on FF_RX_RESETn[2] relative to clock(s) ipb_clkoutput *FF_RX_RESETn[2] *'Warning" TIMING-18*Missing input or output delay2 TIMING-18#398BJAn output delay is missing on FF_RX_RESETn[3] relative to clock(s) ipb_clkJJAn output delay is missing on FF_RX_RESETn[3] relative to clock(s) ipb_clkoutput )FF_RX_RESETn[3] *(Warning" TIMING-18*Missing input or output delay2 TIMING-18#408BJAn output delay is missing on FF_TX_RESETn[0] relative to clock(s) ipb_clkJJAn output delay is missing on FF_TX_RESETn[0] relative to clock(s) ipb_clkoutput 'FF_TX_RESETn[0] *)Warning" TIMING-18*Missing input or output delay2 TIMING-18#418BJAn output delay is missing on FF_TX_RESETn[1] relative to clock(s) ipb_clkJJAn output delay is missing on FF_TX_RESETn[1] relative to clock(s) ipb_clkoutput &FF_TX_RESETn[1] **Warning" TIMING-18*Missing input or output delay2 TIMING-18#428BJAn output delay is missing on FF_TX_RESETn[2] relative to clock(s) ipb_clkJJAn output delay is missing on FF_TX_RESETn[2] relative to clock(s) ipb_clkoutput %FF_TX_RESETn[2] *+Warning" TIMING-18*Missing input or output delay2 TIMING-18#438BJAn output delay is missing on FF_TX_RESETn[3] relative to clock(s) ipb_clkJJAn output delay is missing on FF_TX_RESETn[3] relative to clock(s) ipb_clkoutput $FF_TX_RESETn[3] *,Warning" TIMING-18*Missing input or output delay2 TIMING-18#448BGAn output delay is missing on Si_IN_SEL[0] relative to clock(s) ipb_clkJGAn output delay is missing on Si_IN_SEL[0] relative to clock(s) ipb_clkoutput  Si_IN_SEL[0] *-Warning" TIMING-18*Missing input or output delay2 TIMING-18#458BGAn output delay is missing on Si_IN_SEL[1] relative to clock(s) ipb_clkJGAn output delay is missing on Si_IN_SEL[1] relative to clock(s) ipb_clkoutput   Si_IN_SEL[1] *Warning" TIMING-47*AFalse path or asynchronous clock group between synchronous clocks2 TIMING-47#18BA Clock Group timing constraint is set between synchronous clocks TTC_rxusrclk and fabric_clk_in (see constraint position 659 in the Timing Constraint window in Vivado IDE). Masking entire synchronous clock domains via set_false_path or set_clock_groups may result in failure in hardware.JA Clock Group timing constraint is set between synchronous clocks TTC_rxusrclk and fabric_clk_in (see constraint position 659 in the Timing Constraint window in Vivado IDE). Masking entire synchronous clock domains via set_false_path or set_clock_groups may result in failure in hardware. Clock Group659Warning"ULMTCS-1*+Control Sets use limits recommend reduction2 ULMTCS-1#18BThis design uses 21567 control sets (vs. available limit of 165840, determined by 1 control set per CLB). This exceeds the control set use guideline of 7.5 percent. This is at a level where reduction is RECOMMENDED (see UG949). Use report_control_sets to get more details.JThis design uses 21567 control sets (vs. available limit of 165840, determined by 1 control set per CLB). This exceeds the control set use guideline of 7.5 percent. This is at a level where reduction is RECOMMENDED (see UG949). Use report_control_sets to get more details.215671658407.5Warning"XDCB-1*Runtime intensive exceptions2XDCB-1#18BThe following constraint contains more than 10000 objects. To preserve runtime and memory performance, it is recommended to include minimum number of objects. Check whether this list can be simplified. -from = expands to 10704 design objects. set_multicycle_path -hold -from [get_pins {*gbtbank/*/*gbt_rxgearbox_inst/*_reg[*]/C}] -to [get_pins *gbtbank/*/*/descrambler/*/*_reg*/D] 5 D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc (Line: 151)JThe following constraint contains more than 10000 objects. To preserve runtime and memory performance, it is recommended to include minimum number of objects. Check whether this list can be simplified. -from = expands to 10704 design objects. set_multicycle_path -hold -from [get_pins {*gbtbank/*/*gbt_rxgearbox_inst/*_reg[*]/C}] -to [get_pins *gbtbank/*/*/descrambler/*/*_reg*/D] 5 D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc (Line: 151)10000)-from = expands to 10704 design objects. set_multicycle_path -hold -from [get_pins {*gbtbank/*/*gbt_rxgearbox_inst/*_reg[*]/C}] -to [get_pins *gbtbank/*/*/descrambler/*/*_reg*/D] 5[D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc (Line: 151)Warning"XDCB-1*Runtime intensive exceptions2XDCB-1#28BThe following constraint contains more than 10000 objects. To preserve runtime and memory performance, it is recommended to include minimum number of objects. Check whether this list can be simplified. -from = expands to 10704 design objects. set_multicycle_path -setup -from [get_pins {*gbtbank/*/*gbt_rxgearbox_inst/*_reg[*]/C}] -to [get_pins *gbtbank/*/*/descrambler/*/*_reg*/D] 6 D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc (Line: 150)JThe following constraint contains more than 10000 objects. To preserve runtime and memory performance, it is recommended to include minimum number of objects. Check whether this list can be simplified. -from = expands to 10704 design objects. set_multicycle_path -setup -from [get_pins {*gbtbank/*/*gbt_rxgearbox_inst/*_reg[*]/C}] -to [get_pins *gbtbank/*/*/descrambler/*/*_reg*/D] 6 D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc (Line: 150)10000)-from = expands to 10704 design objects. set_multicycle_path -setup -from [get_pins {*gbtbank/*/*gbt_rxgearbox_inst/*_reg[*]/C}] -to [get_pins *gbtbank/*/*/descrambler/*/*_reg*/D] 6[D:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/constrs_1/ngFEC_ipb.xdc (Line: 150)Advisory"CLKC-27*8MMCME3 with BUF_IN drives sequential IO not with CLKOUT02 CLKC-27#18BThe MMCME3 cell i_clk125_MMCM has COMPENSATION value BUF_IN, but CLKOUT2 output drives sequential IO cells. (The problem cell is i_I2C_if/I2C_array[8].i2c_sda_inst/IBUFCTRL_INST (in i_I2C_if/I2C_array[8].i2c_sda_inst macro).) In order to achieve insertion delay and phase-alignment for the IO sequential cells, a COMPENSATION of ZHOLD must be used and CLKOUT0 output must be the driver%STRJThe MMCME3 cell i_clk125_MMCM has COMPENSATION value BUF_IN, but CLKOUT2 output drives sequential IO cells. (The problem cell is i_I2C_if/I2C_array[8].i2c_sda_inst/IBUFCTRL_INST (in i_I2C_if/I2C_array[8].i2c_sda_inst macro).) In order to achieve insertion delay and phase-alignment for the IO sequential cells, a COMPENSATION of ZHOLD must be used and CLKOUT0 output must be the driver%STR2. (The problem cell is %ELG.)  i_clk125_MMCM * ; IBUFCTRL_INST *Advisory"CLKC-29*1MMCME3 not driven by IO has BUFG in feedback loop2 CLKC-29#18BThe MMCME3 cell fabric_clk_MMCM has a BUFGCE CLKFBOUT_bufg clock buffer in the feedback loop, but the clock input is not directly driven by an I/O to create a Zero Delay Buffer Clock (a common use for having a buffer in the feedback loop). If there is no specific need for this buffer in the feedback loop (e.g. no timing paths between CLKINx/CLKOUTx domains or low latency requirement), then it is suggested to remove that BUFG* from the feedback path. This will allow for a lower power solution and free the clock resource for other purposes.JThe MMCME3 cell fabric_clk_MMCM has a BUFGCE CLKFBOUT_bufg clock buffer in the feedback loop, but the clock input is not directly driven by an I/O to create a Zero Delay Buffer Clock (a common use for having a buffer in the feedback loop). If there is no specific need for this buffer in the feedback loop (e.g. no timing paths between CLKINx/CLKOUTx domains or low latency requirement), then it is suggested to remove that BUFG* from the feedback path. This will allow for a lower power solution and free the clock resource for other purposes.BUFGCE fabric_clk_MMCM * ; CLKFBOUT_bufg *Advisory"CLKC-29*1MMCME3 not driven by IO has BUFG in feedback loop2 CLKC-29#28BThe MMCME3 cell i_clk125_MMCM has a BUFGCE i_clk125_bufg clock buffer in the feedback loop, but the clock input is not directly driven by an I/O to create a Zero Delay Buffer Clock (a common use for having a buffer in the feedback loop). If there is no specific need for this buffer in the feedback loop (e.g. no timing paths between CLKINx/CLKOUTx domains or low latency requirement), then it is suggested to remove that BUFG* from the feedback path. This will allow for a lower power solution and free the clock resource for other purposes.JThe MMCME3 cell i_clk125_MMCM has a BUFGCE i_clk125_bufg clock buffer in the feedback loop, but the clock input is not directly driven by an I/O to create a Zero Delay Buffer Clock (a common use for having a buffer in the feedback loop). If there is no specific need for this buffer in the feedback loop (e.g. no timing paths between CLKINx/CLKOUTx domains or low latency requirement), then it is suggested to remove that BUFG* from the feedback path. This will allow for a lower power solution and free the clock resource for other purposes.BUFGCE  i_clk125_MMCM *  i_clk125_bufg *Advisory"CLKC-55**MMCME3 with global clock driver has no LOC2 CLKC-55#18BThe MMCME3_ADV cell fabric_clk_MMCM CLKIN1 or CLKIN2 pin is driven by global Clock buffer(s) i_tcds2_if/bufgce_clk_40_rx and does not have a LOC constraint. It is recommended to LOC the MMCM and use the CLOCK_DEDICATED_ROUTE constraint on the net(s) driven by the global Clock buffer(s).JThe MMCME3_ADV cell fabric_clk_MMCM CLKIN1 or CLKIN2 pin is driven by global Clock buffer(s) i_tcds2_if/bufgce_clk_40_rx and does not have a LOC constraint. It is recommended to LOC the MMCM and use the CLOCK_DEDICATED_ROUTE constraint on the net(s) driven by the global Clock buffer(s). MMCME3_ADVCLKIN1 or CLKIN2 pin is fabric_clk_MMCM * 8bufgce_clk_40_rx *Advisory"CLKC-55**MMCME3 with global clock driver has no LOC2 CLKC-55#28BThe MMCME3_ADV cell i_clk125_MMCM CLKIN1 or CLKIN2 pin is driven by global Clock buffer(s) i_refclk125_bufg and does not have a LOC constraint. It is recommended to LOC the MMCM and use the CLOCK_DEDICATED_ROUTE constraint on the net(s) driven by the global Clock buffer(s).JThe MMCME3_ADV cell i_clk125_MMCM CLKIN1 or CLKIN2 pin is driven by global Clock buffer(s) i_refclk125_bufg and does not have a LOC constraint. It is recommended to LOC the MMCM and use the CLOCK_DEDICATED_ROUTE constraint on the net(s) driven by the global Clock buffer(s). MMCME3_ADVCLKIN1 or CLKIN2 pin is  i_clk125_MMCM * i_refclk125_bufg *