Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 | Date : Sat Mar 13 04:54:19 2021 | Host : baby running 64-bit major release (build 9200) | Command : report_clock_utilization -file ngFEC_top_clock_utilization_routed.rpt | Design : ngFEC_top | Device : xcku115-flva2104 | Speed File : -1 PRODUCTION 1.26 12-04-2018 | Temperature Grade : C | Design State : Routed -------------------------------------------------------------------------------------------- Clock Utilization Report Table of Contents ----------------- 1. Clock Primitive Utilization 2. Global Clock Resources 3. Global Clock Source Details 4. Clock Regions : Clock Primitives 5. Clock Regions : Load Primitives 6. Clock Regions : Global Clock Summary 7. Clock Regions : Routing Resource Utilization 8. Device Cell Placement Summary for Global Clock g0 9. Device Cell Placement Summary for Global Clock g1 10. Device Cell Placement Summary for Global Clock g2 11. Device Cell Placement Summary for Global Clock g3 12. Device Cell Placement Summary for Global Clock g4 13. Device Cell Placement Summary for Global Clock g5 14. Device Cell Placement Summary for Global Clock g6 15. Device Cell Placement Summary for Global Clock g7 16. Device Cell Placement Summary for Global Clock g8 17. Device Cell Placement Summary for Global Clock g9 18. Device Cell Placement Summary for Global Clock g10 19. Device Cell Placement Summary for Global Clock g11 20. Device Cell Placement Summary for Global Clock g12 21. Device Cell Placement Summary for Global Clock g13 22. Device Cell Placement Summary for Global Clock g14 23. Device Cell Placement Summary for Global Clock g15 24. Device Cell Placement Summary for Global Clock g16 25. Device Cell Placement Summary for Global Clock g17 26. Device Cell Placement Summary for Global Clock g18 27. Device Cell Placement Summary for Global Clock g19 28. Device Cell Placement Summary for Global Clock g20 29. Device Cell Placement Summary for Global Clock g21 30. Device Cell Placement Summary for Global Clock g22 31. Device Cell Placement Summary for Global Clock g23 32. Device Cell Placement Summary for Global Clock g24 33. Device Cell Placement Summary for Global Clock g25 34. Device Cell Placement Summary for Global Clock g26 35. Device Cell Placement Summary for Global Clock g27 36. Device Cell Placement Summary for Global Clock g28 37. Device Cell Placement Summary for Global Clock g29 38. Device Cell Placement Summary for Global Clock g30 39. Device Cell Placement Summary for Global Clock g31 40. Device Cell Placement Summary for Global Clock g32 41. Device Cell Placement Summary for Global Clock g33 42. Device Cell Placement Summary for Global Clock g34 43. Device Cell Placement Summary for Global Clock g35 44. Device Cell Placement Summary for Global Clock g36 45. Device Cell Placement Summary for Global Clock g37 46. Device Cell Placement Summary for Global Clock g38 47. Device Cell Placement Summary for Global Clock g39 48. Device Cell Placement Summary for Global Clock g40 49. Device Cell Placement Summary for Global Clock g41 50. Device Cell Placement Summary for Global Clock g42 51. Device Cell Placement Summary for Global Clock g43 52. Device Cell Placement Summary for Global Clock g44 53. Device Cell Placement Summary for Global Clock g45 54. Device Cell Placement Summary for Global Clock g46 55. Device Cell Placement Summary for Global Clock g47 56. Device Cell Placement Summary for Global Clock g48 57. Device Cell Placement Summary for Global Clock g49 58. Device Cell Placement Summary for Global Clock g50 59. Device Cell Placement Summary for Global Clock g51 60. Device Cell Placement Summary for Global Clock g52 61. Device Cell Placement Summary for Global Clock g53 62. Device Cell Placement Summary for Global Clock g54 63. Device Cell Placement Summary for Global Clock g55 64. Device Cell Placement Summary for Global Clock g56 65. Device Cell Placement Summary for Global Clock g57 66. Device Cell Placement Summary for Global Clock g58 67. Device Cell Placement Summary for Global Clock g59 68. Device Cell Placement Summary for Global Clock g60 69. Device Cell Placement Summary for Global Clock g61 70. Device Cell Placement Summary for Global Clock g62 71. Device Cell Placement Summary for Global Clock g63 72. Clock Region Cell Placement per Global Clock: Region X0Y0 73. Clock Region Cell Placement per Global Clock: Region X1Y0 74. Clock Region Cell Placement per Global Clock: Region X2Y0 75. Clock Region Cell Placement per Global Clock: Region X3Y0 76. Clock Region Cell Placement per Global Clock: Region X4Y0 77. Clock Region Cell Placement per Global Clock: Region X5Y0 78. Clock Region Cell Placement per Global Clock: Region X0Y1 79. Clock Region Cell Placement per Global Clock: Region X1Y1 80. Clock Region Cell Placement per Global Clock: Region X2Y1 81. Clock Region Cell Placement per Global Clock: Region X3Y1 82. Clock Region Cell Placement per Global Clock: Region X4Y1 83. Clock Region Cell Placement per Global Clock: Region X5Y1 84. Clock Region Cell Placement per Global Clock: Region X0Y2 85. Clock Region Cell Placement per Global Clock: Region X1Y2 86. Clock Region Cell Placement per Global Clock: Region X2Y2 87. Clock Region Cell Placement per Global Clock: Region X3Y2 88. Clock Region Cell Placement per Global Clock: Region X4Y2 89. Clock Region Cell Placement per Global Clock: Region X5Y2 90. Clock Region Cell Placement per Global Clock: Region X0Y3 91. Clock Region Cell Placement per Global Clock: Region X1Y3 92. Clock Region Cell Placement per Global Clock: Region X2Y3 93. Clock Region Cell Placement per Global Clock: Region X3Y3 94. Clock Region Cell Placement per Global Clock: Region X4Y3 95. Clock Region Cell Placement per Global Clock: Region X5Y3 96. Clock Region Cell Placement per Global Clock: Region X0Y4 97. Clock Region Cell Placement per Global Clock: Region X1Y4 98. Clock Region Cell Placement per Global Clock: Region X2Y4 99. Clock Region Cell Placement per Global Clock: Region X3Y4 100. Clock Region Cell Placement per Global Clock: Region X4Y4 101. Clock Region Cell Placement per Global Clock: Region X5Y4 102. Clock Region Cell Placement per Global Clock: Region X0Y5 103. Clock Region Cell Placement per Global Clock: Region X1Y5 104. Clock Region Cell Placement per Global Clock: Region X2Y5 105. Clock Region Cell Placement per Global Clock: Region X3Y5 106. Clock Region Cell Placement per Global Clock: Region X4Y5 107. Clock Region Cell Placement per Global Clock: Region X5Y5 108. Clock Region Cell Placement per Global Clock: Region X0Y6 109. Clock Region Cell Placement per Global Clock: Region X1Y6 110. Clock Region Cell Placement per Global Clock: Region X2Y6 111. Clock Region Cell Placement per Global Clock: Region X3Y6 112. Clock Region Cell Placement per Global Clock: Region X4Y6 113. Clock Region Cell Placement per Global Clock: Region X5Y6 114. Clock Region Cell Placement per Global Clock: Region X0Y7 115. Clock Region Cell Placement per Global Clock: Region X1Y7 116. Clock Region Cell Placement per Global Clock: Region X2Y7 117. Clock Region Cell Placement per Global Clock: Region X3Y7 118. Clock Region Cell Placement per Global Clock: Region X4Y7 119. Clock Region Cell Placement per Global Clock: Region X5Y7 120. Clock Region Cell Placement per Global Clock: Region X0Y8 121. Clock Region Cell Placement per Global Clock: Region X1Y8 122. Clock Region Cell Placement per Global Clock: Region X2Y8 123. Clock Region Cell Placement per Global Clock: Region X3Y8 124. Clock Region Cell Placement per Global Clock: Region X4Y8 125. Clock Region Cell Placement per Global Clock: Region X5Y8 126. Clock Region Cell Placement per Global Clock: Region X0Y9 127. Clock Region Cell Placement per Global Clock: Region X1Y9 128. Clock Region Cell Placement per Global Clock: Region X2Y9 129. Clock Region Cell Placement per Global Clock: Region X3Y9 130. Clock Region Cell Placement per Global Clock: Region X4Y9 131. Clock Region Cell Placement per Global Clock: Region X5Y9 1. Clock Primitive Utilization ------------------------------ +------------+------+-----------+-----+--------------+--------+ | Type | Used | Available | LOC | Clock Region | Pblock | +------------+------+-----------+-----+--------------+--------+ | BUFGCE | 12 | 576 | 0 | 0 | 0 | | BUFGCE_DIV | 1 | 96 | 0 | 0 | 0 | | BUFGCTRL | 0 | 192 | 0 | 0 | 0 | | BUFG_GT | 51 | 384 | 0 | 0 | 0 | | MMCM | 2 | 24 | 0 | 0 | 0 | | PLL | 0 | 48 | 0 | 0 | 0 | +------------+------+-----------+-----+--------------+--------+ 2. Global Clock Resources ------------------------- +-----------+-----------+-----------------+------------+------------------+--------------+-----------+-------------------+-------------------+-------------+-----------------+--------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Root | Clock Delay Group | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+------------------+--------------+-----------+-------------------+-------------------+-------------+-----------------+--------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | src0 | BUFGCE/O | None | BUFGCE_X1Y106 | X2Y4 | X2Y4 | | 60 | 204776 | 0 | 32.000 | ipb_clk | i_ipb_clk_bufg/O | CLK | | g1 | src1 | BUFGCE/O | None | BUFGCE_X2Y119 | X4Y4 | X2Y4 | | 60 | 103803 | 0 | 24.952 | fabric_clk | fabric_clk_bufg/O | fabric_clk | | g2 | src2 | BUFGCE/O | None | BUFGCE_X2Y118 | X4Y4 | X2Y4 | | 52 | 27439 | 0 | 8.317 | tx_wordclk | tx_wordclk_bufg/O | tx_wordclk | | g3 | src3 | BUFGCE/O | None | BUFGCE_X1Y100 | X2Y4 | X3Y3 | | 20 | 14619 | 0 | 4.000 | clk250 | i_clk250_bufg/O | clk250 | | g4 | src4 | BUFGCE/O | None | BUFGCE_X1Y114 | X2Y4 | X3Y4 | | 31 | 3888 | 0 | 20.000 | DRPclk | i_DRPclk_bufg/O | DRPclk | | g5 | src5 | BUFGCE/O | None | BUFGCE_X1Y108 | X2Y4 | X3Y4 | | 9 | 3803 | 1 | 8.000 | clk125 | i_clk125_bufg/O | CLKFBIN | | g6 | src6 | BUFG_GT/O | None | BUFG_GT_X1Y1 | X5Y0 | X3Y2,X5Y0 | | 7 | 1861 | 0 | 3.119 | TTC_rxusrclk | i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] | | g7 | src7 | BUFGCE_DIV/O | None | BUFGCE_DIV_X1Y16 | X2Y4 | X4Y2 | | 4 | 791 | 1 | 24.952 | fabric_clk_in | i_tcds2_if/bufgce_clk_40_rx/O | i_tcds2_if/fabric_clk_in | | g8 | src8 | BUFG_GT/O | None | BUFG_GT_X1Y43 | X5Y1 | X3Y0 | | 5 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0] | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g9 | src9 | BUFG_GT/O | None | BUFG_GT_X1Y89 | X5Y3 | X4Y3 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_1 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g10 | src10 | BUFG_GT/O | None | BUFG_GT_X1Y88 | X5Y3 | X4Y3 | | 6 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_2 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g11 | src11 | BUFG_GT/O | None | BUFG_GT_X1Y45 | X5Y1 | X3Y0 | | 4 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_3 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g12 | src12 | BUFG_GT/O | None | BUFG_GT_X1Y41 | X5Y1 | X3Y0 | | 4 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_4 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g13 | src13 | BUFG_GT/O | None | BUFG_GT_X1Y40 | X5Y1 | X3Y1 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_5 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g14 | src14 | BUFG_GT/O | None | BUFG_GT_X1Y65 | X5Y2 | X4Y2 | | 2 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_6 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g15 | src15 | BUFG_GT/O | None | BUFG_GT_X1Y69 | X5Y2 | X4Y2 | | 2 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_7 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g16 | src16 | BUFG_GT/O | None | BUFG_GT_X1Y64 | X5Y2 | X4Y2 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_8 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g17 | src17 | BUFG_GT/O | None | BUFG_GT_X1Y67 | X5Y2 | X4Y2 | | 2 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_9 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g18 | src18 | BUFG_GT/O | None | BUFG_GT_X1Y91 | X5Y3 | X4Y3 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_10 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g19 | src19 | BUFG_GT/O | None | BUFG_GT_X1Y93 | X5Y3 | X4Y3 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_11 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g20 | src20 | BUFG_GT/O | None | BUFG_GT_X1Y185 | X5Y7 | X4Y7 | | 2 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_12 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g21 | src21 | BUFG_GT/O | None | BUFG_GT_X1Y237 | X5Y9 | X4Y9 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_13 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g22 | src22 | BUFG_GT/O | None | BUFG_GT_X1Y233 | X5Y9 | X4Y9 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_14 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g23 | src23 | BUFG_GT/O | None | BUFG_GT_X1Y189 | X5Y7 | X4Y7 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_15 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g24 | src24 | BUFG_GT/O | None | BUFG_GT_X1Y187 | X5Y7 | X4Y7 | | 2 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_16 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g25 | src25 | BUFG_GT/O | None | BUFG_GT_X1Y184 | X5Y7 | X4Y7 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_17 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g26 | src26 | BUFG_GT/O | None | BUFG_GT_X1Y211 | X5Y8 | X4Y8 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_18 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g27 | src27 | BUFG_GT/O | None | BUFG_GT_X1Y208 | X5Y8 | X4Y8 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_19 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g28 | src28 | BUFG_GT/O | None | BUFG_GT_X1Y209 | X5Y8 | X4Y8 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_20 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g29 | src29 | BUFG_GT/O | None | BUFG_GT_X1Y213 | X5Y8 | X4Y8 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_21 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g30 | src30 | BUFG_GT/O | None | BUFG_GT_X1Y235 | X5Y9 | X4Y9 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_22 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g31 | src31 | BUFG_GT/O | None | BUFG_GT_X1Y216 | X5Y9 | X4Y7 | | 6 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_23 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g32 | src32 | BUFG_GT/O | None | BUFG_GT_X0Y67 | X0Y2 | X1Y2 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_24 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g33 | src33 | BUFG_GT/O | None | BUFG_GT_X0Y112 | X0Y4 | X1Y4 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_25 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g34 | src34 | BUFG_GT/O | None | BUFG_GT_X0Y115 | X0Y4 | X1Y4 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_26 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g35 | src35 | BUFG_GT/O | None | BUFG_GT_X0Y69 | X0Y2 | X1Y2 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_27 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g36 | src36 | BUFG_GT/O | None | BUFG_GT_X0Y64 | X0Y2 | X1Y2 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_28 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g37 | src37 | BUFG_GT/O | None | BUFG_GT_X0Y65 | X0Y2 | X1Y2 | | 2 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_29 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g38 | src38 | BUFG_GT/O | None | BUFG_GT_X0Y93 | X0Y3 | X1Y3 | | 2 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_30 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g39 | src39 | BUFG_GT/O | None | BUFG_GT_X0Y91 | X0Y3 | X1Y3 | | 2 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_31 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g40 | src40 | BUFG_GT/O | None | BUFG_GT_X0Y88 | X0Y3 | X1Y3 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_32 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g41 | src41 | BUFG_GT/O | None | BUFG_GT_X0Y89 | X0Y3 | X1Y3 | | 2 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_33 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g42 | src42 | BUFG_GT/O | None | BUFG_GT_X0Y113 | X0Y4 | X1Y4 | | 4 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_34 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g43 | src43 | BUFG_GT/O | None | BUFG_GT_X0Y117 | X0Y4 | X1Y4 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_35 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g44 | src44 | BUFG_GT/O | None | BUFG_GT_X0Y187 | X0Y7 | X1Y7 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_36 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g45 | src45 | BUFG_GT/O | None | BUFG_GT_X0Y216 | X0Y9 | X1Y8 | | 4 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_37 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g46 | src46 | BUFG_GT/O | None | BUFG_GT_X0Y237 | X0Y9 | X1Y9 | | 2 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_38 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g47 | src47 | BUFG_GT/O | None | BUFG_GT_X0Y189 | X0Y7 | X1Y7 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_39 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g48 | src48 | BUFG_GT/O | None | BUFG_GT_X0Y185 | X0Y7 | X1Y7 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_40 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g49 | src49 | BUFG_GT/O | None | BUFG_GT_X0Y168 | X0Y7 | X1Y6 | | 4 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_41 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g50 | src50 | BUFG_GT/O | None | BUFG_GT_X0Y209 | X0Y8 | X1Y8 | | 2 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_42 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g51 | src51 | BUFG_GT/O | None | BUFG_GT_X0Y208 | X0Y8 | X1Y8 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_43 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g52 | src52 | BUFG_GT/O | None | BUFG_GT_X0Y211 | X0Y8 | X1Y8 | | 2 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_44 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g53 | src53 | BUFG_GT/O | None | BUFG_GT_X0Y213 | X0Y8 | X1Y8 | | 2 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_45 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g54 | src54 | BUFG_GT/O | None | BUFG_GT_X0Y235 | X0Y9 | X1Y9 | | 2 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_46 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g55 | src55 | BUFG_GT/O | None | BUFG_GT_X0Y233 | X0Y9 | X1Y9 | | 3 | 674 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_47 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g56 | src56 | BUFG_GT/O | None | BUFG_GT_X1Y3 | X5Y0 | X5Y0 | | 2 | 539 | 0 | 3.119 | txoutclk_out[0]_49 | i_tcds2_if/i_mgt_wrapper/i_txusrclk/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst/O | i_tcds2_if/i_mgt_wrapper/i_txusrclk/bbstub_txoutclk_out[0] | | g57 | src57 | BUFGCE/O | None | BUFGCE_X1Y98 | X2Y4 | X5Y0 | | 1 | 69 | 0 | 16.000 | clk62_5_dcm | i_clk62_5_bufg/O | clk62_5 | | g58 | src58 | BUFGCE/O | None | BUFGCE_X2Y111 | X4Y4 | X2Y4 | n/a | 1 | 0 | 1 | 24.952 | CLKFBOUT | CLKFBOUT_bufg/O | CLKFBOUT_bufg_n_0 | | g59 | src59 | BUFG_GT/O | None | BUFG_GT_X1Y0 | X5Y0 | X2Y4 | n/a | 1 | 0 | 1 | 8.000 | refclk125 | i_refclk125_bufg/O | CLKIN1 | | g60 | src60 | BUFGCE/O | None | BUFGCE_X1Y150 | X2Y6 | X2Y6 | n/a | 36 | 0 | 1392 | n/a | n/a | SFP_GEN[14].ngCCM_gbt/TX_Word_tmp[79]_i_1_bufg_place/O | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | src61 | BUFGCE/O | None | BUFGCE_X0Y128 | X0Y5 | X0Y5 | n/a | 59 | 0 | 8853 | n/a | n/a | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/reg_data[1]_i_1_bufg_place/O | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | src62 | BUFGCE/O | None | BUFGCE_X1Y158 | X2Y6 | X2Y6 | n/a | 49 | 0 | 5252 | n/a | n/a | fabric_clk_div2_reg_bufg_place/O | fabric_clk_div2 | | g63 | src63 | BUFGCE/O | None | BUFGCE_X1Y116 | X2Y4 | X2Y4 | n/a | 60 | 0 | 157668 | n/a | n/a | ipb_rst_BUFG_inst/O | ipb_rst_BUFG | +-----------+-----------+-----------------+------------+------------------+--------------+-----------+-------------------+-------------------+-------------+-----------------+--------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 3. Global Clock Source Details ------------------------------ +-----------+-----------+------------------------+---------------------+---------------------+--------------+-------------+-----------------+---------------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | +-----------+-----------+------------------------+---------------------+---------------------+--------------+-------------+-----------------+---------------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | src0 | g0 | MMCME3_ADV/CLKOUT2 | None | MMCME3_ADV_X1Y4 | X2Y4 | 1 | 0 | 32.000 | ipb_clk_dcm | i_clk125_MMCM/CLKOUT2 | ipb_clk_dcm | | src1 | g1 | MMCME3_ADV/CLKOUT0 | None | MMCME3_ADV_X2Y4 | X4Y4 | 1 | 0 | 24.952 | fabric_clk_dcm | fabric_clk_MMCM/CLKOUT0 | fabric_clk_dcm | | src2 | g2 | MMCME3_ADV/CLKOUT1 | None | MMCME3_ADV_X2Y4 | X4Y4 | 1 | 0 | 8.317 | tx_wordclk_dcm | fabric_clk_MMCM/CLKOUT1 | tx_wordclk_dcm | | src3 | g3 | MMCME3_ADV/CLKOUT3 | None | MMCME3_ADV_X1Y4 | X2Y4 | 1 | 0 | 4.000 | clk250_dcm | i_clk125_MMCM/CLKOUT3 | clk250_dcm | | src4 | g4 | MMCME3_ADV/CLKOUT0 | None | MMCME3_ADV_X1Y4 | X2Y4 | 1 | 0 | 20.000 | DRPclk_dcm | i_clk125_MMCM/CLKOUT0 | DRPclk_dcm | | src5 | g5 | MMCME3_ADV/CLKFBOUT | None | MMCME3_ADV_X1Y4 | X2Y4 | 1 | 0 | 8.000 | clk125_dcm | i_clk125_MMCM/CLKFBOUT | clk125_dcm | | src6 | g6 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y3 | GTHE3_CHANNEL_X1Y3 | X5Y0 | 2 | 0 | 3.119 | rxoutclk_out[0]_1 | i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/rxoutclk_out[0] | | src7 | g7 | BUFG_GT/O | None | BUFG_GT_X1Y1 | X5Y0 | 1861 | 0 | 3.119 | TTC_rxusrclk | i_tcds2_if/i_mgt_wrapper/i_rxusrclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst/O | i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] | | src8 | g8 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y4 | GTHE3_CHANNEL_X1Y4 | X5Y1 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0] | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src9 | g9 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y14 | GTHE3_CHANNEL_X1Y14 | X5Y3 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_1 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src10 | g10 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y15 | GTHE3_CHANNEL_X1Y15 | X5Y3 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_2 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src11 | g11 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y5 | GTHE3_CHANNEL_X1Y5 | X5Y1 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_3 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src12 | g12 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y6 | GTHE3_CHANNEL_X1Y6 | X5Y1 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_4 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src13 | g13 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y7 | GTHE3_CHANNEL_X1Y7 | X5Y1 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_5 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src14 | g14 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y8 | GTHE3_CHANNEL_X1Y8 | X5Y2 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_6 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src15 | g15 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y9 | GTHE3_CHANNEL_X1Y9 | X5Y2 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_7 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src16 | g16 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y10 | GTHE3_CHANNEL_X1Y10 | X5Y2 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_8 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src17 | g17 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y11 | GTHE3_CHANNEL_X1Y11 | X5Y2 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_9 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src18 | g18 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y12 | GTHE3_CHANNEL_X1Y12 | X5Y3 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_10 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src19 | g19 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y13 | GTHE3_CHANNEL_X1Y13 | X5Y3 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_11 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src20 | g20 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y28 | GTHE3_CHANNEL_X1Y28 | X5Y7 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_12 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src21 | g21 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y38 | GTHE3_CHANNEL_X1Y38 | X5Y9 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_13 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src22 | g22 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y39 | GTHE3_CHANNEL_X1Y39 | X5Y9 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_14 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src23 | g23 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y29 | GTHE3_CHANNEL_X1Y29 | X5Y7 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_15 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src24 | g24 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y30 | GTHE3_CHANNEL_X1Y30 | X5Y7 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_16 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src25 | g25 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y31 | GTHE3_CHANNEL_X1Y31 | X5Y7 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_17 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src26 | g26 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y32 | GTHE3_CHANNEL_X1Y32 | X5Y8 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_18 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src27 | g27 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y33 | GTHE3_CHANNEL_X1Y33 | X5Y8 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_19 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src28 | g28 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y34 | GTHE3_CHANNEL_X1Y34 | X5Y8 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_20 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src29 | g29 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y35 | GTHE3_CHANNEL_X1Y35 | X5Y8 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_21 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src30 | g30 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y36 | GTHE3_CHANNEL_X1Y36 | X5Y9 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_22 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src31 | g31 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X1Y37 | GTHE3_CHANNEL_X1Y37 | X5Y9 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_23 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src32 | g32 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y8 | GTHE3_CHANNEL_X0Y8 | X0Y2 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_24 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src33 | g33 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y18 | GTHE3_CHANNEL_X0Y18 | X0Y4 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_25 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src34 | g34 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y19 | GTHE3_CHANNEL_X0Y19 | X0Y4 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_26 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src35 | g35 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y9 | GTHE3_CHANNEL_X0Y9 | X0Y2 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_27 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src36 | g36 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y10 | GTHE3_CHANNEL_X0Y10 | X0Y2 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_28 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src37 | g37 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y11 | GTHE3_CHANNEL_X0Y11 | X0Y2 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_29 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src38 | g38 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y12 | GTHE3_CHANNEL_X0Y12 | X0Y3 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_30 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src39 | g39 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y13 | GTHE3_CHANNEL_X0Y13 | X0Y3 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_31 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src40 | g40 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y14 | GTHE3_CHANNEL_X0Y14 | X0Y3 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_32 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src41 | g41 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y15 | GTHE3_CHANNEL_X0Y15 | X0Y3 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_33 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src42 | g42 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y16 | GTHE3_CHANNEL_X0Y16 | X0Y4 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_34 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src43 | g43 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y17 | GTHE3_CHANNEL_X0Y17 | X0Y4 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_35 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src44 | g44 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y28 | GTHE3_CHANNEL_X0Y28 | X0Y7 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_36 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src45 | g45 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y38 | GTHE3_CHANNEL_X0Y38 | X0Y9 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_37 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src46 | g46 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y39 | GTHE3_CHANNEL_X0Y39 | X0Y9 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_38 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src47 | g47 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y29 | GTHE3_CHANNEL_X0Y29 | X0Y7 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_39 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src48 | g48 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y30 | GTHE3_CHANNEL_X0Y30 | X0Y7 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_40 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src49 | g49 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y31 | GTHE3_CHANNEL_X0Y31 | X0Y7 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_41 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src50 | g50 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y32 | GTHE3_CHANNEL_X0Y32 | X0Y8 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_42 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src51 | g51 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y33 | GTHE3_CHANNEL_X0Y33 | X0Y8 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_43 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src52 | g52 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y34 | GTHE3_CHANNEL_X0Y34 | X0Y8 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_44 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src53 | g53 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y35 | GTHE3_CHANNEL_X0Y35 | X0Y8 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_45 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src54 | g54 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y36 | GTHE3_CHANNEL_X0Y36 | X0Y9 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_46 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src55 | g55 | GTHE3_CHANNEL/RXOUTCLK | GTHE3_CHANNEL_X0Y37 | GTHE3_CHANNEL_X0Y37 | X0Y9 | 2 | 0 | 8.317 | gtwiz_userclk_rx_srcclk_out[0]_47 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/RXOUTCLK | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gtwiz_userclk_rx_srcclk_out[0] | | src56 | g56 | GTHE3_CHANNEL/TXOUTCLK | GTHE3_CHANNEL_X1Y3 | GTHE3_CHANNEL_X1Y3 | X5Y0 | 2 | 0 | 3.119 | txoutclk_out[0]_49 | i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST/TXOUTCLK | i_tcds2_if/i_mgt_wrapper/i_mgt/inst/gen_gtwizard_gthe3_top.ttc_mgt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/txoutclk_out[0] | | src57 | g57 | MMCME3_ADV/CLKOUT1 | None | MMCME3_ADV_X1Y4 | X2Y4 | 1 | 0 | 16.000 | clk62_5_dcm | i_clk125_MMCM/CLKOUT1 | clk62_5_dcm | | src58 | g58 | MMCME3_ADV/CLKFBOUT | None | MMCME3_ADV_X2Y4 | X4Y4 | 1 | 0 | 24.952 | CLKFBOUT | fabric_clk_MMCM/CLKFBOUT | CLKFBOUT | | src59 | g59 | IBUFDS_GTE3/ODIV2 | GTHE3_COMMON_X1Y0 | GTHE3_COMMON_X1Y0 | X5Y0 | 2 | 0 | 8.000 | refclk125 | i_refclk125_ibuf/ODIV2 | refclk125_o | | src60 | g60 | LUT1/O | None | SLICE_X48Y375 | X2Y6 | 1 | 2 | | | SFP_GEN[14].ngCCM_gbt/TX_Word_tmp[79]_i_1/O | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0]_bufg_place | | src61 | g61 | LUT1/O | None | SLICE_X9Y308 | X0Y5 | 1 | 0 | | | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/reg_data[1]_i_1/O | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0]_bufg_place | | src62 | g62 | FDRE/Q | None | SLICE_X43Y370 | X1Y6 | 1 | 0 | | | fabric_clk_div2_reg/Q | fabric_clk_div2_bufg_place | | src63 | g63 | FDRE/Q | None | SLICE_X48Y271 | X2Y4 | 1 | 0 | | | ipb_rst_reg_lopt_replica/Q | Q_replN | +-----------+-----------+------------------------+---------------------+---------------------+--------------+-------------+-----------------+---------------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 4. Clock Regions : Clock Primitives ----------------------------------- +-------------------+---------------+---------------+---------------+---------------+---------------+---------------+---------------+ | | Global Clock | BUFGCE | BUFGCE_DIV | BUFGCTRL | BUFG_GT | MMCM | PLL | +-------------------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ | X0Y0 | 4 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X1Y0 | 4 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X2Y0 | 15 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X3Y0 | 13 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X4Y0 | 19 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X5Y0 | 10 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 24 | 0 | 0 | 0 | 0 | | X0Y1 | 7 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X1Y1 | 8 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X2Y1 | 21 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X3Y1 | 15 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X4Y1 | 31* | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X5Y1 | 15 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 24 | 0 | 0 | 0 | 0 | | X0Y2 | 11 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 24 | 0 | 0 | 0 | 0 | | X1Y2 | 13 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X2Y2 | 26* | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X3Y2 | 15 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X4Y2 | 28* | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X5Y2 | 12 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 24 | 0 | 0 | 0 | 0 | | X0Y3 | 11 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 24 | 0 | 0 | 0 | 0 | | X1Y3 | 13 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X2Y3 | 27* | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X3Y3 | 16 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X4Y3 | 30* | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X5Y3 | 14 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 24 | 0 | 0 | 0 | 0 | | X0Y4 | 11 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 24 | 0 | 0 | 0 | 0 | | X1Y4 | 13 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X2Y4 | 31* | 24 | 6 | 24 | 1 | 4 | 0 | 8 | 0 | 0 | 1 | 1 | 0 | 2 | | X3Y4 | 15 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X4Y4 | 25* | 24 | 3 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 1 | 1 | 0 | 2 | | X5Y4 | 10 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | 0 | | X0Y5 | 7 | 24 | 1 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X1Y5 | 7 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X2Y5 | 15 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X3Y5 | 9 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X4Y5 | 14 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X5Y5 | 6 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | 0 | | X0Y6 | 7 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X1Y6 | 9 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X2Y6 | 18 | 24 | 2 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X3Y6 | 8 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X4Y6 | 14 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X5Y6 | 7 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | 0 | | X0Y7 | 11 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 24 | 0 | 0 | 0 | 0 | | X1Y7 | 12 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X2Y7 | 24 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X3Y7 | 12 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X4Y7 | 24 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X5Y7 | 11 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 24 | 0 | 0 | 0 | 0 | | X0Y8 | 9 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 24 | 0 | 0 | 0 | 0 | | X1Y8 | 12 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X2Y8 | 25* | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X3Y8 | 13 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X4Y8 | 24 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X5Y8 | 10 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 24 | 0 | 0 | 0 | 0 | | X0Y9 | 9 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 24 | 0 | 0 | 0 | 0 | | X1Y9 | 11 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X2Y9 | 23 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X3Y9 | 12 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | X4Y9 | 20 | 24 | 0 | 24 | 0 | 4 | 0 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | | X5Y9 | 10 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 24 | 0 | 0 | 0 | 0 | +-------------------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+ * Global Clock column represents track count; while other columns represents cell counts 5. Clock Regions : Load Primitives ---------------------------------- +-------------------+------------------+------------------+------------------+------------------+------------------+------------------+------------------+ | | Global Clock | FF | LUTRAM | Block RAM (18K) | DSP | GT | HARD IP | +-------------------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+ | X0Y0 | 4 | 24 | 6236 | 20160 | 0 | 4800 | 71 | 72 | 0 | 120 | 0 | 0 | 0 | 0 | | X1Y0 | 4 | 24 | 6961 | 22080 | 0 | 5280 | 70 | 72 | 0 | 96 | 0 | 0 | 0 | 0 | | X2Y0 | 15 | 24 | 6632 | 20160 | 0 | 4800 | 71 | 72 | 0 | 120 | 0 | 0 | 0 | 0 | | X3Y0 | 13 | 24 | 7162 | 22080 | 0 | 5280 | 72 | 72 | 0 | 96 | 0 | 0 | 0 | 0 | | X4Y0 | 19 | 24 | 6460 | 20160 | 0 | 4800 | 71 | 72 | 0 | 120 | 0 | 0 | 0 | 0 | | X5Y0 | 10 | 24 | 7307 | 21120 | 9 | 960 | 53 | 72 | 0 | 0 | 2 | 4 | 0 | 1 | | X0Y1 | 7 | 24 | 6995 | 22080 | 1 | 5760 | 72 | 72 | 0 | 120 | 0 | 0 | 0 | 0 | | X1Y1 | 8 | 24 | 7323 | 24000 | 0 | 6240 | 71 | 72 | 2 | 96 | 0 | 0 | 0 | 0 | | X2Y1 | 21 | 24 | 6757 | 22080 | 0 | 5760 | 71 | 72 | 34 | 120 | 0 | 0 | 0 | 0 | | X3Y1 | 15 | 24 | 7770 | 24000 | 0 | 6240 | 70 | 72 | 13 | 96 | 0 | 0 | 0 | 0 | | X4Y1 | 31* | 24 | 7320 | 22080 | 0 | 5760 | 68 | 72 | 49 | 120 | 0 | 0 | 0 | 0 | | X5Y1 | 15 | 24 | 7638 | 23040 | 14 | 1920 | 67 | 72 | 0 | 0 | 4 | 4 | 0 | 0 | | X0Y2 | 11 | 24 | 7465 | 22080 | 4 | 5760 | 70 | 72 | 0 | 120 | 4 | 4 | 0 | 0 | | X1Y2 | 13 | 24 | 7770 | 24000 | 0 | 6240 | 72 | 72 | 20 | 96 | 0 | 0 | 0 | 0 | | X2Y2 | 26* | 24 | 7599 | 22080 | 0 | 5760 | 69 | 72 | 99 | 120 | 0 | 0 | 0 | 0 | | X3Y2 | 15 | 24 | 7409 | 24000 | 0 | 6240 | 66 | 72 | 57 | 96 | 0 | 0 | 0 | 0 | | X4Y2 | 28* | 24 | 7090 | 22080 | 0 | 5760 | 60 | 72 | 70 | 120 | 0 | 0 | 0 | 0 | | X5Y2 | 12 | 24 | 7538 | 23040 | 4 | 1920 | 66 | 72 | 0 | 0 | 4 | 4 | 0 | 0 | | X0Y3 | 11 | 24 | 7512 | 22080 | 4 | 5760 | 67 | 72 | 0 | 120 | 4 | 4 | 0 | 0 | | X1Y3 | 13 | 24 | 8098 | 24000 | 0 | 6240 | 71 | 72 | 4 | 96 | 0 | 0 | 0 | 0 | | X2Y3 | 27* | 24 | 8086 | 22080 | 0 | 5760 | 64 | 72 | 49 | 120 | 0 | 0 | 0 | 0 | | X3Y3 | 16 | 24 | 7865 | 24000 | 2 | 6240 | 59 | 72 | 53 | 96 | 0 | 0 | 0 | 0 | | X4Y3 | 30* | 24 | 8401 | 22080 | 0 | 5760 | 64 | 72 | 60 | 120 | 0 | 0 | 0 | 0 | | X5Y3 | 14 | 24 | 7611 | 23040 | 30 | 1920 | 57 | 72 | 0 | 0 | 4 | 4 | 0 | 1 | | X0Y4 | 11 | 24 | 6730 | 20160 | 3 | 4800 | 55 | 72 | 0 | 120 | 4 | 4 | 0 | 0 | | X1Y4 | 13 | 24 | 7092 | 22080 | 0 | 5280 | 69 | 72 | 14 | 96 | 0 | 0 | 0 | 0 | | X2Y4 | 31* | 24 | 7331 | 20160 | 1 | 4800 | 51 | 72 | 33 | 120 | 0 | 0 | 0 | 0 | | X3Y4 | 15 | 24 | 7752 | 22080 | 0 | 5280 | 46 | 72 | 29 | 96 | 0 | 0 | 0 | 0 | | X4Y4 | 25* | 24 | 7668 | 20160 | 0 | 4800 | 31 | 72 | 33 | 120 | 0 | 0 | 0 | 0 | | X5Y4 | 10 | 24 | 3811 | 21120 | 43 | 960 | 18 | 72 | 0 | 0 | 0 | 4 | 0 | 1 | | X0Y5 | 7 | 24 | 4013 | 20160 | 0 | 4800 | 48 | 72 | 0 | 120 | 0 | 0 | 0 | 0 | | X1Y5 | 7 | 24 | 5789 | 22080 | 0 | 5280 | 59 | 72 | 0 | 96 | 0 | 0 | 0 | 0 | | X2Y5 | 15 | 24 | 6041 | 20160 | 0 | 4800 | 67 | 72 | 0 | 120 | 0 | 0 | 0 | 0 | | X3Y5 | 9 | 24 | 6362 | 22080 | 0 | 5280 | 48 | 72 | 0 | 96 | 0 | 0 | 0 | 0 | | X4Y5 | 14 | 24 | 5640 | 20160 | 0 | 4800 | 64 | 72 | 0 | 120 | 0 | 0 | 0 | 0 | | X5Y5 | 6 | 24 | 5354 | 21120 | 0 | 960 | 66 | 72 | 0 | 0 | 0 | 4 | 0 | 1 | | X0Y6 | 7 | 24 | 4357 | 22080 | 0 | 5760 | 58 | 72 | 0 | 120 | 0 | 0 | 0 | 0 | | X1Y6 | 9 | 24 | 6145 | 24000 | 0 | 6240 | 67 | 72 | 0 | 96 | 0 | 0 | 0 | 0 | | X2Y6 | 18 | 24 | 6390 | 22080 | 0 | 5760 | 62 | 72 | 0 | 120 | 0 | 0 | 0 | 0 | | X3Y6 | 8 | 24 | 6841 | 24000 | 0 | 6240 | 67 | 72 | 0 | 96 | 0 | 0 | 0 | 0 | | X4Y6 | 14 | 24 | 6007 | 22080 | 0 | 5760 | 61 | 72 | 0 | 120 | 0 | 0 | 0 | 0 | | X5Y6 | 7 | 24 | 5225 | 23040 | 1 | 1920 | 52 | 72 | 0 | 0 | 0 | 4 | 0 | 0 | | X0Y7 | 11 | 24 | 5850 | 22080 | 4 | 5760 | 49 | 72 | 0 | 120 | 4 | 4 | 0 | 0 | | X1Y7 | 12 | 24 | 6796 | 24000 | 0 | 6240 | 56 | 72 | 0 | 96 | 0 | 0 | 0 | 0 | | X2Y7 | 24 | 24 | 6402 | 22080 | 0 | 5760 | 64 | 72 | 0 | 120 | 0 | 0 | 0 | 0 | | X3Y7 | 12 | 24 | 6935 | 24000 | 0 | 6240 | 52 | 72 | 0 | 96 | 0 | 0 | 0 | 0 | | X4Y7 | 24 | 24 | 6041 | 22080 | 0 | 5760 | 67 | 72 | 0 | 120 | 0 | 0 | 0 | 0 | | X5Y7 | 11 | 24 | 6675 | 23040 | 4 | 1920 | 58 | 72 | 0 | 0 | 4 | 4 | 0 | 0 | | X0Y8 | 9 | 24 | 4506 | 22080 | 5 | 5760 | 46 | 72 | 0 | 120 | 4 | 4 | 0 | 0 | | X1Y8 | 12 | 24 | 6217 | 24000 | 0 | 6240 | 62 | 72 | 0 | 96 | 0 | 0 | 0 | 0 | | X2Y8 | 25* | 24 | 6641 | 22080 | 0 | 5760 | 54 | 72 | 0 | 120 | 0 | 0 | 0 | 0 | | X3Y8 | 13 | 24 | 7102 | 24000 | 0 | 6240 | 67 | 72 | 0 | 96 | 0 | 0 | 0 | 0 | | X4Y8 | 24 | 24 | 6084 | 22080 | 0 | 5760 | 59 | 72 | 0 | 120 | 0 | 0 | 0 | 0 | | X5Y8 | 10 | 24 | 6533 | 23040 | 4 | 1920 | 52 | 72 | 0 | 0 | 4 | 4 | 0 | 1 | | X0Y9 | 9 | 24 | 2625 | 20160 | 3 | 4800 | 28 | 72 | 0 | 120 | 4 | 4 | 0 | 0 | | X1Y9 | 11 | 24 | 4992 | 22080 | 0 | 5280 | 44 | 72 | 0 | 96 | 0 | 0 | 0 | 0 | | X2Y9 | 23 | 24 | 5548 | 20160 | 0 | 4800 | 52 | 72 | 0 | 120 | 0 | 0 | 0 | 0 | | X3Y9 | 12 | 24 | 5249 | 22080 | 0 | 5280 | 54 | 72 | 0 | 96 | 0 | 0 | 0 | 0 | | X4Y9 | 20 | 24 | 4723 | 20160 | 0 | 4800 | 47 | 72 | 0 | 120 | 0 | 0 | 0 | 0 | | X5Y9 | 10 | 24 | 4240 | 21120 | 3 | 960 | 26 | 72 | 0 | 0 | 4 | 4 | 0 | 1 | +-------------------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+--------+---------+ * Global Clock column represents track count; while other columns represents cell counts 6. Clock Regions : Global Clock Summary --------------------------------------- All Modules +----+----+----+----+----+----+----+ | | X0 | X1 | X2 | X3 | X4 | X5 | +----+----+----+----+----+----+----+ | Y9 | 9 | 11 | 12 | 12 | 10 | 10 | | Y8 | 9 | 12 | 13 | 13 | 12 | 10 | | Y7 | 11 | 12 | 12 | 12 | 13 | 11 | | Y6 | 7 | 9 | 9 | 8 | 8 | 7 | | Y5 | 7 | 7 | 8 | 10 | 7 | 6 | | Y4 | 11 | 13 | 19 | 18 | 14 | 11 | | Y3 | 11 | 13 | 15 | 16 | 15 | 15 | | Y2 | 11 | 13 | 14 | 15 | 15 | 13 | | Y1 | 7 | 8 | 14 | 15 | 16 | 16 | | Y0 | 4 | 4 | 12 | 14 | 11 | 11 | +----+----+----+----+----+----+----+ 7. Clock Regions : Routing Resource Utilization ----------------------------------------------- All Modules +-------------------+----------------------+-----------------------+----------------------+----------------------+ | | HROUTES | HDISTRS | VROUTES | VDISTRS | +-------------------+------+-------+-------+------+-------+--------+------+-------+-------+------+-------+-------+ | Clock Region Name | Used | Avail | Util% | Used | Avail | Util% | Used | Avail | Util% | Used | Avail | Util% | +-------------------+------+-------+-------+------+-------+--------+------+-------+-------+------+-------+-------+ | X0Y0 | 0 | 24 | 0.00 | 4 | 24 | 16.67 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X1Y0 | 0 | 24 | 0.00 | 4 | 24 | 16.67 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | | X2Y0 | 2 | 24 | 8.33 | 15 | 24 | 62.50 | 0 | 24 | 0.00 | 6 | 24 | 25.00 | | X3Y0 | 4 | 24 | 16.67 | 13 | 24 | 54.17 | 3 | 24 | 12.50 | 6 | 24 | 25.00 | | X4Y0 | 6 | 24 | 25.00 | 19 | 24 | 79.17 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X5Y0 | 6 | 24 | 25.00 | 10 | 24 | 41.67 | 1 | 24 | 4.17 | 2 | 24 | 8.33 | | X0Y1 | 0 | 24 | 0.00 | 7 | 24 | 29.17 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X1Y1 | 0 | 24 | 0.00 | 8 | 24 | 33.33 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | | X2Y1 | 0 | 24 | 0.00 | 21 | 24 | 87.50 | 1 | 24 | 4.17 | 6 | 24 | 25.00 | | X3Y1 | 4 | 24 | 16.67 | 15 | 24 | 62.50 | 4 | 24 | 16.67 | 5 | 24 | 20.83 | | X4Y1 | 12 | 24 | 50.00 | 31 | 24 | 129.17 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X5Y1 | 8 | 24 | 33.33 | 15 | 24 | 62.50 | 1 | 24 | 4.17 | 0 | 24 | 0.00 | | X0Y2 | 8 | 24 | 33.33 | 11 | 24 | 45.83 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X1Y2 | 8 | 24 | 33.33 | 13 | 24 | 54.17 | 0 | 24 | 0.00 | 4 | 24 | 16.67 | | X2Y2 | 0 | 24 | 0.00 | 26 | 24 | 108.33 | 1 | 24 | 4.17 | 6 | 24 | 25.00 | | X3Y2 | 0 | 24 | 0.00 | 15 | 24 | 62.50 | 1 | 24 | 4.17 | 4 | 24 | 16.67 | | X4Y2 | 4 | 24 | 16.67 | 28 | 24 | 116.67 | 1 | 24 | 4.17 | 5 | 24 | 20.83 | | X5Y2 | 8 | 24 | 33.33 | 12 | 24 | 50.00 | 1 | 24 | 4.17 | 0 | 24 | 0.00 | | X0Y3 | 8 | 24 | 33.33 | 11 | 24 | 45.83 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X1Y3 | 8 | 24 | 33.33 | 13 | 24 | 54.17 | 0 | 24 | 0.00 | 4 | 24 | 16.67 | | X2Y3 | 0 | 24 | 0.00 | 27 | 24 | 112.50 | 1 | 24 | 4.17 | 6 | 24 | 25.00 | | X3Y3 | 0 | 24 | 0.00 | 16 | 24 | 66.67 | 2 | 24 | 8.33 | 3 | 24 | 12.50 | | X4Y3 | 4 | 24 | 16.67 | 30 | 24 | 125.00 | 1 | 24 | 4.17 | 5 | 24 | 20.83 | | X5Y3 | 8 | 24 | 33.33 | 14 | 24 | 58.33 | 1 | 24 | 4.17 | 0 | 24 | 0.00 | | X0Y4 | 8 | 24 | 33.33 | 11 | 24 | 45.83 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X1Y4 | 8 | 24 | 33.33 | 13 | 24 | 54.17 | 0 | 24 | 0.00 | 4 | 24 | 16.67 | | X2Y4 | 19 | 24 | 79.17 | 31 | 24 | 129.17 | 1 | 24 | 4.17 | 8 | 24 | 33.33 | | X3Y4 | 16 | 24 | 66.67 | 15 | 24 | 62.50 | 2 | 24 | 8.33 | 3 | 24 | 12.50 | | X4Y4 | 8 | 24 | 33.33 | 25 | 24 | 104.17 | 1 | 24 | 4.17 | 0 | 24 | 0.00 | | X5Y4 | 1 | 24 | 4.17 | 10 | 24 | 41.67 | 1 | 24 | 4.17 | 0 | 24 | 0.00 | | X0Y5 | 1 | 24 | 4.17 | 7 | 24 | 29.17 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X1Y5 | 0 | 24 | 0.00 | 7 | 24 | 29.17 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | | X2Y5 | 0 | 24 | 0.00 | 15 | 24 | 62.50 | 0 | 24 | 0.00 | 6 | 24 | 25.00 | | X3Y5 | 0 | 24 | 0.00 | 9 | 24 | 37.50 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X4Y5 | 0 | 24 | 0.00 | 14 | 24 | 58.33 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X5Y5 | 0 | 24 | 0.00 | 6 | 24 | 25.00 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | | X0Y6 | 0 | 24 | 0.00 | 7 | 24 | 29.17 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X1Y6 | 0 | 24 | 0.00 | 9 | 24 | 37.50 | 1 | 24 | 4.17 | 1 | 24 | 4.17 | | X2Y6 | 3 | 24 | 12.50 | 18 | 24 | 75.00 | 0 | 24 | 0.00 | 6 | 24 | 25.00 | | X3Y6 | 0 | 24 | 0.00 | 8 | 24 | 33.33 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X4Y6 | 0 | 24 | 0.00 | 14 | 24 | 58.33 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X5Y6 | 0 | 24 | 0.00 | 7 | 24 | 29.17 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | | X0Y7 | 8 | 24 | 33.33 | 11 | 24 | 45.83 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X1Y7 | 7 | 24 | 29.17 | 12 | 24 | 50.00 | 1 | 24 | 4.17 | 3 | 24 | 12.50 | | X2Y7 | 0 | 24 | 0.00 | 24 | 24 | 100.00 | 0 | 24 | 0.00 | 6 | 24 | 25.00 | | X3Y7 | 0 | 24 | 0.00 | 12 | 24 | 50.00 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X4Y7 | 4 | 24 | 16.67 | 24 | 24 | 100.00 | 1 | 24 | 4.17 | 5 | 24 | 20.83 | | X5Y7 | 8 | 24 | 33.33 | 11 | 24 | 45.83 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | | X0Y8 | 8 | 24 | 33.33 | 9 | 24 | 37.50 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X1Y8 | 8 | 24 | 33.33 | 12 | 24 | 50.00 | 1 | 24 | 4.17 | 5 | 24 | 20.83 | | X2Y8 | 0 | 24 | 0.00 | 25 | 24 | 104.17 | 0 | 24 | 0.00 | 6 | 24 | 25.00 | | X3Y8 | 0 | 24 | 0.00 | 13 | 24 | 54.17 | 0 | 24 | 0.00 | 1 | 24 | 4.17 | | X4Y8 | 4 | 24 | 16.67 | 24 | 24 | 100.00 | 1 | 24 | 4.17 | 5 | 24 | 20.83 | | X5Y8 | 8 | 24 | 33.33 | 10 | 24 | 41.67 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | | X0Y9 | 8 | 24 | 33.33 | 9 | 24 | 37.50 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | | X1Y9 | 7 | 24 | 29.17 | 11 | 24 | 45.83 | 1 | 24 | 4.17 | 3 | 24 | 12.50 | | X2Y9 | 0 | 24 | 0.00 | 23 | 24 | 95.83 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | | X3Y9 | 0 | 24 | 0.00 | 12 | 24 | 50.00 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | | X4Y9 | 5 | 24 | 20.83 | 20 | 24 | 83.33 | 1 | 24 | 4.17 | 3 | 24 | 12.50 | | X5Y9 | 8 | 24 | 33.33 | 10 | 24 | 41.67 | 0 | 24 | 0.00 | 0 | 24 | 0.00 | +-------------------+------+-------+-------+------+-------+--------+------+-------+-------+------+-------+-------+ 8. Device Cell Placement Summary for Global Clock g0 ---------------------------------------------------- +-----------+-----------------+-------------------+---------+-------------+----------------+----------+-------------+----------+----------------+----------+-----+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+---------+-------------+----------------+----------+-------------+----------+----------------+----------+-----+ | g0 | BUFGCE/O | X2Y4 | ipb_clk | 32.000 | {0.000 16.000} | X2Y4 | 202733 | 0 | 0 | 0 | CLK | +-----------+-----------------+-------------------+---------+-------------+----------------+----------+-------------+----------+----------------+----------+-----+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+-------+-------+--------------+-------+-------+-------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+-------+-------+--------------+-------+-------+-------+-----------------------+ | Y9 | 1000 | 2802 | 2641 | 2693 | 2330 | 1377 | 0 | | Y8 | 1973 | 3827 | 2382 | 4304 | 3029 | 2831 | 1 | | Y7 | 2451 | 2964 | 3598 | 2633 | 3443 | 3294 | 2 | | Y6 | 2704 | 4117 | 4171 | 4406 | 3584 | 2566 | 3 | | Y5 | 2027 | 3775 | 3887 | 1905 | 4104 | 3625 | 4 | | Y4 | 2850 | 2943 | (R) (D) 3834 | 4500 | 3921 | 439 | 4 | | Y3 | 3812 | 4779 | 4273 | 4138 | 4054 | 3023 | 3 | | Y2 | 3603 | 3930 | 3021 | 2746 | 3058 | 3824 | 2 | | Y1 | 4314 | 5473 | 4084 | 4015 | 4030 | 3461 | 1 | | Y0 | 4343 | 4749 | 3734 | 5141 | 3864 | 2334 | 0 | +----+-------+-------+--------------+-------+-------+-------+-----------------------+ 9. Device Cell Placement Summary for Global Clock g1 ---------------------------------------------------- +-----------+-----------------+-------------------+------------+-------------+----------------+----------+-------------+----------+----------------+----------+------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------+-------------+----------------+----------+-------------+----------+----------------+----------+------------+ | g1 | BUFGCE/O | X4Y4 | fabric_clk | 24.952 | {0.000 12.476} | X2Y4 | 103755 | 0 | 0 | 0 | fabric_clk | +-----------+-----------------+-------------------+------------+-------------+----------------+----------+-------------+----------+----------------+----------+------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+-------+-------+---------+-------+----------+-------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+-------+-------+---------+-------+----------+-------+-----------------------+ | Y9 | 522 | 1369 | 989 | 1942 | 1175 | 589 | 0 | | Y8 | 1080 | 1673 | 1763 | 1933 | 1452 | 1715 | 1 | | Y7 | 1421 | 1658 | 2008 | 2161 | 1816 | 1941 | 2 | | Y6 | 1541 | 2004 | 1999 | 2408 | 2448 | 1568 | 3 | | Y5 | 1563 | 2049 | 1960 | 2434 | 1573 | 1769 | 4 | | Y4 | 2071 | 2098 | (R) 968 | 721 | (D) 525 | 359 | 4 | | Y3 | 2201 | 2292 | 1098 | 1940 | 906 | 1635 | 3 | | Y2 | 2219 | 2593 | 1769 | 1543 | 1966 | 2339 | 2 | | Y1 | 2176 | 1895 | 1948 | 1161 | 2414 | 2256 | 1 | | Y0 | 1935 | 2253 | 2522 | 2027 | 2349 | 1053 | 0 | +----+-------+-------+---------+-------+----------+-------+-----------------------+ 10. Device Cell Placement Summary for Global Clock g2 ----------------------------------------------------- +-----------+-----------------+-------------------+------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------+ | g2 | BUFGCE/O | X4Y4 | tx_wordclk | 8.317 | {0.000 4.159} | X2Y4 | 27295 | 0 | 0 | 48 | tx_wordclk | +-----------+-----------------+-------------------+------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+-------+------+--------+-------+--------+-------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+-------+------+--------+-------+--------+-------+-----------------------+ | Y9 | 1103 | 6 | 5 | 194 | 6 | 1174 | 0 | | Y8 | 1462 | 4 | 251 | 33 | 32 | 1346 | 1 | | Y7 | 1870 | 80 | 18 | 17 | 10 | 1439 | 2 | | Y6 | 146 | 9 | 230 | 15 | 12 | 1122 | 3 | | Y5 | 452 | 0 | 226 | 2036 | 0 | 0 | 4 | | Y4 | 1708 | 532 | (R) 16 | 15 | (D) 0 | 294 | 4 | | Y3 | 1467 | 229 | 15 | 48 | 15 | 1637 | 3 | | Y2 | 1646 | 270 | 112 | 324 | 484 | 1393 | 2 | | Y1 | 549 | 0 | 325 | 22 | 431 | 1866 | 1 | | Y0 | 0 | 0 | 366 | 0 | 273 | 8 | 0 | +----+-------+------+--------+-------+--------+-------+-----------------------+ 11. Device Cell Placement Summary for Global Clock g3 ----------------------------------------------------- +-----------+-----------------+-------------------+--------+-------------+---------------+----------+-------------+----------+----------------+----------+--------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+--------+-------------+---------------+----------+-------------+----------+----------------+----------+--------+ | g3 | BUFGCE/O | X2Y4 | clk250 | 4.000 | {0.000 2.000} | X3Y3 | 14619 | 0 | 0 | 0 | clk250 | +-----------+-----------------+-------------------+--------+-------------+---------------+----------+-------------+----------+----------------+----------+--------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+-----------+----------+-------+------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+------+-----------+----------+-------+------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 8 | 16 | 0 | 0 | 1 | | Y4 | 0 | 122 | (D) 1160 | 2559 | 3180 | 326 | 2 | | Y3 | 0 | 50 | 674 | (R) 1784 | 1518 | 85 | 2 | | Y2 | 0 | 142 | 769 | 733 | 790 | 0 | 1 | | Y1 | 0 | 2 | 118 | 89 | 494 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+------+-----------+----------+-------+------+-----------------------+ 12. Device Cell Placement Summary for Global Clock g4 ----------------------------------------------------- +-----------+-----------------+-------------------+--------+-------------+----------------+----------+-------------+----------+----------------+----------+--------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+--------+-------------+----------------+----------+-------------+----------+----------------+----------+--------+ | g4 | BUFGCE/O | X2Y4 | DRPclk | 20.000 | {0.000 10.000} | X3Y4 | 3888 | 0 | 0 | 0 | DRPclk | +-----------+-----------------+-------------------+--------+-------------+----------------+----------+-------------+----------+----------------+----------+--------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+---------+-------+------+------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+------+---------+-------+------+------+-----------------------+ | Y9 | 0 | 117 | 63 | 0 | 39 | 161 | 0 | | Y8 | 0 | 114 | 193 | 33 | 305 | 59 | 1 | | Y7 | 0 | 348 | 83 | 137 | 185 | 0 | 2 | | Y6 | 0 | 54 | 0 | 53 | 0 | 0 | 3 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 290 | (D) 34 | (R) 0 | 0 | 2 | 4 | | Y3 | 0 | 211 | 84 | 1 | 134 | 108 | 3 | | Y2 | 0 | 274 | 51 | 94 | 303 | 0 | 2 | | Y1 | 0 | 0 | 221 | 97 | 34 | 0 | 1 | | Y0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | +----+----+------+---------+-------+------+------+-----------------------+ 13. Device Cell Placement Summary for Global Clock g5 ----------------------------------------------------- +-----------+-----------------+-------------------+--------+-------------+---------------+----------+-------------+----------+----------------+----------+---------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+--------+-------------+---------------+----------+-------------+----------+----------------+----------+---------+ | g5 | BUFGCE/O | X2Y4 | clk125 | 8.000 | {0.000 4.000} | X3Y4 | 3801 | 0 | 1 | 1 | CLKFBIN | +-----------+-----------------+-------------------+--------+-------------+---------------+----------+-------------+----------+----------------+----------+---------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+--------+-------+----+-------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+--------+-------+----+-------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | (D) 2 | (R) 7 | 2 | 2341 | 4 | | Y3 | 0 | 0 | 0 | 0 | 0 | 617 | 3 | | Y2 | 0 | 0 | 0 | 0 | 0 | 1 | 2 | | Y1 | 0 | 0 | 0 | 0 | 1 | 20 | 1 | | Y0 | 0 | 0 | 0 | 0 | 0 | 812 | 0 | +----+----+----+--------+-------+----+-------+-----------------------+ 14. Device Cell Placement Summary for Global Clock g6 ----------------------------------------------------- +-----------+-----------------+-------------------+--------------+-------------+---------------+-----------+-------------+----------+----------------+----------+------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+--------------+-------------+---------------+-----------+-------------+----------+----------------+----------+------------------------------------------------------------+ | g6 | BUFG_GT/O | X5Y0 | TTC_rxusrclk | 3.119 | {0.000 1.559} | X3Y2,X5Y0 | 1858 | 0 | 1 | 1 | i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] | +-----------+-----------------+-------------------+--------------+-------------+---------------+-----------+-------------+----------+----------------+----------+------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+-------+-----+--------------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+-------+-----+--------------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 5 | 0 | 0 | 0 | 2 | | Y2 | 0 | 0 | 0 | (R) 1 | 0 | 0 | 2 | | Y1 | 0 | 0 | 0 | 0 | 5 | 44 | 1 | | Y0 | 0 | 0 | 0 | 0 | 17 | (R) (D) 1787 | 0 | +----+----+----+----+-------+-----+--------------+-----------------------+ 15. Device Cell Placement Summary for Global Clock g7 ----------------------------------------------------- +-----------+-----------------+-------------------+---------------+-------------+----------------+----------+-------------+----------+----------------+----------+--------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+---------------+-------------+----------------+----------+-------------+----------+----------------+----------+--------------------------+ | g7 | BUFGCE_DIV/O | X2Y4 | fabric_clk_in | 24.952 | {0.000 12.476} | X4Y2 | 791 | 0 | 1 | 0 | i_tcds2_if/fabric_clk_in | +-----------+-----------------+-------------------+---------------+-------------+----------------+----------+-------------+----------+----------------+----------+--------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+--------+----+-------+------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+--------+----+-------+------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | (D) 0 | 0 | 13 | 0 | 1 | | Y3 | 0 | 0 | 0 | 4 | 0 | 0 | 2 | | Y2 | 0 | 0 | 0 | 0 | (R) 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 6 | 1 | | Y0 | 0 | 0 | 0 | 0 | 0 | 769 | 0 | +----+----+----+--------+----+-------+------+-----------------------+ 16. Device Cell Placement Summary for Global Clock g8 ----------------------------------------------------- +-----------+-----------------+-------------------+--------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+--------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g8 | BUFG_GT/O | X5Y1 | gtwiz_userclk_rx_srcclk_out[0] | 8.317 | {0.000 4.159} | X3Y0 | 672 | 0 | 0 | 1 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+--------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+-----+--------+----+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+-----+--------+----+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 32 | 584 | 0 | (D) 8 | 0 | | Y0 | 0 | 0 | 11 | (R) 38 | 0 | 0 | 0 | +----+----+----+-----+--------+----+--------+-----------------------+ 17. Device Cell Placement Summary for Global Clock g9 ----------------------------------------------------- +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g9 | BUFG_GT/O | X5Y3 | gtwiz_userclk_rx_srcclk_out[0]_1 | 8.317 | {0.000 4.159} | X4Y3 | 672 | 0 | 0 | 1 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+-----+---------+----------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+-----+---------+----------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 26 | (R) 525 | (D) 122 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+-----+---------+----------+-----------------------+ 18. Device Cell Placement Summary for Global Clock g10 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g10 | BUFG_GT/O | X5Y3 | gtwiz_userclk_rx_srcclk_out[0]_2 | 8.317 | {0.000 4.159} | X4Y3 | 672 | 0 | 0 | 1 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+----+---------+----------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+----+---------+----------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 8 | 81 | 110 | 0 | | Y3 | 0 | 0 | 0 | 1 | (R) 252 | (D) 221 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+----+---------+----------+-----------------------+ 19. Device Cell Placement Summary for Global Clock g11 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g11 | BUFG_GT/O | X5Y1 | gtwiz_userclk_rx_srcclk_out[0]_3 | 8.317 | {0.000 4.159} | X3Y0 | 672 | 0 | 0 | 1 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+-----+-------+----+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+-----+-------+----+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 10 | 638 | 0 | (D) 8 | 0 | | Y0 | 0 | 0 | 17 | (R) 0 | 0 | 0 | 0 | +----+----+----+-----+-------+----+--------+-----------------------+ 20. Device Cell Placement Summary for Global Clock g12 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g12 | BUFG_GT/O | X5Y1 | gtwiz_userclk_rx_srcclk_out[0]_4 | 8.317 | {0.000 4.159} | X3Y0 | 672 | 0 | 0 | 1 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+-----+-------+----+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+-----+-------+----+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 16 | 632 | 0 | (D) 8 | 0 | | Y0 | 0 | 0 | 17 | (R) 0 | 0 | 0 | 0 | +----+----+----+-----+-------+----+--------+-----------------------+ 21. Device Cell Placement Summary for Global Clock g13 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g13 | BUFG_GT/O | X5Y1 | gtwiz_userclk_rx_srcclk_out[0]_5 | 8.317 | {0.000 4.159} | X3Y1 | 672 | 0 | 0 | 1 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+-----+---------+----+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+-----+---------+----+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 79 | (R) 586 | 0 | (D) 8 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+-----+---------+----+--------+-----------------------+ 22. Device Cell Placement Summary for Global Clock g14 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g14 | BUFG_GT/O | X5Y2 | gtwiz_userclk_rx_srcclk_out[0]_6 | 8.317 | {0.000 4.159} | X4Y2 | 672 | 0 | 0 | 1 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+------+-------+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+------+-------+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 665 | (R) 0 | (D) 8 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+------+-------+--------+-----------------------+ 23. Device Cell Placement Summary for Global Clock g15 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g15 | BUFG_GT/O | X5Y2 | gtwiz_userclk_rx_srcclk_out[0]_7 | 8.317 | {0.000 4.159} | X4Y2 | 672 | 0 | 0 | 1 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+------+-------+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+------+-------+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 665 | (R) 0 | (D) 8 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+------+-------+--------+-----------------------+ 24. Device Cell Placement Summary for Global Clock g16 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g16 | BUFG_GT/O | X5Y2 | gtwiz_userclk_rx_srcclk_out[0]_8 | 8.317 | {0.000 4.159} | X4Y2 | 672 | 0 | 0 | 1 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+-----+---------+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+-----+---------+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 70 | (R) 595 | (D) 8 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+-----+---------+--------+-----------------------+ 25. Device Cell Placement Summary for Global Clock g17 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g17 | BUFG_GT/O | X5Y2 | gtwiz_userclk_rx_srcclk_out[0]_9 | 8.317 | {0.000 4.159} | X4Y2 | 672 | 0 | 0 | 1 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+------+-------+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+------+-------+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 665 | (R) 0 | (D) 8 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+------+-------+--------+-----------------------+ 26. Device Cell Placement Summary for Global Clock g18 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g18 | BUFG_GT/O | X5Y3 | gtwiz_userclk_rx_srcclk_out[0]_10 | 8.317 | {0.000 4.159} | X4Y3 | 672 | 0 | 0 | 1 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+----+---------+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+----+---------+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 7 | (R) 658 | (D) 8 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+----+---------+--------+-----------------------+ 27. Device Cell Placement Summary for Global Clock g19 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g19 | BUFG_GT/O | X5Y3 | gtwiz_userclk_rx_srcclk_out[0]_11 | 8.317 | {0.000 4.159} | X4Y3 | 672 | 0 | 0 | 1 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+----+---------+----------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+----+---------+----------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 7 | (R) 439 | (D) 227 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+----+---------+----------+-----------------------+ 28. Device Cell Placement Summary for Global Clock g20 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g20 | BUFG_GT/O | X5Y7 | gtwiz_userclk_rx_srcclk_out[0]_12 | 8.317 | {0.000 4.159} | X4Y7 | 672 | 0 | 0 | 1 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+------+-------+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+------+-------+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 665 | (R) 0 | (D) 8 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+------+-------+--------+-----------------------+ 29. Device Cell Placement Summary for Global Clock g21 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g21 | BUFG_GT/O | X5Y9 | gtwiz_userclk_rx_srcclk_out[0]_13 | 8.317 | {0.000 4.159} | X4Y9 | 672 | 0 | 0 | 1 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+-----+--------+----------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+-----+--------+----------+-----------------------+ | Y9 | 0 | 0 | 0 | 29 | (R) 75 | (D) 569 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+-----+--------+----------+-----------------------+ 30. Device Cell Placement Summary for Global Clock g22 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g22 | BUFG_GT/O | X5Y9 | gtwiz_userclk_rx_srcclk_out[0]_14 | 8.317 | {0.000 4.159} | X4Y9 | 672 | 0 | 0 | 1 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+-----+---------+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+-----+---------+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 40 | (R) 630 | (D) 3 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+-----+---------+--------+-----------------------+ 31. Device Cell Placement Summary for Global Clock g23 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g23 | BUFG_GT/O | X5Y7 | gtwiz_userclk_rx_srcclk_out[0]_15 | 8.317 | {0.000 4.159} | X4Y7 | 672 | 0 | 0 | 1 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+------+-------+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+------+-------+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 660 | (R) 5 | (D) 8 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+------+-------+--------+-----------------------+ 32. Device Cell Placement Summary for Global Clock g24 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g24 | BUFG_GT/O | X5Y7 | gtwiz_userclk_rx_srcclk_out[0]_16 | 8.317 | {0.000 4.159} | X4Y7 | 672 | 0 | 0 | 1 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+------+-------+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+------+-------+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 665 | (R) 0 | (D) 8 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+------+-------+--------+-----------------------+ 33. Device Cell Placement Summary for Global Clock g25 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g25 | BUFG_GT/O | X5Y7 | gtwiz_userclk_rx_srcclk_out[0]_17 | 8.317 | {0.000 4.159} | X4Y7 | 672 | 0 | 0 | 1 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+-----+---------+---------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+-----+---------+---------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 28 | (R) 620 | (D) 25 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+-----+---------+---------+-----------------------+ 34. Device Cell Placement Summary for Global Clock g26 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g26 | BUFG_GT/O | X5Y8 | gtwiz_userclk_rx_srcclk_out[0]_18 | 8.317 | {0.000 4.159} | X4Y8 | 672 | 0 | 0 | 1 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+------+-------+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+------+-------+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 662 | (R) 3 | (D) 8 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+------+-------+--------+-----------------------+ 35. Device Cell Placement Summary for Global Clock g27 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g27 | BUFG_GT/O | X5Y8 | gtwiz_userclk_rx_srcclk_out[0]_19 | 8.317 | {0.000 4.159} | X4Y8 | 672 | 0 | 0 | 1 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+-----+---------+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+-----+---------+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 49 | (R) 616 | (D) 8 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+-----+---------+--------+-----------------------+ 36. Device Cell Placement Summary for Global Clock g28 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g28 | BUFG_GT/O | X5Y8 | gtwiz_userclk_rx_srcclk_out[0]_20 | 8.317 | {0.000 4.159} | X4Y8 | 672 | 0 | 0 | 1 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+-----+---------+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+-----+---------+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 47 | (R) 618 | (D) 8 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+-----+---------+--------+-----------------------+ 37. Device Cell Placement Summary for Global Clock g29 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g29 | BUFG_GT/O | X5Y8 | gtwiz_userclk_rx_srcclk_out[0]_21 | 8.317 | {0.000 4.159} | X4Y8 | 672 | 0 | 0 | 1 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+-----+--------+----------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+-----+--------+----------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 28 | (R) 45 | (D) 600 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+-----+--------+----------+-----------------------+ 38. Device Cell Placement Summary for Global Clock g30 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g30 | BUFG_GT/O | X5Y9 | gtwiz_userclk_rx_srcclk_out[0]_22 | 8.317 | {0.000 4.159} | X4Y9 | 672 | 0 | 0 | 1 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+-----+---------+----------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+-----+---------+----------+-----------------------+ | Y9 | 0 | 0 | 0 | 29 | (R) 258 | (D) 386 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+-----+---------+----------+-----------------------+ 39. Device Cell Placement Summary for Global Clock g31 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g31 | BUFG_GT/O | X5Y9 | gtwiz_userclk_rx_srcclk_out[0]_23 | 8.317 | {0.000 4.159} | X4Y7 | 672 | 0 | 0 | 1 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+------+-------+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+------+-------+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 354 | 238 | (D) 8 | 1 | | Y8 | 0 | 0 | 0 | 52 | 20 | 0 | 2 | | Y7 | 0 | 0 | 0 | 0 | (R) 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+----+------+-------+--------+-----------------------+ 40. Device Cell Placement Summary for Global Clock g32 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g32 | BUFG_GT/O | X0Y2 | gtwiz_userclk_rx_srcclk_out[0]_24 | 8.317 | {0.000 4.159} | X1Y2 | 672 | 0 | 0 | 1 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+-------+------+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+-------+------+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | (D) 8 | (R) 7 | 658 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+-------+------+----+----+----+-----------------------+ 41. Device Cell Placement Summary for Global Clock g33 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g33 | BUFG_GT/O | X0Y4 | gtwiz_userclk_rx_srcclk_out[0]_25 | 8.317 | {0.000 4.159} | X1Y4 | 672 | 0 | 0 | 1 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+---------+-----+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+---------+-----+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | (D) 8 | (R) 637 | 28 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+---------+-----+----+----+----+-----------------------+ 42. Device Cell Placement Summary for Global Clock g34 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g34 | BUFG_GT/O | X0Y4 | gtwiz_userclk_rx_srcclk_out[0]_26 | 8.317 | {0.000 4.159} | X1Y4 | 672 | 0 | 0 | 1 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+-------+------+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+-------+------+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | (D) 8 | (R) 0 | 664 | 1 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+-------+------+----+----+----+-----------------------+ 43. Device Cell Placement Summary for Global Clock g35 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g35 | BUFG_GT/O | X0Y2 | gtwiz_userclk_rx_srcclk_out[0]_27 | 8.317 | {0.000 4.159} | X1Y2 | 672 | 0 | 0 | 1 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+-------+------+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+-------+------+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | (D) 3 | (R) 5 | 665 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+-------+------+----+----+----+-----------------------+ 44. Device Cell Placement Summary for Global Clock g36 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g36 | BUFG_GT/O | X0Y2 | gtwiz_userclk_rx_srcclk_out[0]_28 | 8.317 | {0.000 4.159} | X1Y2 | 672 | 0 | 0 | 1 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+---------+---------+-----+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+---------+---------+-----+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | (D) 32 | (R) 611 | 30 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+---------+---------+-----+----+----+----+-----------------------+ 45. Device Cell Placement Summary for Global Clock g37 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g37 | BUFG_GT/O | X0Y2 | gtwiz_userclk_rx_srcclk_out[0]_29 | 8.317 | {0.000 4.159} | X1Y2 | 672 | 0 | 0 | 1 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+-------+------+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+-------+------+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | (D) 8 | (R) 0 | 665 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+-------+------+----+----+----+-----------------------+ 46. Device Cell Placement Summary for Global Clock g38 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g38 | BUFG_GT/O | X0Y3 | gtwiz_userclk_rx_srcclk_out[0]_30 | 8.317 | {0.000 4.159} | X1Y3 | 672 | 0 | 0 | 1 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+-------+------+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+-------+------+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | (D) 8 | (R) 0 | 665 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+-------+------+----+----+----+-----------------------+ 47. Device Cell Placement Summary for Global Clock g39 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g39 | BUFG_GT/O | X0Y3 | gtwiz_userclk_rx_srcclk_out[0]_31 | 8.317 | {0.000 4.159} | X1Y3 | 672 | 0 | 0 | 1 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+-------+------+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+-------+------+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | (D) 8 | (R) 0 | 665 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+-------+------+----+----+----+-----------------------+ 48. Device Cell Placement Summary for Global Clock g40 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g40 | BUFG_GT/O | X0Y3 | gtwiz_userclk_rx_srcclk_out[0]_32 | 8.317 | {0.000 4.159} | X1Y3 | 672 | 0 | 0 | 1 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+---------+---------+-----+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+---------+---------+-----+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | (D) 60 | (R) 584 | 29 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+---------+---------+-----+----+----+----+-----------------------+ 49. Device Cell Placement Summary for Global Clock g41 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g41 | BUFG_GT/O | X0Y3 | gtwiz_userclk_rx_srcclk_out[0]_33 | 8.317 | {0.000 4.159} | X1Y3 | 672 | 0 | 0 | 1 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+-------+------+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+-------+------+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | (D) 8 | (R) 0 | 665 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+-------+------+----+----+----+-----------------------+ 50. Device Cell Placement Summary for Global Clock g42 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g42 | BUFG_GT/O | X0Y4 | gtwiz_userclk_rx_srcclk_out[0]_34 | 8.317 | {0.000 4.159} | X1Y4 | 672 | 0 | 0 | 1 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----------+---------+-----+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----------+---------+-----+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | (D) 121 | (R) 524 | 27 | 1 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----------+---------+-----+----+----+----+-----------------------+ 51. Device Cell Placement Summary for Global Clock g43 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g43 | BUFG_GT/O | X0Y4 | gtwiz_userclk_rx_srcclk_out[0]_35 | 8.317 | {0.000 4.159} | X1Y4 | 672 | 0 | 0 | 1 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+-------+------+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+-------+------+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | (D) 8 | (R) 0 | 664 | 1 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+-------+------+----+----+----+-----------------------+ 52. Device Cell Placement Summary for Global Clock g44 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g44 | BUFG_GT/O | X0Y7 | gtwiz_userclk_rx_srcclk_out[0]_36 | 8.317 | {0.000 4.159} | X1Y7 | 672 | 0 | 0 | 1 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+---------+------+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+---------+------+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | (D) 8 | (R) 120 | 545 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+---------+------+----+----+----+-----------------------+ 53. Device Cell Placement Summary for Global Clock g45 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g45 | BUFG_GT/O | X0Y9 | gtwiz_userclk_rx_srcclk_out[0]_37 | 8.317 | {0.000 4.159} | X1Y8 | 672 | 0 | 0 | 1 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+-------+------+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+-------+------+----+----+----+-----------------------+ | Y9 | (D) 8 | 84 | 522 | 0 | 0 | 0 | 0 | | Y8 | 0 | (R) 0 | 59 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+-------+------+----+----+----+-----------------------+ 54. Device Cell Placement Summary for Global Clock g46 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g46 | BUFG_GT/O | X0Y9 | gtwiz_userclk_rx_srcclk_out[0]_38 | 8.317 | {0.000 4.159} | X1Y9 | 672 | 0 | 0 | 1 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+-------+------+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+-------+------+----+----+----+-----------------------+ | Y9 | (D) 8 | (R) 0 | 665 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+-------+------+----+----+----+-----------------------+ 55. Device Cell Placement Summary for Global Clock g47 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g47 | BUFG_GT/O | X0Y7 | gtwiz_userclk_rx_srcclk_out[0]_39 | 8.317 | {0.000 4.159} | X1Y7 | 672 | 0 | 0 | 1 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----------+---------+-----+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----------+---------+-----+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | (D) 130 | (R) 515 | 28 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----------+---------+-----+----+----+----+-----------------------+ 56. Device Cell Placement Summary for Global Clock g48 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g48 | BUFG_GT/O | X0Y7 | gtwiz_userclk_rx_srcclk_out[0]_40 | 8.317 | {0.000 4.159} | X1Y7 | 672 | 0 | 0 | 1 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+---------+-----+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+---------+-----+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | (D) 3 | (R) 642 | 28 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+---------+-----+----+----+----+-----------------------+ 57. Device Cell Placement Summary for Global Clock g49 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g49 | BUFG_GT/O | X0Y7 | gtwiz_userclk_rx_srcclk_out[0]_41 | 8.317 | {0.000 4.159} | X1Y6 | 672 | 0 | 0 | 1 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+-------+------+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+-------+------+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | (D) 8 | 504 | 132 | 0 | 0 | 0 | 0 | | Y6 | 0 | (R) 0 | 29 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+-------+------+----+----+----+-----------------------+ 58. Device Cell Placement Summary for Global Clock g50 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g50 | BUFG_GT/O | X0Y8 | gtwiz_userclk_rx_srcclk_out[0]_42 | 8.317 | {0.000 4.159} | X1Y8 | 672 | 0 | 0 | 1 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+-------+------+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+-------+------+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | (D) 8 | (R) 0 | 665 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+-------+------+----+----+----+-----------------------+ 59. Device Cell Placement Summary for Global Clock g51 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g51 | BUFG_GT/O | X0Y8 | gtwiz_userclk_rx_srcclk_out[0]_43 | 8.317 | {0.000 4.159} | X1Y8 | 672 | 0 | 0 | 1 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+---------+-----+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+---------+-----+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | (D) 8 | (R) 635 | 30 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+---------+-----+----+----+----+-----------------------+ 60. Device Cell Placement Summary for Global Clock g52 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g52 | BUFG_GT/O | X0Y8 | gtwiz_userclk_rx_srcclk_out[0]_44 | 8.317 | {0.000 4.159} | X1Y8 | 672 | 0 | 0 | 1 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+-------+------+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+-------+------+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | (D) 8 | (R) 0 | 665 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+-------+------+----+----+----+-----------------------+ 61. Device Cell Placement Summary for Global Clock g53 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g53 | BUFG_GT/O | X0Y8 | gtwiz_userclk_rx_srcclk_out[0]_45 | 8.317 | {0.000 4.159} | X1Y8 | 672 | 0 | 0 | 1 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+-------+------+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+-------+------+----+----+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | (D) 8 | (R) 0 | 665 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+-------+------+----+----+----+-----------------------+ 62. Device Cell Placement Summary for Global Clock g54 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g54 | BUFG_GT/O | X0Y9 | gtwiz_userclk_rx_srcclk_out[0]_46 | 8.317 | {0.000 4.159} | X1Y9 | 672 | 0 | 0 | 1 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+-------+------+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+-------+------+----+----+----+-----------------------+ | Y9 | (D) 8 | (R) 0 | 665 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+-------+------+----+----+----+-----------------------+ 63. Device Cell Placement Summary for Global Clock g55 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g55 | BUFG_GT/O | X0Y9 | gtwiz_userclk_rx_srcclk_out[0]_47 | 8.317 | {0.000 4.159} | X1Y9 | 672 | 0 | 0 | 1 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | +-----------+-----------------+-------------------+-----------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+---------+-----+----+----+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+--------+---------+-----+----+----+----+-----------------------+ | Y9 | (D) 3 | (R) 641 | 29 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+--------+---------+-----+----+----+----+-----------------------+ 64. Device Cell Placement Summary for Global Clock g56 ------------------------------------------------------ +-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------+ | g56 | BUFG_GT/O | X5Y0 | txoutclk_out[0]_49 | 3.119 | {0.000 1.559} | X5Y0 | 537 | 0 | 0 | 1 | i_tcds2_if/i_mgt_wrapper/i_txusrclk/bbstub_txoutclk_out[0] | +-----------+-----------------+-------------------+--------------------+-------------+---------------+----------+-------------+----------+----------------+----------+------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+----+----+----+-------------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+----+----+----+-------------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 16 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | (R) (D) 522 | 0 | +----+----+----+----+----+----+-------------+-----------------------+ 65. Device Cell Placement Summary for Global Clock g57 ------------------------------------------------------ +-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------+ | g57 | BUFGCE/O | X2Y4 | clk62_5_dcm | 16.000 | {0.000 8.000} | X5Y0 | 65 | 0 | 0 | 1 | clk62_5 | +-----------+-----------------+-------------------+-------------+-------------+---------------+----------+-------------+----------+----------------+----------+---------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+--------+----+----+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+--------+----+----+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | (D) 0 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | (R) 66 | 0 | +----+----+----+--------+----+----+--------+-----------------------+ 66. Device Cell Placement Summary for Global Clock g58 ------------------------------------------------------ +-----------+-----------------+-------------------+----------+-------------+----------------+----------+-------------+----------+----------------+----------+-------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------+-------------+----------------+----------+-------------+----------+----------------+----------+-------------------+ | g58 | BUFGCE/O | X4Y4 | CLKFBOUT | 24.952 | {6.238 18.714} | X2Y4 | 0 | 0 | 1 | 0 | CLKFBOUT_bufg_n_0 | +-----------+-----------------+-------------------+----------+-------------+----------------+----------+-------------+----------+----------------+----------+-------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+-------+----+--------+----+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+-------+----+--------+----+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | (R) 0 | 0 | (D) 1 | 0 | 4 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +----+----+----+-------+----+--------+----+-----------------------+ 67. Device Cell Placement Summary for Global Clock g59 ------------------------------------------------------ +-----------+-----------------+-------------------+-----------+-------------+---------------+----------+-------------+----------+----------------+----------+--------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------+-------------+---------------+----------+-------------+----------+----------------+----------+--------+ | g59 | BUFG_GT/O | X5Y0 | refclk125 | 8.000 | {0.000 4.000} | X2Y4 | 0 | 0 | 1 | 0 | CLKIN1 | +-----------+-----------------+-------------------+-----------+-------------+---------------+----------+-------------+----------+----------------+----------+--------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+-------+----+----+--------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+----+----+-------+----+----+--------+-----------------------+ | Y9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y4 | 0 | 0 | (R) 1 | 0 | 0 | 0 | 0 | | Y3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Y0 | 0 | 0 | 0 | 0 | 0 | (D) 0 | 0 | +----+----+----+-------+----+----+--------+-----------------------+ 68. Device Cell Placement Summary for Global Clock g60 ------------------------------------------------------ +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------------------------------+ | g60 | BUFGCE/O | X2Y6 | | | | X2Y6 | 1392 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+-----+-----+------------+------+-----+------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+-----+-----+------------+------+-----+------+-----------------------+ | Y9 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | | Y8 | 0 | 0 | 29 | 2 | 0 | 0 | 0 | | Y7 | 54 | 15 | 0 | 0 | 0 | 29 | 0 | | Y6 | 17 | 1 | (R) (D) 29 | 14 | 11 | 104 | 0 | | Y5 | 58 | 0 | 32 | 244 | 0 | 1 | 0 | | Y4 | 54 | 58 | 0 | 0 | 4 | 25 | 0 | | Y3 | 33 | 25 | 0 | 8 | 0 | 58 | 0 | | Y2 | 49 | 40 | 25 | 25 | 58 | 25 | 0 | | Y1 | 31 | 0 | 33 | 0 | 45 | 33 | 0 | | Y0 | 0 | 0 | 54 | 0 | 42 | 0 | 0 | +----+-----+-----+------------+------+-----+------+-----------------------+ 69. Device Cell Placement Summary for Global Clock g61 ------------------------------------------------------ +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------------------------------------------+ | g61 | BUFGCE/O | X0Y5 | | | | X0Y5 | 8853 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+------------+------+------+------+------+------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+------------+------+------+------+------+------+-----------------------+ | Y9 | 33 | 147 | 121 | 126 | 117 | 44 | 0 | | Y8 | 91 | 196 | 78 | 230 | 136 | 142 | 0 | | Y7 | 90 | 171 | 163 | 89 | 149 | 166 | 0 | | Y6 | 126 | 166 | 202 | 206 | 144 | 140 | 0 | | Y5 | (R) (D) 60 | 209 | 182 | 71 | 209 | 182 | 0 | | Y4 | 136 | 116 | 133 | 95 | 11 | 0 | 0 | | Y3 | 162 | 245 | 136 | 79 | 184 | 153 | 0 | | Y2 | 140 | 169 | 140 | 93 | 150 | 172 | 0 | | Y1 | 198 | 272 | 192 | 209 | 226 | 138 | 0 | | Y0 | 217 | 181 | 167 | 296 | 140 | 117 | 0 | +----+------------+------+------+------+------+------+-----------------------+ 70. Device Cell Placement Summary for Global Clock g62 ------------------------------------------------------ +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------+ | g62 | BUFGCE/O | X2Y6 | | | | X2Y6 | 5252 | 0 | 0 | 0 | fabric_clk_div2 | +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+------+------+-------------+------+------+------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+------+------+-------------+------+------+------+-----------------------+ | Y9 | 0 | 2 | 4 | 79 | 0 | 0 | 0 | | Y8 | 0 | 2 | 108 | 36 | 6 | 0 | 0 | | Y7 | 164 | 98 | 9 | 17 | 6 | 104 | 0 | | Y6 | 53 | 10 | (R) (D) 109 | 88 | 86 | 340 | 0 | | Y5 | 188 | 26 | 111 | 878 | 0 | 3 | 0 | | Y4 | 194 | 262 | 14 | 12 | 21 | 128 | 0 | | Y3 | 100 | 128 | 23 | 59 | 56 | 201 | 0 | | Y2 | 159 | 127 | 113 | 108 | 212 | 90 | 0 | | Y1 | 91 | 0 | 113 | 1 | 136 | 95 | 0 | | Y0 | 0 | 0 | 156 | 0 | 126 | 0 | 0 | +----+------+------+-------------+------+------+------+-----------------------+ 71. Device Cell Placement Summary for Global Clock g63 ------------------------------------------------------ +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------+ | g63 | BUFGCE/O | X2Y4 | | | | X2Y4 | 157668 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+--------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+-------+-------+--------------+-------+-------+-------+-----------------------+ | | X0 | X1 | X2 | X3 | X4 | X5 | HORIZONTAL PROG DELAY | +----+-------+-------+--------------+-------+-------+-------+-----------------------+ | Y9 | 786 | 2287 | 2160 | 2199 | 1882 | 1132 | 0 | | Y8 | 1599 | 3130 | 1962 | 3539 | 2459 | 2281 | 0 | | Y7 | 1999 | 2445 | 2910 | 2086 | 2798 | 2644 | 0 | | Y6 | 2200 | 3343 | 3560 | 3604 | 2942 | 2094 | 0 | | Y5 | 1647 | 3104 | 3133 | 1409 | 3361 | 2939 | 0 | | Y4 | 2321 | 2407 | (R) (D) 2510 | 1594 | 748 | 103 | 0 | | Y3 | 3073 | 3889 | 3796 | 2485 | 2642 | 2433 | 0 | | Y2 | 2917 | 3217 | 2491 | 2121 | 2456 | 3104 | 0 | | Y1 | 3424 | 4292 | 3326 | 3342 | 3267 | 2787 | 0 | | Y0 | 3529 | 3532 | 2998 | 4226 | 3134 | 1870 | 0 | +----+-------+-------+--------------+-------+-------+-------+-----------------------+ 72. Clock Region Cell Placement per Global Clock: Region X0Y0 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 4343 | 0 | 4301 | 0 | 42 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1935 | 0 | 1935 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g61 | 8 | BUFGCE/O | None | 0 | 217 | 217 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g63 | 20 | BUFGCE/O | None | 0 | 3529 | 3529 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 73. Clock Region Cell Placement per Global Clock: Region X1Y0 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 4749 | 0 | 4708 | 0 | 41 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2253 | 0 | 2253 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g61 | 8 | BUFGCE/O | None | 0 | 181 | 181 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g63 | 20 | BUFGCE/O | None | 0 | 3532 | 3532 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 74. Clock Region Cell Placement per Global Clock: Region X2Y0 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3734 | 0 | 3695 | 0 | 39 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2522 | 0 | 2520 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 366 | 0 | 366 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4 | 18 | BUFGCE/O | None | 6 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g8 | 19 | BUFG_GT/O | None | 11 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g11 | 21 | BUFG_GT/O | None | 17 | 0 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g12 | 17 | BUFG_GT/O | None | 17 | 0 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g59+ | 0 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKIN1 | | g60 | 6 | BUFGCE/O | None | 0 | 54 | 54 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 167 | 167 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 156 | 156 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2998 | 2998 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 75. Clock Region Cell Placement per Global Clock: Region X3Y0 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 5141 | 0 | 5098 | 0 | 43 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2027 | 0 | 2026 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2+ | 22 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4+ | 18 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g5+ | 12 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKFBIN | | g6+ | 1 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] | | g8 | 19 | BUFG_GT/O | None | 38 | 0 | 38 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g11+ | 21 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g12+ | 17 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g59+ | 0 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKIN1 | | g60+ | 6 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 296 | 296 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62+ | 14 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 4226 | 4226 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 76. Clock Region Cell Placement per Global Clock: Region X4Y0 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3864 | 0 | 3821 | 0 | 43 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2349 | 0 | 2349 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 273 | 0 | 273 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g5+ | 12 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKFBIN | | g6 | 1 | BUFG_GT/O | None | 17 | 0 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] | | g7+ | 11 | BUFGCE_DIV/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/fabric_clk_in | | g59+ | 0 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKIN1 | | g60 | 6 | BUFGCE/O | None | 0 | 42 | 42 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 140 | 140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 126 | 126 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3134 | 3134 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 77. Clock Region Cell Placement per Global Clock: Region X5Y0 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 2334 | 0 | 2303 | 1 | 30 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1053 | 0 | 1052 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 8 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g5 | 12 | BUFGCE/O | None | 812 | 0 | 803 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | CLKFBIN | | g6 | 1 | BUFG_GT/O | None | 1787 | 0 | 1786 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] | | g7 | 11 | BUFGCE_DIV/O | None | 769 | 0 | 769 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/fabric_clk_in | | g56 | 3 | BUFG_GT/O | None | 522 | 0 | 521 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | i_tcds2_if/i_mgt_wrapper/i_txusrclk/bbstub_txoutclk_out[0] | | g57 | 2 | BUFGCE/O | None | 66 | 0 | 65 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | clk62_5 | | g59+ | 0 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKIN1 | | g61 | 8 | BUFGCE/O | None | 0 | 117 | 117 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g63 | 20 | BUFGCE/O | None | 0 | 1870 | 1869 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 78. Clock Region Cell Placement per Global Clock: Region X0Y1 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 4314 | 0 | 4272 | 0 | 42 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2176 | 0 | 2175 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 549 | 0 | 548 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g60 | 6 | BUFGCE/O | None | 0 | 31 | 31 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 198 | 198 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 91 | 91 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3424 | 3424 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 79. Clock Region Cell Placement per Global Clock: Region X1Y1 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 5473 | 0 | 5430 | 0 | 43 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1895 | 0 | 1893 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2+ | 22 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | clk250 | | g60+ | 6 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 272 | 272 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62+ | 14 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 4292 | 4292 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 80. Clock Region Cell Placement per Global Clock: Region X2Y1 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 4084 | 0 | 4042 | 0 | 42 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1948 | 0 | 1948 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 325 | 0 | 325 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 118 | 0 | 84 | 0 | 0 | 34 | 0 | 0 | 0 | 0 | clk250 | | g4 | 18 | BUFGCE/O | None | 221 | 0 | 221 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g8 | 19 | BUFG_GT/O | None | 32 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g11 | 21 | BUFG_GT/O | None | 10 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g12 | 17 | BUFG_GT/O | None | 16 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g13 | 16 | BUFG_GT/O | None | 79 | 0 | 79 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g59+ | 0 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKIN1 | | g60 | 6 | BUFGCE/O | None | 0 | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 192 | 192 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 113 | 113 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3326 | 3326 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 81. Clock Region Cell Placement per Global Clock: Region X3Y1 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 4015 | 0 | 3974 | 0 | 41 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1161 | 0 | 1161 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 22 | 0 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 89 | 0 | 76 | 0 | 0 | 13 | 0 | 0 | 0 | 0 | clk250 | | g4 | 18 | BUFGCE/O | None | 97 | 0 | 97 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g5+ | 12 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKFBIN | | g6+ | 1 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] | | g8 | 19 | BUFG_GT/O | None | 584 | 0 | 584 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g11 | 21 | BUFG_GT/O | None | 638 | 0 | 638 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g12 | 17 | BUFG_GT/O | None | 632 | 0 | 632 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g13 | 16 | BUFG_GT/O | None | 586 | 0 | 586 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60+ | 6 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 209 | 209 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3342 | 3342 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 82. Clock Region Cell Placement per Global Clock: Region X4Y1 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 4030 | 0 | 3992 | 0 | 38 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2414 | 0 | 2412 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 431 | 0 | 431 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 494 | 0 | 445 | 0 | 0 | 49 | 0 | 0 | 0 | 0 | clk250 | | g4 | 18 | BUFGCE/O | None | 34 | 0 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g5 | 12 | BUFGCE/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKFBIN | | g6 | 1 | BUFG_GT/O | None | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] | | g7+ | 11 | BUFGCE_DIV/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/fabric_clk_in | | g8+ | 19 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g11+ | 21 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g12+ | 17 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g13+ | 16 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 45 | 45 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 226 | 226 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 136 | 136 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3267 | 3267 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 83. Clock Region Cell Placement per Global Clock: Region X5Y1 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3461 | 0 | 3420 | 0 | 41 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2256 | 0 | 2256 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 1866 | 0 | 1857 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | tx_wordclk | | g5 | 12 | BUFGCE/O | None | 20 | 0 | 11 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | CLKFBIN | | g6 | 1 | BUFG_GT/O | None | 44 | 0 | 44 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] | | g7 | 11 | BUFGCE_DIV/O | None | 6 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/fabric_clk_in | | g8 | 19 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g11 | 21 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g12 | 17 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g13 | 16 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g56 | 3 | BUFG_GT/O | None | 16 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/i_mgt_wrapper/i_txusrclk/bbstub_txoutclk_out[0] | | g57+ | 2 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk62_5 | | g60 | 6 | BUFGCE/O | None | 0 | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 138 | 138 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 95 | 95 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2787 | 2787 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 84. Clock Region Cell Placement per Global Clock: Region X0Y2 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3603 | 0 | 3563 | 0 | 40 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2219 | 0 | 2217 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 1646 | 0 | 1638 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | tx_wordclk | | g32 | 19 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g35 | 21 | BUFG_GT/O | None | 3 | 0 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g36 | 16 | BUFG_GT/O | None | 32 | 0 | 31 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g37 | 17 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 49 | 49 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 140 | 140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 159 | 159 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2917 | 2917 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 85. Clock Region Cell Placement per Global Clock: Region X1Y2 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3930 | 0 | 3889 | 0 | 41 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2593 | 0 | 2592 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 270 | 0 | 270 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 142 | 0 | 122 | 0 | 0 | 20 | 0 | 0 | 0 | 0 | clk250 | | g4 | 18 | BUFGCE/O | None | 274 | 0 | 274 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g32 | 19 | BUFG_GT/O | None | 7 | 0 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g35 | 21 | BUFG_GT/O | None | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g36 | 16 | BUFG_GT/O | None | 611 | 0 | 611 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g37+ | 17 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 40 | 40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 169 | 169 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 127 | 127 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3217 | 3217 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 86. Clock Region Cell Placement per Global Clock: Region X2Y2 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3021 | 0 | 2980 | 0 | 41 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1769 | 0 | 1768 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 112 | 0 | 112 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 769 | 0 | 670 | 0 | 0 | 99 | 0 | 0 | 0 | 0 | clk250 | | g4 | 18 | BUFGCE/O | None | 51 | 0 | 51 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g32 | 19 | BUFG_GT/O | None | 658 | 0 | 658 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g35 | 21 | BUFG_GT/O | None | 665 | 0 | 665 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g36 | 16 | BUFG_GT/O | None | 30 | 0 | 30 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g37 | 17 | BUFG_GT/O | None | 665 | 0 | 665 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g59+ | 0 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKIN1 | | g60 | 6 | BUFGCE/O | None | 0 | 25 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 140 | 140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 113 | 113 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2491 | 2491 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 87. Clock Region Cell Placement per Global Clock: Region X3Y2 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 2746 | 0 | 2706 | 0 | 40 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1543 | 0 | 1543 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 324 | 0 | 324 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 733 | 0 | 676 | 0 | 0 | 57 | 0 | 0 | 0 | 0 | clk250 | | g4 | 18 | BUFGCE/O | None | 94 | 0 | 94 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g5+ | 12 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKFBIN | | g6 | 1 | BUFG_GT/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] | | g14 | 17 | BUFG_GT/O | None | 665 | 0 | 665 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g15 | 21 | BUFG_GT/O | None | 665 | 0 | 665 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g16 | 16 | BUFG_GT/O | None | 70 | 0 | 70 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g17 | 19 | BUFG_GT/O | None | 665 | 0 | 665 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 25 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 93 | 93 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 108 | 108 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2121 | 2121 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 88. Clock Region Cell Placement per Global Clock: Region X4Y2 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3058 | 0 | 3023 | 0 | 35 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1966 | 0 | 1965 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 484 | 0 | 484 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 790 | 0 | 720 | 0 | 0 | 70 | 0 | 0 | 0 | 0 | clk250 | | g4 | 18 | BUFGCE/O | None | 303 | 0 | 303 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g5+ | 12 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKFBIN | | g7+ | 11 | BUFGCE_DIV/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/fabric_clk_in | | g14+ | 17 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g15+ | 21 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g16 | 16 | BUFG_GT/O | None | 595 | 0 | 595 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g17+ | 19 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 150 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 212 | 212 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2456 | 2456 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 89. Clock Region Cell Placement per Global Clock: Region X5Y2 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3824 | 0 | 3787 | 0 | 37 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2339 | 0 | 2337 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 1393 | 0 | 1385 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | tx_wordclk | | g5 | 12 | BUFGCE/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKFBIN | | g14 | 17 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g15 | 21 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g16 | 16 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g17 | 19 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g57+ | 2 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk62_5 | | g60 | 6 | BUFGCE/O | None | 0 | 25 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 172 | 172 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 90 | 90 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3104 | 3104 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 90. Clock Region Cell Placement per Global Clock: Region X0Y3 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3812 | 0 | 3773 | 0 | 39 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2201 | 0 | 2200 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 1467 | 0 | 1459 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | tx_wordclk | | g38 | 21 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g39 | 19 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g40 | 16 | BUFG_GT/O | None | 60 | 0 | 59 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g41 | 17 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 162 | 162 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 100 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3073 | 3073 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 91. Clock Region Cell Placement per Global Clock: Region X1Y3 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 4779 | 0 | 4737 | 0 | 42 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2292 | 0 | 2291 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 229 | 0 | 229 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 50 | 0 | 46 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | clk250 | | g4 | 18 | BUFGCE/O | None | 211 | 0 | 211 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g38+ | 21 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g39+ | 19 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g40 | 16 | BUFG_GT/O | None | 584 | 0 | 584 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g41+ | 17 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 25 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 245 | 245 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 128 | 128 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3889 | 3889 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 92. Clock Region Cell Placement per Global Clock: Region X2Y3 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 4273 | 0 | 4235 | 0 | 38 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1098 | 0 | 1098 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 15 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 674 | 0 | 625 | 0 | 0 | 49 | 0 | 0 | 0 | 0 | clk250 | | g4 | 18 | BUFGCE/O | None | 84 | 0 | 84 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g6 | 1 | BUFG_GT/O | None | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] | | g38 | 21 | BUFG_GT/O | None | 665 | 0 | 665 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g39 | 19 | BUFG_GT/O | None | 665 | 0 | 665 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g40 | 16 | BUFG_GT/O | None | 29 | 0 | 29 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g41 | 17 | BUFG_GT/O | None | 665 | 0 | 665 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g59+ | 0 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKIN1 | | g60+ | 6 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 136 | 136 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 23 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3796 | 3796 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 93. Clock Region Cell Placement per Global Clock: Region X3Y3 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 4138 | 0 | 4106 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1940 | 0 | 1938 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 48 | 0 | 48 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 1784 | 0 | 1727 | 2 | 2 | 53 | 0 | 0 | 0 | 0 | clk250 | | g4 | 18 | BUFGCE/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g5+ | 12 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKFBIN | | g6+ | 1 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] | | g7 | 11 | BUFGCE_DIV/O | None | 4 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/fabric_clk_in | | g9 | 17 | BUFG_GT/O | None | 26 | 0 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g10 | 16 | BUFG_GT/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g18 | 19 | BUFG_GT/O | None | 7 | 0 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g19 | 21 | BUFG_GT/O | None | 7 | 0 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 8 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 79 | 79 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 59 | 59 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2485 | 2485 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 94. Clock Region Cell Placement per Global Clock: Region X4Y3 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 4054 | 0 | 4014 | 0 | 40 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 906 | 0 | 906 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 15 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 1518 | 0 | 1458 | 0 | 0 | 60 | 0 | 0 | 0 | 0 | clk250 | | g4 | 18 | BUFGCE/O | None | 134 | 0 | 134 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g5+ | 12 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKFBIN | | g7+ | 11 | BUFGCE_DIV/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/fabric_clk_in | | g9 | 17 | BUFG_GT/O | None | 525 | 0 | 525 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g10 | 16 | BUFG_GT/O | None | 252 | 0 | 252 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g18 | 19 | BUFG_GT/O | None | 658 | 0 | 658 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g19 | 21 | BUFG_GT/O | None | 439 | 0 | 439 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60+ | 6 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 184 | 184 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 56 | 56 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2642 | 2642 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 95. Clock Region Cell Placement per Global Clock: Region X5Y3 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3023 | 0 | 2990 | 0 | 33 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1635 | 0 | 1634 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 1637 | 0 | 1630 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 85 | 0 | 85 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk250 | | g4 | 18 | BUFGCE/O | None | 108 | 0 | 108 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g5 | 12 | BUFGCE/O | None | 617 | 0 | 590 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | CLKFBIN | | g9 | 17 | BUFG_GT/O | None | 122 | 0 | 121 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g10 | 16 | BUFG_GT/O | None | 221 | 0 | 220 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g18 | 19 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g19 | 21 | BUFG_GT/O | None | 227 | 0 | 226 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g57+ | 2 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk62_5 | | g60 | 6 | BUFGCE/O | None | 0 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 153 | 153 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 201 | 201 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2433 | 2433 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 96. Clock Region Cell Placement per Global Clock: Region X0Y4 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 2850 | 0 | 2819 | 0 | 31 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2071 | 0 | 2069 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 1708 | 0 | 1701 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | tx_wordclk | | g33 | 16 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g34 | 19 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g42 | 17 | BUFG_GT/O | None | 121 | 0 | 120 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g43 | 21 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 54 | 54 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 136 | 136 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 194 | 194 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2321 | 2321 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 97. Clock Region Cell Placement per Global Clock: Region X1Y4 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 2943 | 0 | 2905 | 0 | 38 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2098 | 0 | 2096 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 532 | 0 | 532 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 122 | 0 | 108 | 0 | 0 | 14 | 0 | 0 | 0 | 0 | clk250 | | g4 | 18 | BUFGCE/O | None | 290 | 0 | 290 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g33 | 16 | BUFG_GT/O | None | 637 | 0 | 637 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g34+ | 19 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g42 | 17 | BUFG_GT/O | None | 524 | 0 | 524 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g43+ | 21 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 116 | 116 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 262 | 262 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2407 | 2407 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 98. Clock Region Cell Placement per Global Clock: Region X2Y4 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3834 | 0 | 3803 | 0 | 31 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 968 | 0 | 968 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 16 | 0 | 15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 1160 | 0 | 1127 | 0 | 0 | 33 | 0 | 0 | 0 | 0 | clk250 | | g4 | 18 | BUFGCE/O | None | 34 | 0 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g5 | 12 | BUFGCE/O | None | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CLKFBIN | | g6 | 1 | BUFG_GT/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] | | g7+ | 11 | BUFGCE_DIV/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/fabric_clk_in | | g33 | 16 | BUFG_GT/O | None | 28 | 0 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g34 | 19 | BUFG_GT/O | None | 664 | 0 | 664 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g42 | 17 | BUFG_GT/O | None | 27 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g43 | 21 | BUFG_GT/O | None | 664 | 0 | 664 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g57+ | 2 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk62_5 | | g58+ | 15 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKFBOUT_bufg_n_0 | | g59 | 0 | BUFG_GT/O | None | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CLKIN1 | | g60+ | 6 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 133 | 133 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 14 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2510 | 2510 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 99. Clock Region Cell Placement per Global Clock: Region X3Y4 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 4500 | 0 | 4474 | 0 | 26 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 721 | 0 | 721 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 15 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 2559 | 0 | 2530 | 0 | 0 | 29 | 0 | 0 | 0 | 0 | clk250 | | g4+ | 18 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g5 | 12 | BUFGCE/O | None | 7 | 0 | 1 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | CLKFBIN | | g6+ | 1 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/i_mgt_wrapper/i_rxusrclk/bbstub_rxoutclk_out[0] | | g7+ | 11 | BUFGCE_DIV/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | i_tcds2_if/fabric_clk_in | | g10 | 16 | BUFG_GT/O | None | 8 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g34 | 19 | BUFG_GT/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g42 | 17 | BUFG_GT/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g43 | 21 | BUFG_GT/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[2].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g57+ | 2 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk62_5 | | g58+ | 15 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKFBOUT_bufg_n_0 | | g60+ | 6 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 95 | 95 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 12 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 1594 | 1594 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 100. Clock Region Cell Placement per Global Clock: Region X4Y4 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3921 | 0 | 3903 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 525 | 0 | 525 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2+ | 22 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 3180 | 0 | 3147 | 0 | 0 | 33 | 0 | 0 | 0 | 0 | clk250 | | g4+ | 18 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g5 | 12 | BUFGCE/O | None | 2 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | CLKFBIN | | g7 | 11 | BUFGCE_DIV/O | None | 12 | 1 | 12 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | i_tcds2_if/fabric_clk_in | | g10 | 16 | BUFG_GT/O | None | 81 | 0 | 81 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g57+ | 2 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk62_5 | | g58 | 15 | BUFGCE/O | None | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CLKFBOUT_bufg_n_0 | | g60 | 6 | BUFGCE/O | None | 0 | 4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 11 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 21 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 748 | 748 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 101. Clock Region Cell Placement per Global Clock: Region X5Y4 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 439 | 0 | 431 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 359 | 0 | 359 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 294 | 0 | 294 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 326 | 0 | 326 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk250 | | g4 | 18 | BUFGCE/O | None | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g5 | 12 | BUFGCE/O | None | 2341 | 0 | 2289 | 43 | 9 | 0 | 0 | 0 | 0 | 0 | CLKFBIN | | g10 | 16 | BUFG_GT/O | None | 110 | 0 | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[0].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g57+ | 2 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk62_5 | | g60 | 6 | BUFGCE/O | None | 0 | 25 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g62 | 14 | BUFGCE/O | None | 0 | 128 | 128 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 103 | 103 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 102. Clock Region Cell Placement per Global Clock: Region X0Y5 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 2027 | 0 | 1999 | 0 | 28 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1563 | 0 | 1562 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 452 | 0 | 452 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g60 | 6 | BUFGCE/O | None | 0 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 60 | 60 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 188 | 188 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 1647 | 1646 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 103. Clock Region Cell Placement per Global Clock: Region X1Y5 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3775 | 0 | 3741 | 0 | 34 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2049 | 0 | 2048 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2+ | 22 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g60+ | 6 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 209 | 209 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 26 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3104 | 3104 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 104. Clock Region Cell Placement per Global Clock: Region X2Y5 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3887 | 0 | 3849 | 0 | 38 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1960 | 0 | 1958 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 226 | 0 | 226 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 8 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk250 | | g60 | 6 | BUFGCE/O | None | 0 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 182 | 182 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 111 | 111 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3133 | 3133 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 105. Clock Region Cell Placement per Global Clock: Region X3Y5 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 1905 | 0 | 1876 | 0 | 29 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2434 | 0 | 2433 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 2036 | 0 | 2036 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g3 | 4 | BUFGCE/O | None | 16 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk250 | | g4+ | 18 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g31 | 0 | BUFG_GT/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 244 | 244 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 71 | 71 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 878 | 878 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 1409 | 1409 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 106. Clock Region Cell Placement per Global Clock: Region X4Y5 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 4104 | 0 | 4067 | 0 | 37 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1573 | 0 | 1573 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g31+ | 0 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60+ | 6 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 209 | 209 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62+ | 14 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3361 | 3361 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 107. Clock Region Cell Placement per Global Clock: Region X5Y5 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3625 | 0 | 3585 | 0 | 40 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1769 | 0 | 1769 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g60 | 6 | BUFGCE/O | None | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 182 | 182 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2939 | 2939 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 108. Clock Region Cell Placement per Global Clock: Region X0Y6 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 2704 | 0 | 2671 | 0 | 33 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1541 | 0 | 1540 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 146 | 0 | 146 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g60 | 6 | BUFGCE/O | None | 0 | 17 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 126 | 126 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 53 | 53 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2200 | 2200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 109. Clock Region Cell Placement per Global Clock: Region X1Y6 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 4117 | 0 | 4078 | 0 | 39 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2004 | 0 | 2004 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 9 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4 | 18 | BUFGCE/O | None | 54 | 0 | 54 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g49+ | 0 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 166 | 166 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 10 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3343 | 3343 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 110. Clock Region Cell Placement per Global Clock: Region X2Y6 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 4171 | 0 | 4132 | 0 | 39 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1999 | 0 | 1999 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 230 | 0 | 230 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4+ | 18 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g49 | 0 | BUFG_GT/O | None | 29 | 0 | 29 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 29 | 29 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 202 | 202 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 109 | 109 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3560 | 3560 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 111. Clock Region Cell Placement per Global Clock: Region X3Y6 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 4406 | 0 | 4365 | 0 | 41 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2408 | 0 | 2408 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 15 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4 | 18 | BUFGCE/O | None | 53 | 0 | 53 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g60 | 6 | BUFGCE/O | None | 0 | 14 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 206 | 206 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 88 | 88 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3604 | 3604 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 112. Clock Region Cell Placement per Global Clock: Region X4Y6 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3584 | 0 | 3549 | 0 | 35 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2448 | 0 | 2446 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 12 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g31+ | 0 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 11 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 144 | 144 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 86 | 86 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2942 | 2942 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 113. Clock Region Cell Placement per Global Clock: Region X5Y6 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 2566 | 0 | 2537 | 0 | 29 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1568 | 0 | 1567 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 1122 | 0 | 1121 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g60 | 6 | BUFGCE/O | None | 0 | 104 | 104 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 140 | 140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 340 | 340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2094 | 2094 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 114. Clock Region Cell Placement per Global Clock: Region X0Y7 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 2451 | 0 | 2422 | 0 | 29 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1421 | 0 | 1421 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 1870 | 0 | 1862 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | tx_wordclk | | g44 | 19 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g47 | 21 | BUFG_GT/O | None | 130 | 0 | 129 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g48 | 17 | BUFG_GT/O | None | 3 | 0 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g49 | 0 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 54 | 54 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 90 | 90 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 164 | 164 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 1999 | 1999 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 115. Clock Region Cell Placement per Global Clock: Region X1Y7 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 2964 | 0 | 2929 | 0 | 35 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1658 | 0 | 1658 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 80 | 0 | 80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4 | 18 | BUFGCE/O | None | 348 | 0 | 348 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g44 | 19 | BUFG_GT/O | None | 120 | 0 | 120 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g47 | 21 | BUFG_GT/O | None | 515 | 0 | 515 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g48 | 17 | BUFG_GT/O | None | 642 | 0 | 642 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g49 | 0 | BUFG_GT/O | None | 504 | 0 | 504 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 15 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 171 | 171 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 98 | 98 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2445 | 2445 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 116. Clock Region Cell Placement per Global Clock: Region X2Y7 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3598 | 0 | 3562 | 0 | 36 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2008 | 0 | 2006 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 18 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4 | 18 | BUFGCE/O | None | 83 | 0 | 83 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g44 | 19 | BUFG_GT/O | None | 545 | 0 | 545 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g47 | 21 | BUFG_GT/O | None | 28 | 0 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g48 | 17 | BUFG_GT/O | None | 28 | 0 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g49 | 0 | BUFG_GT/O | None | 132 | 0 | 132 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60+ | 6 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 163 | 163 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2910 | 2910 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 117. Clock Region Cell Placement per Global Clock: Region X3Y7 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 2633 | 0 | 2603 | 0 | 30 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 2161 | 0 | 2160 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 17 | 0 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4 | 18 | BUFGCE/O | None | 137 | 0 | 137 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g20 | 17 | BUFG_GT/O | None | 665 | 0 | 665 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g23 | 21 | BUFG_GT/O | None | 660 | 0 | 660 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g24 | 19 | BUFG_GT/O | None | 665 | 0 | 665 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g25 | 16 | BUFG_GT/O | None | 28 | 0 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60+ | 6 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 89 | 89 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 17 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2086 | 2086 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 118. Clock Region Cell Placement per Global Clock: Region X4Y7 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3443 | 0 | 3406 | 0 | 37 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1816 | 0 | 1815 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 10 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4 | 18 | BUFGCE/O | None | 185 | 0 | 185 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g20+ | 17 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g23 | 21 | BUFG_GT/O | None | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g24+ | 19 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g25 | 16 | BUFG_GT/O | None | 620 | 0 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g31+ | 0 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60+ | 6 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 149 | 149 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 6 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2798 | 2798 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 119. Clock Region Cell Placement per Global Clock: Region X5Y7 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3294 | 0 | 3259 | 0 | 35 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1941 | 0 | 1940 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 1439 | 0 | 1431 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | tx_wordclk | | g20 | 17 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[0].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g23 | 21 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[1].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g24 | 19 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[2].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g25 | 16 | BUFG_GT/O | None | 25 | 0 | 24 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[3].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 29 | 29 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 166 | 166 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 104 | 104 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2644 | 2644 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 120. Clock Region Cell Placement per Global Clock: Region X0Y8 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 1973 | 0 | 1946 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1080 | 0 | 1079 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 1462 | 0 | 1453 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | tx_wordclk | | g50 | 17 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g51 | 16 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g52 | 19 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g53 | 21 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g61 | 8 | BUFGCE/O | None | 0 | 91 | 91 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g63 | 20 | BUFGCE/O | None | 0 | 1599 | 1599 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 121. Clock Region Cell Placement per Global Clock: Region X1Y8 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3827 | 0 | 3794 | 0 | 33 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1673 | 0 | 1670 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 4 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4 | 18 | BUFGCE/O | None | 114 | 0 | 114 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g45+ | 0 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g50+ | 17 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g51 | 16 | BUFG_GT/O | None | 635 | 0 | 635 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g52+ | 19 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g53+ | 21 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g61 | 8 | BUFGCE/O | None | 0 | 196 | 196 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3130 | 3130 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 122. Clock Region Cell Placement per Global Clock: Region X2Y8 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 2382 | 0 | 2351 | 0 | 31 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1763 | 0 | 1762 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 251 | 0 | 251 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4 | 18 | BUFGCE/O | None | 193 | 0 | 193 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g45 | 0 | BUFG_GT/O | None | 59 | 0 | 59 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g50 | 17 | BUFG_GT/O | None | 665 | 0 | 665 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g51 | 16 | BUFG_GT/O | None | 30 | 0 | 30 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g52 | 19 | BUFG_GT/O | None | 665 | 0 | 665 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g53 | 21 | BUFG_GT/O | None | 665 | 0 | 665 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 29 | 29 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 78 | 78 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 108 | 108 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 1962 | 1962 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 123. Clock Region Cell Placement per Global Clock: Region X3Y8 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 4304 | 0 | 4265 | 0 | 39 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1933 | 0 | 1933 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 33 | 0 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4 | 18 | BUFGCE/O | None | 33 | 0 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g26 | 19 | BUFG_GT/O | None | 662 | 0 | 662 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g27 | 16 | BUFG_GT/O | None | 49 | 0 | 49 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g28 | 17 | BUFG_GT/O | None | 47 | 0 | 47 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g29 | 21 | BUFG_GT/O | None | 28 | 0 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g31 | 0 | BUFG_GT/O | None | 52 | 0 | 52 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 230 | 230 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 36 | 36 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 3539 | 3539 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 124. Clock Region Cell Placement per Global Clock: Region X4Y8 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 3029 | 0 | 2994 | 0 | 35 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1452 | 0 | 1451 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 32 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4 | 18 | BUFGCE/O | None | 305 | 0 | 305 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g26 | 19 | BUFG_GT/O | None | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g27 | 16 | BUFG_GT/O | None | 616 | 0 | 616 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g28 | 17 | BUFG_GT/O | None | 618 | 0 | 618 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g29 | 21 | BUFG_GT/O | None | 45 | 0 | 45 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g31 | 0 | BUFG_GT/O | None | 20 | 0 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g61 | 8 | BUFGCE/O | None | 0 | 136 | 136 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 6 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2459 | 2459 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 125. Clock Region Cell Placement per Global Clock: Region X5Y8 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 2831 | 0 | 2802 | 0 | 29 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1715 | 0 | 1714 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 1346 | 0 | 1338 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | tx_wordclk | | g4 | 18 | BUFGCE/O | None | 59 | 0 | 59 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g26 | 19 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[4].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g27 | 16 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[5].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g28 | 17 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[6].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g29 | 21 | BUFG_GT/O | None | 600 | 0 | 599 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[7].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g61 | 8 | BUFGCE/O | None | 0 | 142 | 142 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g63 | 20 | BUFGCE/O | None | 0 | 2281 | 2281 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 126. Clock Region Cell Placement per Global Clock: Region X0Y9 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 1000 | 0 | 984 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 522 | 0 | 522 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 1103 | 0 | 1096 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | tx_wordclk | | g45 | 0 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g46 | 21 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g54 | 19 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g55 | 17 | BUFG_GT/O | None | 3 | 0 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g61 | 8 | BUFGCE/O | None | 0 | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g63 | 20 | BUFGCE/O | None | 0 | 786 | 786 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 127. Clock Region Cell Placement per Global Clock: Region X1Y9 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 2802 | 0 | 2775 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1369 | 0 | 1369 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 6 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4 | 18 | BUFGCE/O | None | 117 | 0 | 117 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g45 | 0 | BUFG_GT/O | None | 84 | 0 | 84 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g46+ | 21 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g54+ | 19 | BUFG_GT/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g55 | 17 | BUFG_GT/O | None | 641 | 0 | 641 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g61 | 8 | BUFGCE/O | None | 0 | 147 | 147 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2287 | 2287 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 128. Clock Region Cell Placement per Global Clock: Region X2Y9 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 2641 | 0 | 2610 | 0 | 31 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 989 | 0 | 989 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4 | 18 | BUFGCE/O | None | 63 | 0 | 63 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g45 | 0 | BUFG_GT/O | None | 522 | 0 | 522 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g46 | 21 | BUFG_GT/O | None | 665 | 0 | 665 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g54 | 19 | BUFG_GT/O | None | 665 | 0 | 665 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g55 | 17 | BUFG_GT/O | None | 29 | 0 | 29 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[3].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60+ | 6 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 121 | 121 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2160 | 2160 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 129. Clock Region Cell Placement per Global Clock: Region X3Y9 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 2693 | 0 | 2663 | 0 | 30 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1942 | 0 | 1940 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 194 | 0 | 194 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4+ | 18 | BUFGCE/O | None | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g21 | 21 | BUFG_GT/O | None | 29 | 0 | 29 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g22 | 17 | BUFG_GT/O | None | 40 | 0 | 40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g30 | 19 | BUFG_GT/O | None | 29 | 0 | 29 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g31 | 0 | BUFG_GT/O | None | 354 | 0 | 354 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g60 | 6 | BUFGCE/O | None | 0 | 27 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[14].ngCCM_gbt/fabric_clk_div2_reg[0] | | g61 | 8 | BUFGCE/O | None | 0 | 126 | 126 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g62 | 14 | BUFGCE/O | None | 0 | 79 | 79 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk_div2 | | g63 | 20 | BUFGCE/O | None | 0 | 2199 | 2199 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts **** In Global Id column, sympbol '+' indicates that global clock was used only to route through the clock region. 130. Clock Region Cell Placement per Global Clock: Region X4Y9 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 2330 | 0 | 2302 | 0 | 28 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 1175 | 0 | 1175 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 6 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | tx_wordclk | | g4 | 18 | BUFGCE/O | None | 39 | 0 | 39 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g21 | 21 | BUFG_GT/O | None | 75 | 0 | 75 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g22 | 17 | BUFG_GT/O | None | 630 | 0 | 630 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g30 | 19 | BUFG_GT/O | None | 258 | 0 | 258 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g31 | 0 | BUFG_GT/O | None | 238 | 0 | 238 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g61 | 8 | BUFGCE/O | None | 0 | 117 | 117 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g63 | 20 | BUFGCE/O | None | 0 | 1882 | 1882 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 131. Clock Region Cell Placement per Global Clock: Region X5Y9 -------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | 10 | BUFGCE/O | None | 1377 | 0 | 1361 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | CLK | | g1 | 23 | BUFGCE/O | None | 589 | 0 | 589 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | fabric_clk | | g2 | 22 | BUFGCE/O | None | 1174 | 0 | 1167 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | tx_wordclk | | g4 | 18 | BUFGCE/O | None | 161 | 0 | 161 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DRPclk | | g21 | 21 | BUFG_GT/O | None | 569 | 0 | 568 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[10].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g22 | 17 | BUFG_GT/O | None | 3 | 0 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[11].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g30 | 19 | BUFG_GT/O | None | 386 | 0 | 385 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[8].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g31 | 0 | BUFG_GT/O | None | 8 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | g_gbt_bank[1].gbtbank/i_gbt_bank/mgt_inst/g_mgt_channel[9].i_mgt_ip_rx_buf/i_mgt_ip/inst/gen_gtwizard_gthe3_top.mgt_ip_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_rx_user_clocking_internal.gen_single_instance.gtwiz_userclk_rx_inst/gtwiz_userclk_rx_usrclk2_out[0] | | g61 | 8 | BUFGCE/O | None | 0 | 44 | 44 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SFP_GEN[1].ngFEC_module/bram_array[0].buffer_server/E[0] | | g63 | 20 | BUFGCE/O | None | 0 | 1132 | 1132 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ipb_rst_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts