// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
// Date        : Fri Mar 12 21:25:04 2021
// Host        : baby running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode synth_stub
//               d:/Design_collection/ngFECKU115_ipb/ngFECKU115_ipb.srcs/sources_1/ip/ttc_mgt/ttc_mgt_stub.v
// Design      : ttc_mgt
// Purpose     : Stub declaration of top-level module interface
// Device      : xcku115-flva2104-1-c
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ttc_mgt_gtwizard_top,Vivado 2020.2" *)
module ttc_mgt(gtwiz_userclk_tx_active_in, 
  gtwiz_userclk_rx_active_in, gtwiz_buffbypass_rx_reset_in, 
  gtwiz_buffbypass_rx_start_user_in, gtwiz_buffbypass_rx_done_out, 
  gtwiz_buffbypass_rx_error_out, gtwiz_reset_tx_done_in, gtwiz_reset_rx_done_in, 
  gtwiz_userdata_tx_in, gtwiz_userdata_rx_out, gtrefclk00_in, gtrefclk01_in, 
  gtsouthrefclk00_in, gtsouthrefclk01_in, gtsouthrefclk10_in, gtsouthrefclk11_in, 
  qpll0refclksel_in, qpll0reset_in, qpll1refclksel_in, qpll1reset_in, qpll0lock_out, 
  qpll0outclk_out, qpll0outrefclk_out, qpll1lock_out, qpll1outclk_out, qpll1outrefclk_out, 
  gthrxn_in, gthrxp_in, gtrxreset_in, gttxreset_in, loopback_in, rxpolarity_in, 
  rxprogdivreset_in, rxslide_in, rxuserrdy_in, rxusrclk_in, rxusrclk2_in, txpolarity_in, 
  txprogdivreset_in, txuserrdy_in, txusrclk_in, txusrclk2_in, gthtxn_out, gthtxp_out, 
  gtpowergood_out, rxcdrlock_out, rxoutclk_out, rxpmaresetdone_out, rxrecclkout_out, 
  rxresetdone_out, txoutclk_out, txpmaresetdone_out, txresetdone_out)
/* synthesis syn_black_box black_box_pad_pin="gtwiz_userclk_tx_active_in[0:0],gtwiz_userclk_rx_active_in[0:0],gtwiz_buffbypass_rx_reset_in[0:0],gtwiz_buffbypass_rx_start_user_in[0:0],gtwiz_buffbypass_rx_done_out[0:0],gtwiz_buffbypass_rx_error_out[0:0],gtwiz_reset_tx_done_in[0:0],gtwiz_reset_rx_done_in[0:0],gtwiz_userdata_tx_in[31:0],gtwiz_userdata_rx_out[31:0],gtrefclk00_in[0:0],gtrefclk01_in[0:0],gtsouthrefclk00_in[0:0],gtsouthrefclk01_in[0:0],gtsouthrefclk10_in[0:0],gtsouthrefclk11_in[0:0],qpll0refclksel_in[2:0],qpll0reset_in[0:0],qpll1refclksel_in[2:0],qpll1reset_in[0:0],qpll0lock_out[0:0],qpll0outclk_out[0:0],qpll0outrefclk_out[0:0],qpll1lock_out[0:0],qpll1outclk_out[0:0],qpll1outrefclk_out[0:0],gthrxn_in[0:0],gthrxp_in[0:0],gtrxreset_in[0:0],gttxreset_in[0:0],loopback_in[2:0],rxpolarity_in[0:0],rxprogdivreset_in[0:0],rxslide_in[0:0],rxuserrdy_in[0:0],rxusrclk_in[0:0],rxusrclk2_in[0:0],txpolarity_in[0:0],txprogdivreset_in[0:0],txuserrdy_in[0:0],txusrclk_in[0:0],txusrclk2_in[0:0],gthtxn_out[0:0],gthtxp_out[0:0],gtpowergood_out[0:0],rxcdrlock_out[0:0],rxoutclk_out[0:0],rxpmaresetdone_out[0:0],rxrecclkout_out[0:0],rxresetdone_out[0:0],txoutclk_out[0:0],txpmaresetdone_out[0:0],txresetdone_out[0:0]" */;
  input [0:0]gtwiz_userclk_tx_active_in;
  input [0:0]gtwiz_userclk_rx_active_in;
  input [0:0]gtwiz_buffbypass_rx_reset_in;
  input [0:0]gtwiz_buffbypass_rx_start_user_in;
  output [0:0]gtwiz_buffbypass_rx_done_out;
  output [0:0]gtwiz_buffbypass_rx_error_out;
  input [0:0]gtwiz_reset_tx_done_in;
  input [0:0]gtwiz_reset_rx_done_in;
  input [31:0]gtwiz_userdata_tx_in;
  output [31:0]gtwiz_userdata_rx_out;
  input [0:0]gtrefclk00_in;
  input [0:0]gtrefclk01_in;
  input [0:0]gtsouthrefclk00_in;
  input [0:0]gtsouthrefclk01_in;
  input [0:0]gtsouthrefclk10_in;
  input [0:0]gtsouthrefclk11_in;
  input [2:0]qpll0refclksel_in;
  input [0:0]qpll0reset_in;
  input [2:0]qpll1refclksel_in;
  input [0:0]qpll1reset_in;
  output [0:0]qpll0lock_out;
  output [0:0]qpll0outclk_out;
  output [0:0]qpll0outrefclk_out;
  output [0:0]qpll1lock_out;
  output [0:0]qpll1outclk_out;
  output [0:0]qpll1outrefclk_out;
  input [0:0]gthrxn_in;
  input [0:0]gthrxp_in;
  input [0:0]gtrxreset_in;
  input [0:0]gttxreset_in;
  input [2:0]loopback_in;
  input [0:0]rxpolarity_in;
  input [0:0]rxprogdivreset_in;
  input [0:0]rxslide_in;
  input [0:0]rxuserrdy_in;
  input [0:0]rxusrclk_in;
  input [0:0]rxusrclk2_in;
  input [0:0]txpolarity_in;
  input [0:0]txprogdivreset_in;
  input [0:0]txuserrdy_in;
  input [0:0]txusrclk_in;
  input [0:0]txusrclk2_in;
  output [0:0]gthtxn_out;
  output [0:0]gthtxp_out;
  output [0:0]gtpowergood_out;
  output [0:0]rxcdrlock_out;
  output [0:0]rxoutclk_out;
  output [0:0]rxpmaresetdone_out;
  output [0:0]rxrecclkout_out;
  output [0:0]rxresetdone_out;
  output [0:0]txoutclk_out;
  output [0:0]txpmaresetdone_out;
  output [0:0]txresetdone_out;
endmodule