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-- DO NOT MODIFY THIS FILE.

-- IP VLNV: xilinx.com:ip:gtwizard_ultrascale:1.7
-- IP Revision: 9

-- The following code must appear in the VHDL architecture header.

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT ttc_mgt
  PORT (
    gtwiz_userclk_tx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_userclk_rx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_buffbypass_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_buffbypass_rx_start_user_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_buffbypass_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_buffbypass_rx_error_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_tx_done_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_rx_done_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    gtrefclk00_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtrefclk01_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtsouthrefclk00_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtsouthrefclk01_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtsouthrefclk10_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtsouthrefclk11_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    qpll0refclksel_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    qpll0reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    qpll1refclksel_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    qpll1reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    qpll0lock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    qpll0outclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    qpll0outrefclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    qpll1lock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    qpll1outclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    qpll1outrefclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gthrxn_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gthrxp_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtrxreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gttxreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    loopback_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    rxpolarity_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxprogdivreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxslide_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxuserrdy_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxusrclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxusrclk2_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txpolarity_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txprogdivreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txuserrdy_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txusrclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txusrclk2_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gthtxn_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gthtxp_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtpowergood_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxcdrlock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxoutclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxrecclkout_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    txoutclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    txpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    txresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
  );
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : ttc_mgt
  PORT MAP (
    gtwiz_userclk_tx_active_in => gtwiz_userclk_tx_active_in,
    gtwiz_userclk_rx_active_in => gtwiz_userclk_rx_active_in,
    gtwiz_buffbypass_rx_reset_in => gtwiz_buffbypass_rx_reset_in,
    gtwiz_buffbypass_rx_start_user_in => gtwiz_buffbypass_rx_start_user_in,
    gtwiz_buffbypass_rx_done_out => gtwiz_buffbypass_rx_done_out,
    gtwiz_buffbypass_rx_error_out => gtwiz_buffbypass_rx_error_out,
    gtwiz_reset_tx_done_in => gtwiz_reset_tx_done_in,
    gtwiz_reset_rx_done_in => gtwiz_reset_rx_done_in,
    gtwiz_userdata_tx_in => gtwiz_userdata_tx_in,
    gtwiz_userdata_rx_out => gtwiz_userdata_rx_out,
    gtrefclk00_in => gtrefclk00_in,
    gtrefclk01_in => gtrefclk01_in,
    gtsouthrefclk00_in => gtsouthrefclk00_in,
    gtsouthrefclk01_in => gtsouthrefclk01_in,
    gtsouthrefclk10_in => gtsouthrefclk10_in,
    gtsouthrefclk11_in => gtsouthrefclk11_in,
    qpll0refclksel_in => qpll0refclksel_in,
    qpll0reset_in => qpll0reset_in,
    qpll1refclksel_in => qpll1refclksel_in,
    qpll1reset_in => qpll1reset_in,
    qpll0lock_out => qpll0lock_out,
    qpll0outclk_out => qpll0outclk_out,
    qpll0outrefclk_out => qpll0outrefclk_out,
    qpll1lock_out => qpll1lock_out,
    qpll1outclk_out => qpll1outclk_out,
    qpll1outrefclk_out => qpll1outrefclk_out,
    gthrxn_in => gthrxn_in,
    gthrxp_in => gthrxp_in,
    gtrxreset_in => gtrxreset_in,
    gttxreset_in => gttxreset_in,
    loopback_in => loopback_in,
    rxpolarity_in => rxpolarity_in,
    rxprogdivreset_in => rxprogdivreset_in,
    rxslide_in => rxslide_in,
    rxuserrdy_in => rxuserrdy_in,
    rxusrclk_in => rxusrclk_in,
    rxusrclk2_in => rxusrclk2_in,
    txpolarity_in => txpolarity_in,
    txprogdivreset_in => txprogdivreset_in,
    txuserrdy_in => txuserrdy_in,
    txusrclk_in => txusrclk_in,
    txusrclk2_in => txusrclk2_in,
    gthtxn_out => gthtxn_out,
    gthtxp_out => gthtxp_out,
    gtpowergood_out => gtpowergood_out,
    rxcdrlock_out => rxcdrlock_out,
    rxoutclk_out => rxoutclk_out,
    rxpmaresetdone_out => rxpmaresetdone_out,
    rxrecclkout_out => rxrecclkout_out,
    rxresetdone_out => rxresetdone_out,
    txoutclk_out => txoutclk_out,
    txpmaresetdone_out => txpmaresetdone_out,
    txresetdone_out => txresetdone_out
  );
-- INST_TAG_END ------ End INSTANTIATION Template ---------

-- You must compile the wrapper file ttc_mgt.vhd when simulating
-- the core, ttc_mgt. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.