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Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:gtwizard_ultrascale:1.7 // IP Revision: 9 // The following must be inserted into your Verilog file for this // core to be instantiated. Change the instance name and port connections // (in parentheses) to your own signal names. //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG mgt_ip your_instance_name ( .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in), // input wire [0 : 0] gtwiz_userclk_tx_active_in .gtwiz_userclk_rx_reset_in(gtwiz_userclk_rx_reset_in), // input wire [0 : 0] gtwiz_userclk_rx_reset_in .gtwiz_userclk_rx_srcclk_out(gtwiz_userclk_rx_srcclk_out), // output wire [0 : 0] gtwiz_userclk_rx_srcclk_out .gtwiz_userclk_rx_usrclk_out(gtwiz_userclk_rx_usrclk_out), // output wire [0 : 0] gtwiz_userclk_rx_usrclk_out .gtwiz_userclk_rx_usrclk2_out(gtwiz_userclk_rx_usrclk2_out), // output wire [0 : 0] gtwiz_userclk_rx_usrclk2_out .gtwiz_userclk_rx_active_out(gtwiz_userclk_rx_active_out), // output wire [0 : 0] gtwiz_userclk_rx_active_out .gtwiz_reset_clk_freerun_in(gtwiz_reset_clk_freerun_in), // input wire [0 : 0] gtwiz_reset_clk_freerun_in .gtwiz_reset_all_in(gtwiz_reset_all_in), // input wire [0 : 0] gtwiz_reset_all_in .gtwiz_reset_tx_pll_and_datapath_in(gtwiz_reset_tx_pll_and_datapath_in), // input wire [0 : 0] gtwiz_reset_tx_pll_and_datapath_in .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in), // input wire [0 : 0] gtwiz_reset_tx_datapath_in .gtwiz_reset_rx_pll_and_datapath_in(gtwiz_reset_rx_pll_and_datapath_in), // input wire [0 : 0] gtwiz_reset_rx_pll_and_datapath_in .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), // input wire [0 : 0] gtwiz_reset_rx_datapath_in .gtwiz_reset_rx_cdr_stable_out(gtwiz_reset_rx_cdr_stable_out), // output wire [0 : 0] gtwiz_reset_rx_cdr_stable_out .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out), // output wire [0 : 0] gtwiz_reset_tx_done_out .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out), // output wire [0 : 0] gtwiz_reset_rx_done_out .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in), // input wire [19 : 0] gtwiz_userdata_tx_in .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out), // output wire [19 : 0] gtwiz_userdata_rx_out .drpaddr_in(drpaddr_in), // input wire [8 : 0] drpaddr_in .drpclk_in(drpclk_in), // input wire [0 : 0] drpclk_in .drpdi_in(drpdi_in), // input wire [15 : 0] drpdi_in .drpen_in(drpen_in), // input wire [0 : 0] drpen_in .drpwe_in(drpwe_in), // input wire [0 : 0] drpwe_in .gthrxn_in(gthrxn_in), // input wire [0 : 0] gthrxn_in .gthrxp_in(gthrxp_in), // input wire [0 : 0] gthrxp_in .gtrefclk0_in(gtrefclk0_in), // input wire [0 : 0] gtrefclk0_in .loopback_in(loopback_in), // input wire [2 : 0] loopback_in .rxpd_in(rxpd_in), // input wire [1 : 0] rxpd_in .rxpolarity_in(rxpolarity_in), // input wire [0 : 0] rxpolarity_in .rxslide_in(rxslide_in), // input wire [0 : 0] rxslide_in .txpd_in(txpd_in), // input wire [1 : 0] txpd_in .txpdelecidlemode_in(txpdelecidlemode_in), // input wire [0 : 0] txpdelecidlemode_in .txpippmen_in(txpippmen_in), // input wire [0 : 0] txpippmen_in .txpippmovrden_in(txpippmovrden_in), // input wire [0 : 0] txpippmovrden_in .txpippmpd_in(txpippmpd_in), // input wire [0 : 0] txpippmpd_in .txpippmsel_in(txpippmsel_in), // input wire [0 : 0] txpippmsel_in .txpippmstepsize_in(txpippmstepsize_in), // input wire [4 : 0] txpippmstepsize_in .txpolarity_in(txpolarity_in), // input wire [0 : 0] txpolarity_in .txusrclk_in(txusrclk_in), // input wire [0 : 0] txusrclk_in .txusrclk2_in(txusrclk2_in), // input wire [0 : 0] txusrclk2_in .cplllock_out(cplllock_out), // output wire [0 : 0] cplllock_out .drpdo_out(drpdo_out), // output wire [15 : 0] drpdo_out .drprdy_out(drprdy_out), // output wire [0 : 0] drprdy_out .gthtxn_out(gthtxn_out), // output wire [0 : 0] gthtxn_out .gthtxp_out(gthtxp_out), // output wire [0 : 0] gthtxp_out .gtpowergood_out(gtpowergood_out), // output wire [0 : 0] gtpowergood_out .rxpmaresetdone_out(rxpmaresetdone_out), // output wire [0 : 0] rxpmaresetdone_out .txbufstatus_out(txbufstatus_out), // output wire [1 : 0] txbufstatus_out .txoutclk_out(txoutclk_out), // output wire [0 : 0] txoutclk_out .txpmaresetdone_out(txpmaresetdone_out) // output wire [0 : 0] txpmaresetdone_out ); // INST_TAG_END ------ End INSTANTIATION Template --------- // You must compile the wrapper file mgt_ip.v when simulating // the core, mgt_ip. When compiling the wrapper file, be sure to // reference the Verilog simulation library.