// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 // Date : Fri Mar 12 21:28:47 2021 // Host : baby running 64-bit major release (build 9200) // Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gig_ethernet_pcs_pma_0_sim_netlist.v // Design : gig_ethernet_pcs_pma_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xcku115-flva2104-1-c // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* EXAMPLE_SIMULATION = "0" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "gig_ethernet_pcs_pma_v16_2_1,Vivado 2020.2" *) (* NotValidForBitStream *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix (gtrefclk, txp, txn, rxp, rxn, resetdone, cplllock, mmcm_reset, txoutclk, rxoutclk, userclk, userclk2, rxuserclk, rxuserclk2, pma_reset, mmcm_locked, independent_clock_bufg, gmii_txd, gmii_tx_en, gmii_tx_er, gmii_rxd, gmii_rx_dv, gmii_rx_er, gmii_isolate, configuration_vector, status_vector, reset, gtpowergood, signal_detect); input gtrefclk; output txp; output txn; input rxp; input rxn; output resetdone; output cplllock; output mmcm_reset; output txoutclk; output rxoutclk; input userclk; input userclk2; input rxuserclk; input rxuserclk2; input pma_reset; input mmcm_locked; input independent_clock_bufg; input [7:0]gmii_txd; input gmii_tx_en; input gmii_tx_er; output [7:0]gmii_rxd; output gmii_rx_dv; output gmii_rx_er; output gmii_isolate; input [4:0]configuration_vector; output [15:0]status_vector; input reset; output gtpowergood; input signal_detect; wire \ ; wire [4:0]configuration_vector; wire cplllock; wire gmii_isolate; wire gmii_rx_dv; wire gmii_rx_er; wire [7:0]gmii_rxd; wire gmii_tx_en; wire gmii_tx_er; wire [7:0]gmii_txd; wire gtpowergood; wire gtrefclk; wire independent_clock_bufg; wire mmcm_locked; wire mmcm_reset; wire pma_reset; wire reset; wire resetdone; wire rxn; wire rxoutclk; wire rxp; wire rxuserclk2; wire signal_detect; wire [6:0]\^status_vector ; wire txn; wire txoutclk; wire txp; wire userclk; wire userclk2; wire [15:7]NLW_U0_status_vector_UNCONNECTED; assign status_vector[15] = \ ; assign status_vector[14] = \ ; assign status_vector[13] = \ ; assign status_vector[12] = \ ; assign status_vector[11] = \ ; assign status_vector[10] = \ ; assign status_vector[9] = \ ; assign status_vector[8] = \ ; assign status_vector[7] = \ ; assign status_vector[6:0] = \^status_vector [6:0]; GND GND (.G(\ )); (* EXAMPLE_SIMULATION = "0" *) (* downgradeipidentifiedwarnings = "yes" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_block U0 (.configuration_vector({1'b0,configuration_vector[3:1],1'b0}), .cplllock(cplllock), .gmii_isolate(gmii_isolate), .gmii_rx_dv(gmii_rx_dv), .gmii_rx_er(gmii_rx_er), .gmii_rxd(gmii_rxd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), .gmii_txd(gmii_txd), .gtpowergood(gtpowergood), .gtrefclk(gtrefclk), .independent_clock_bufg(independent_clock_bufg), .mmcm_locked(mmcm_locked), .mmcm_reset(mmcm_reset), .pma_reset(pma_reset), .reset(reset), .resetdone(resetdone), .rxn(rxn), .rxoutclk(rxoutclk), .rxp(rxp), .rxuserclk(1'b0), .rxuserclk2(rxuserclk2), .signal_detect(signal_detect), .status_vector({NLW_U0_status_vector_UNCONNECTED[15:7],\^status_vector }), .txn(txn), .txoutclk(txoutclk), .txp(txp), .userclk(userclk), .userclk2(userclk2)); endmodule (* EXAMPLE_SIMULATION = "0" *) (* downgradeipidentifiedwarnings = "yes" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_block (gtrefclk, txp, txn, rxp, rxn, txoutclk, rxoutclk, resetdone, cplllock, mmcm_reset, mmcm_locked, userclk, userclk2, rxuserclk, rxuserclk2, independent_clock_bufg, pma_reset, gmii_txd, gmii_tx_en, gmii_tx_er, gmii_rxd, gmii_rx_dv, gmii_rx_er, gmii_isolate, configuration_vector, status_vector, reset, gtpowergood, signal_detect); input gtrefclk; output txp; output txn; input rxp; input rxn; output txoutclk; output rxoutclk; output resetdone; output cplllock; output mmcm_reset; input mmcm_locked; input userclk; input userclk2; input rxuserclk; input rxuserclk2; input independent_clock_bufg; input pma_reset; input [7:0]gmii_txd; input gmii_tx_en; input gmii_tx_er; output [7:0]gmii_rxd; output gmii_rx_dv; output gmii_rx_er; output gmii_isolate; input [4:0]configuration_vector; output [15:0]status_vector; input reset; output gtpowergood; input signal_detect; wire \ ; wire [4:0]configuration_vector; wire cplllock; wire enablealign; wire gmii_isolate; wire gmii_rx_dv; wire gmii_rx_er; wire [7:0]gmii_rxd; wire gmii_tx_en; wire gmii_tx_er; wire [7:0]gmii_txd; wire gtpowergood; wire gtrefclk; wire independent_clock_bufg; wire mgt_rx_reset; wire mgt_tx_reset; wire mmcm_locked; wire mmcm_reset; wire pma_reset; wire powerdown; wire reset; wire resetdone; wire resetdone_i; wire rxbuferr; wire rxchariscomma; wire rxcharisk; wire [1:0]rxclkcorcnt; wire [7:0]rxdata; wire rxdisperr; wire rxn; wire rxnotintable; wire rxoutclk; wire rxp; wire rxuserclk2; wire signal_detect; wire [6:0]\^status_vector ; wire txbuferr; wire txchardispmode; wire txchardispval; wire txcharisk; wire [7:0]txdata; wire txn; wire txoutclk; wire txp; wire userclk; wire userclk2; wire NLW_gig_ethernet_pcs_pma_0_core_an_enable_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_an_interrupt_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_drp_den_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_drp_dwe_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_drp_req_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_en_cdet_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_ewrap_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_loc_ref_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_mdio_out_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_mdio_tri_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_s_axi_arready_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_s_axi_awready_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_s_axi_bvalid_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_s_axi_rvalid_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_0_core_s_axi_wready_UNCONNECTED; wire [9:0]NLW_gig_ethernet_pcs_pma_0_core_drp_daddr_UNCONNECTED; wire [15:0]NLW_gig_ethernet_pcs_pma_0_core_drp_di_UNCONNECTED; wire [63:0]NLW_gig_ethernet_pcs_pma_0_core_rxphy_correction_timer_UNCONNECTED; wire [31:0]NLW_gig_ethernet_pcs_pma_0_core_rxphy_ns_field_UNCONNECTED; wire [47:0]NLW_gig_ethernet_pcs_pma_0_core_rxphy_s_field_UNCONNECTED; wire [1:0]NLW_gig_ethernet_pcs_pma_0_core_s_axi_bresp_UNCONNECTED; wire [31:0]NLW_gig_ethernet_pcs_pma_0_core_s_axi_rdata_UNCONNECTED; wire [1:0]NLW_gig_ethernet_pcs_pma_0_core_s_axi_rresp_UNCONNECTED; wire [1:0]NLW_gig_ethernet_pcs_pma_0_core_speed_selection_UNCONNECTED; wire [15:7]NLW_gig_ethernet_pcs_pma_0_core_status_vector_UNCONNECTED; wire [9:0]NLW_gig_ethernet_pcs_pma_0_core_tx_code_group_UNCONNECTED; assign status_vector[15] = \ ; assign status_vector[14] = \ ; assign status_vector[13] = \ ; assign status_vector[12] = \ ; assign status_vector[11] = \ ; assign status_vector[10] = \ ; assign status_vector[9] = \ ; assign status_vector[8] = \ ; assign status_vector[7] = \ ; assign status_vector[6:0] = \^status_vector [6:0]; GND GND (.G(\ )); (* B_SHIFTER_ADDR = "10'b0101010000" *) (* C_1588 = "0" *) (* C_2_5G = "FALSE" *) (* C_COMPONENT_NAME = "gig_ethernet_pcs_pma_0" *) (* C_DYNAMIC_SWITCHING = "FALSE" *) (* C_ELABORATION_TRANSIENT_DIR = "BlankString" *) (* C_FAMILY = "kintexu" *) (* C_HAS_AN = "FALSE" *) (* C_HAS_AXIL = "FALSE" *) (* C_HAS_MDIO = "FALSE" *) (* C_HAS_TEMAC = "TRUE" *) (* C_IS_SGMII = "FALSE" *) (* C_RX_GMII_CLK = "TXOUTCLK" *) (* C_SGMII_FABRIC_BUFFER = "TRUE" *) (* C_SGMII_PHY_MODE = "FALSE" *) (* C_USE_LVDS = "FALSE" *) (* C_USE_TBI = "FALSE" *) (* C_USE_TRANSCEIVER = "TRUE" *) (* GT_RX_BYTE_WIDTH = "1" *) (* KEEP_HIERARCHY = "soft" *) (* downgradeipidentifiedwarnings = "yes" *) (* is_du_within_envelope = "true" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_2_1 gig_ethernet_pcs_pma_0_core (.an_adv_config_val(1'b0), .an_adv_config_vector({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .an_enable(NLW_gig_ethernet_pcs_pma_0_core_an_enable_UNCONNECTED), .an_interrupt(NLW_gig_ethernet_pcs_pma_0_core_an_interrupt_UNCONNECTED), .an_restart_config(1'b0), .basex_or_sgmii(1'b0), .configuration_valid(1'b0), .configuration_vector({1'b0,configuration_vector[3:1],1'b0}), .correction_timer({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .dcm_locked(mmcm_locked), .drp_daddr(NLW_gig_ethernet_pcs_pma_0_core_drp_daddr_UNCONNECTED[9:0]), .drp_dclk(1'b0), .drp_den(NLW_gig_ethernet_pcs_pma_0_core_drp_den_UNCONNECTED), .drp_di(NLW_gig_ethernet_pcs_pma_0_core_drp_di_UNCONNECTED[15:0]), .drp_do({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drp_drdy(1'b0), .drp_dwe(NLW_gig_ethernet_pcs_pma_0_core_drp_dwe_UNCONNECTED), .drp_gnt(1'b0), .drp_req(NLW_gig_ethernet_pcs_pma_0_core_drp_req_UNCONNECTED), .en_cdet(NLW_gig_ethernet_pcs_pma_0_core_en_cdet_UNCONNECTED), .enablealign(enablealign), .ewrap(NLW_gig_ethernet_pcs_pma_0_core_ewrap_UNCONNECTED), .gmii_isolate(gmii_isolate), .gmii_rx_dv(gmii_rx_dv), .gmii_rx_er(gmii_rx_er), .gmii_rxd(gmii_rxd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), .gmii_txd(gmii_txd), .gtx_clk(1'b0), .link_timer_basex({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .link_timer_sgmii({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .link_timer_value({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .loc_ref(NLW_gig_ethernet_pcs_pma_0_core_loc_ref_UNCONNECTED), .mdc(1'b0), .mdio_in(1'b0), .mdio_out(NLW_gig_ethernet_pcs_pma_0_core_mdio_out_UNCONNECTED), .mdio_tri(NLW_gig_ethernet_pcs_pma_0_core_mdio_tri_UNCONNECTED), .mgt_rx_reset(mgt_rx_reset), .mgt_tx_reset(mgt_tx_reset), .phyad({1'b0,1'b0,1'b0,1'b0,1'b0}), .pma_rx_clk0(1'b0), .pma_rx_clk1(1'b0), .powerdown(powerdown), .reset(reset), .reset_done(resetdone), .rx_code_group0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rx_code_group1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rx_gt_nominal_latency({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b1,1'b1,1'b0,1'b0}), .rxbufstatus({rxbuferr,1'b0}), .rxchariscomma(rxchariscomma), .rxcharisk(rxcharisk), .rxclkcorcnt({1'b0,rxclkcorcnt}), .rxdata(rxdata), .rxdisperr(rxdisperr), .rxnotintable(rxnotintable), .rxphy_correction_timer(NLW_gig_ethernet_pcs_pma_0_core_rxphy_correction_timer_UNCONNECTED[63:0]), .rxphy_ns_field(NLW_gig_ethernet_pcs_pma_0_core_rxphy_ns_field_UNCONNECTED[31:0]), .rxphy_s_field(NLW_gig_ethernet_pcs_pma_0_core_rxphy_s_field_UNCONNECTED[47:0]), .rxrecclk(1'b0), .rxrundisp(1'b0), .s_axi_aclk(1'b0), .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arready(NLW_gig_ethernet_pcs_pma_0_core_s_axi_arready_UNCONNECTED), .s_axi_arvalid(1'b0), .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(NLW_gig_ethernet_pcs_pma_0_core_s_axi_awready_UNCONNECTED), .s_axi_awvalid(1'b0), .s_axi_bready(1'b0), .s_axi_bresp(NLW_gig_ethernet_pcs_pma_0_core_s_axi_bresp_UNCONNECTED[1:0]), .s_axi_bvalid(NLW_gig_ethernet_pcs_pma_0_core_s_axi_bvalid_UNCONNECTED), .s_axi_rdata(NLW_gig_ethernet_pcs_pma_0_core_s_axi_rdata_UNCONNECTED[31:0]), .s_axi_resetn(1'b0), .s_axi_rready(1'b0), .s_axi_rresp(NLW_gig_ethernet_pcs_pma_0_core_s_axi_rresp_UNCONNECTED[1:0]), .s_axi_rvalid(NLW_gig_ethernet_pcs_pma_0_core_s_axi_rvalid_UNCONNECTED), .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wready(NLW_gig_ethernet_pcs_pma_0_core_s_axi_wready_UNCONNECTED), .s_axi_wvalid(1'b0), .signal_detect(signal_detect), .speed_is_100(1'b0), .speed_is_10_100(1'b0), .speed_selection(NLW_gig_ethernet_pcs_pma_0_core_speed_selection_UNCONNECTED[1:0]), .status_vector({NLW_gig_ethernet_pcs_pma_0_core_status_vector_UNCONNECTED[15:7],\^status_vector }), .systemtimer_ns_field({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .systemtimer_s_field({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .tx_code_group(NLW_gig_ethernet_pcs_pma_0_core_tx_code_group_UNCONNECTED[9:0]), .txbuferr(txbuferr), .txchardispmode(txchardispmode), .txchardispval(txchardispval), .txcharisk(txcharisk), .txdata(txdata), .userclk(1'b0), .userclk2(userclk2)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_sync_block sync_block_reset_done (.data_in(resetdone_i), .resetdone(resetdone), .userclk2(userclk2)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_transceiver transceiver_inst (.D(txdata), .Q(rxclkcorcnt), .SR(mgt_rx_reset), .cplllock(cplllock), .data_in(resetdone_i), .enablealign(enablealign), .gtpowergood(gtpowergood), .gtrefclk(gtrefclk), .independent_clock_bufg(independent_clock_bufg), .mmcm_locked(mmcm_locked), .mmcm_reset(mmcm_reset), .pma_reset(pma_reset), .powerdown(powerdown), .rxbuferr(rxbuferr), .rxchariscomma(rxchariscomma), .rxcharisk(rxcharisk), .\rxdata_reg[7]_0 (rxdata), .rxdisperr(rxdisperr), .rxn(rxn), .rxnotintable(rxnotintable), .rxoutclk(rxoutclk), .rxp(rxp), .rxuserclk2(rxuserclk2), .txbuferr(txbuferr), .txchardispmode_reg_reg_0(txchardispmode), .txchardispval_reg_reg_0(txchardispval), .txcharisk_reg_reg_0(txcharisk), .txn(txn), .txoutclk(txoutclk), .txp(txp), .txreset(mgt_tx_reset), .userclk(userclk), .userclk2(userclk2)); endmodule (* CHECK_LICENSE_TYPE = "gig_ethernet_pcs_pma_0_gt,gig_ethernet_pcs_pma_0_gt_gtwizard_top,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "gig_ethernet_pcs_pma_0_gt_gtwizard_top,Vivado 2020.2" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_gt (gtwiz_userclk_tx_active_in, gtwiz_userclk_rx_active_in, gtwiz_reset_clk_freerun_in, gtwiz_reset_all_in, gtwiz_reset_tx_pll_and_datapath_in, gtwiz_reset_tx_datapath_in, gtwiz_reset_rx_pll_and_datapath_in, gtwiz_reset_rx_datapath_in, gtwiz_reset_rx_cdr_stable_out, gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out, gtwiz_userdata_tx_in, gtwiz_userdata_rx_out, cpllrefclksel_in, drpaddr_in, drpclk_in, drpdi_in, drpen_in, drpwe_in, eyescanreset_in, eyescantrigger_in, gthrxn_in, gthrxp_in, gtrefclk0_in, gtrefclk1_in, loopback_in, pcsrsvdin_in, rx8b10ben_in, rxbufreset_in, rxcdrhold_in, rxcommadeten_in, rxdfelpmreset_in, rxlpmen_in, rxmcommaalignen_in, rxpcommaalignen_in, rxpcsreset_in, rxpd_in, rxpmareset_in, rxpolarity_in, rxprbscntreset_in, rxprbssel_in, rxrate_in, rxusrclk_in, rxusrclk2_in, tx8b10ben_in, txctrl0_in, txctrl1_in, txctrl2_in, txdiffctrl_in, txelecidle_in, txinhibit_in, txpcsreset_in, txpd_in, txpmareset_in, txpolarity_in, txpostcursor_in, txprbsforceerr_in, txprbssel_in, txprecursor_in, txusrclk_in, txusrclk2_in, cplllock_out, dmonitorout_out, drpdo_out, drprdy_out, eyescandataerror_out, gthtxn_out, gthtxp_out, gtpowergood_out, rxbufstatus_out, rxbyteisaligned_out, rxbyterealign_out, rxclkcorcnt_out, rxcommadet_out, rxctrl0_out, rxctrl1_out, rxctrl2_out, rxctrl3_out, rxoutclk_out, rxpmaresetdone_out, rxprbserr_out, rxresetdone_out, txbufstatus_out, txoutclk_out, txpmaresetdone_out, txprgdivresetdone_out, txresetdone_out); input [0:0]gtwiz_userclk_tx_active_in; input [0:0]gtwiz_userclk_rx_active_in; input [0:0]gtwiz_reset_clk_freerun_in; input [0:0]gtwiz_reset_all_in; input [0:0]gtwiz_reset_tx_pll_and_datapath_in; input [0:0]gtwiz_reset_tx_datapath_in; input [0:0]gtwiz_reset_rx_pll_and_datapath_in; input [0:0]gtwiz_reset_rx_datapath_in; output [0:0]gtwiz_reset_rx_cdr_stable_out; output [0:0]gtwiz_reset_tx_done_out; output [0:0]gtwiz_reset_rx_done_out; input [15:0]gtwiz_userdata_tx_in; output [15:0]gtwiz_userdata_rx_out; input [2:0]cpllrefclksel_in; input [8:0]drpaddr_in; input [0:0]drpclk_in; input [15:0]drpdi_in; input [0:0]drpen_in; input [0:0]drpwe_in; input [0:0]eyescanreset_in; input [0:0]eyescantrigger_in; input [0:0]gthrxn_in; input [0:0]gthrxp_in; input [0:0]gtrefclk0_in; input [0:0]gtrefclk1_in; input [2:0]loopback_in; input [15:0]pcsrsvdin_in; input [0:0]rx8b10ben_in; input [0:0]rxbufreset_in; input [0:0]rxcdrhold_in; input [0:0]rxcommadeten_in; input [0:0]rxdfelpmreset_in; input [0:0]rxlpmen_in; input [0:0]rxmcommaalignen_in; input [0:0]rxpcommaalignen_in; input [0:0]rxpcsreset_in; input [1:0]rxpd_in; input [0:0]rxpmareset_in; input [0:0]rxpolarity_in; input [0:0]rxprbscntreset_in; input [3:0]rxprbssel_in; input [2:0]rxrate_in; input [0:0]rxusrclk_in; input [0:0]rxusrclk2_in; input [0:0]tx8b10ben_in; input [15:0]txctrl0_in; input [15:0]txctrl1_in; input [7:0]txctrl2_in; input [3:0]txdiffctrl_in; input [0:0]txelecidle_in; input [0:0]txinhibit_in; input [0:0]txpcsreset_in; input [1:0]txpd_in; input [0:0]txpmareset_in; input [0:0]txpolarity_in; input [4:0]txpostcursor_in; input [0:0]txprbsforceerr_in; input [3:0]txprbssel_in; input [4:0]txprecursor_in; input [0:0]txusrclk_in; input [0:0]txusrclk2_in; output [0:0]cplllock_out; output [16:0]dmonitorout_out; output [15:0]drpdo_out; output [0:0]drprdy_out; output [0:0]eyescandataerror_out; output [0:0]gthtxn_out; output [0:0]gthtxp_out; output [0:0]gtpowergood_out; output [2:0]rxbufstatus_out; output [0:0]rxbyteisaligned_out; output [0:0]rxbyterealign_out; output [1:0]rxclkcorcnt_out; output [0:0]rxcommadet_out; output [15:0]rxctrl0_out; output [15:0]rxctrl1_out; output [7:0]rxctrl2_out; output [7:0]rxctrl3_out; output [0:0]rxoutclk_out; output [0:0]rxpmaresetdone_out; output [0:0]rxprbserr_out; output [0:0]rxresetdone_out; output [1:0]txbufstatus_out; output [0:0]txoutclk_out; output [0:0]txpmaresetdone_out; output [0:0]txprgdivresetdone_out; output [0:0]txresetdone_out; wire \ ; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire [0:0]gthrxn_in; wire [0:0]gthrxp_in; wire [0:0]gthtxn_out; wire [0:0]gthtxp_out; wire [0:0]gtpowergood_out; wire [0:0]gtrefclk0_in; wire [0:0]gtwiz_reset_all_in; wire [0:0]gtwiz_reset_rx_datapath_in; wire [0:0]gtwiz_reset_rx_done_out; wire [0:0]gtwiz_reset_tx_datapath_in; wire [0:0]gtwiz_reset_tx_done_out; wire [0:0]gtwiz_userclk_tx_active_in; wire [15:0]gtwiz_userdata_rx_out; wire [15:0]gtwiz_userdata_tx_in; wire [2:2]\^rxbufstatus_out ; wire [1:0]rxclkcorcnt_out; wire [1:0]\^rxctrl0_out ; wire [1:0]\^rxctrl1_out ; wire [1:0]\^rxctrl2_out ; wire [1:0]\^rxctrl3_out ; wire [0:0]rxmcommaalignen_in; wire [0:0]rxoutclk_out; wire [1:0]rxpd_in; wire [0:0]rxusrclk_in; wire [1:1]\^txbufstatus_out ; wire [15:0]txctrl0_in; wire [15:0]txctrl1_in; wire [7:0]txctrl2_in; wire [0:0]txelecidle_in; wire [0:0]txoutclk_out; wire [2:0]NLW_inst_bufgtce_out_UNCONNECTED; wire [2:0]NLW_inst_bufgtcemask_out_UNCONNECTED; wire [8:0]NLW_inst_bufgtdiv_out_UNCONNECTED; wire [2:0]NLW_inst_bufgtreset_out_UNCONNECTED; wire [2:0]NLW_inst_bufgtrstmask_out_UNCONNECTED; wire [0:0]NLW_inst_cpllfbclklost_out_UNCONNECTED; wire [0:0]NLW_inst_cpllrefclklost_out_UNCONNECTED; wire [16:0]NLW_inst_dmonitorout_out_UNCONNECTED; wire [0:0]NLW_inst_dmonitoroutclk_out_UNCONNECTED; wire [15:0]NLW_inst_drpdo_common_out_UNCONNECTED; wire [15:0]NLW_inst_drpdo_out_UNCONNECTED; wire [0:0]NLW_inst_drprdy_common_out_UNCONNECTED; wire [0:0]NLW_inst_drprdy_out_UNCONNECTED; wire [0:0]NLW_inst_eyescandataerror_out_UNCONNECTED; wire [0:0]NLW_inst_gtrefclkmonitor_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_buffbypass_rx_done_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_buffbypass_rx_error_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_buffbypass_tx_done_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_buffbypass_tx_error_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_reset_qpll0reset_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_reset_qpll1reset_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_rx_active_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_rx_srcclk_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_rx_usrclk2_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_rx_usrclk_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_tx_active_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_tx_srcclk_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_tx_usrclk2_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_tx_usrclk_out_UNCONNECTED; wire [0:0]NLW_inst_gtytxn_out_UNCONNECTED; wire [0:0]NLW_inst_gtytxp_out_UNCONNECTED; wire [0:0]NLW_inst_pcierategen3_out_UNCONNECTED; wire [0:0]NLW_inst_pcierateidle_out_UNCONNECTED; wire [1:0]NLW_inst_pcierateqpllpd_out_UNCONNECTED; wire [1:0]NLW_inst_pcierateqpllreset_out_UNCONNECTED; wire [0:0]NLW_inst_pciesynctxsyncdone_out_UNCONNECTED; wire [0:0]NLW_inst_pcieusergen3rdy_out_UNCONNECTED; wire [0:0]NLW_inst_pcieuserphystatusrst_out_UNCONNECTED; wire [0:0]NLW_inst_pcieuserratestart_out_UNCONNECTED; wire [11:0]NLW_inst_pcsrsvdout_out_UNCONNECTED; wire [0:0]NLW_inst_phystatus_out_UNCONNECTED; wire [7:0]NLW_inst_pinrsrvdas_out_UNCONNECTED; wire [7:0]NLW_inst_pmarsvdout0_out_UNCONNECTED; wire [7:0]NLW_inst_pmarsvdout1_out_UNCONNECTED; wire [0:0]NLW_inst_powerpresent_out_UNCONNECTED; wire [0:0]NLW_inst_qpll0fbclklost_out_UNCONNECTED; wire [0:0]NLW_inst_qpll0lock_out_UNCONNECTED; wire [0:0]NLW_inst_qpll0outclk_out_UNCONNECTED; wire [0:0]NLW_inst_qpll0outrefclk_out_UNCONNECTED; wire [0:0]NLW_inst_qpll0refclklost_out_UNCONNECTED; wire [0:0]NLW_inst_qpll1fbclklost_out_UNCONNECTED; wire [0:0]NLW_inst_qpll1lock_out_UNCONNECTED; wire [0:0]NLW_inst_qpll1outclk_out_UNCONNECTED; wire [0:0]NLW_inst_qpll1outrefclk_out_UNCONNECTED; wire [0:0]NLW_inst_qpll1refclklost_out_UNCONNECTED; wire [7:0]NLW_inst_qplldmonitor0_out_UNCONNECTED; wire [7:0]NLW_inst_qplldmonitor1_out_UNCONNECTED; wire [0:0]NLW_inst_refclkoutmonitor0_out_UNCONNECTED; wire [0:0]NLW_inst_refclkoutmonitor1_out_UNCONNECTED; wire [0:0]NLW_inst_resetexception_out_UNCONNECTED; wire [1:0]NLW_inst_rxbufstatus_out_UNCONNECTED; wire [0:0]NLW_inst_rxbyteisaligned_out_UNCONNECTED; wire [0:0]NLW_inst_rxbyterealign_out_UNCONNECTED; wire [0:0]NLW_inst_rxcdrlock_out_UNCONNECTED; wire [0:0]NLW_inst_rxcdrphdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxchanbondseq_out_UNCONNECTED; wire [0:0]NLW_inst_rxchanisaligned_out_UNCONNECTED; wire [0:0]NLW_inst_rxchanrealign_out_UNCONNECTED; wire [4:0]NLW_inst_rxchbondo_out_UNCONNECTED; wire [0:0]NLW_inst_rxckcaldone_out_UNCONNECTED; wire [0:0]NLW_inst_rxcominitdet_out_UNCONNECTED; wire [0:0]NLW_inst_rxcommadet_out_UNCONNECTED; wire [0:0]NLW_inst_rxcomsasdet_out_UNCONNECTED; wire [0:0]NLW_inst_rxcomwakedet_out_UNCONNECTED; wire [15:2]NLW_inst_rxctrl0_out_UNCONNECTED; wire [15:2]NLW_inst_rxctrl1_out_UNCONNECTED; wire [7:2]NLW_inst_rxctrl2_out_UNCONNECTED; wire [7:2]NLW_inst_rxctrl3_out_UNCONNECTED; wire [127:0]NLW_inst_rxdata_out_UNCONNECTED; wire [7:0]NLW_inst_rxdataextendrsvd_out_UNCONNECTED; wire [1:0]NLW_inst_rxdatavalid_out_UNCONNECTED; wire [0:0]NLW_inst_rxdlysresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxelecidle_out_UNCONNECTED; wire [5:0]NLW_inst_rxheader_out_UNCONNECTED; wire [1:0]NLW_inst_rxheadervalid_out_UNCONNECTED; wire [0:0]NLW_inst_rxlfpstresetdet_out_UNCONNECTED; wire [0:0]NLW_inst_rxlfpsu2lpexitdet_out_UNCONNECTED; wire [0:0]NLW_inst_rxlfpsu3wakedet_out_UNCONNECTED; wire [6:0]NLW_inst_rxmonitorout_out_UNCONNECTED; wire [0:0]NLW_inst_rxosintdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxosintstarted_out_UNCONNECTED; wire [0:0]NLW_inst_rxosintstrobedone_out_UNCONNECTED; wire [0:0]NLW_inst_rxosintstrobestarted_out_UNCONNECTED; wire [0:0]NLW_inst_rxoutclkfabric_out_UNCONNECTED; wire [0:0]NLW_inst_rxoutclkpcs_out_UNCONNECTED; wire [0:0]NLW_inst_rxphaligndone_out_UNCONNECTED; wire [0:0]NLW_inst_rxphalignerr_out_UNCONNECTED; wire [0:0]NLW_inst_rxpmaresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxprbserr_out_UNCONNECTED; wire [0:0]NLW_inst_rxprbslocked_out_UNCONNECTED; wire [0:0]NLW_inst_rxprgdivresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxqpisenn_out_UNCONNECTED; wire [0:0]NLW_inst_rxqpisenp_out_UNCONNECTED; wire [0:0]NLW_inst_rxratedone_out_UNCONNECTED; wire [1:0]NLW_inst_rxrecclk0_sel_out_UNCONNECTED; wire [0:0]NLW_inst_rxrecclk0sel_out_UNCONNECTED; wire [1:0]NLW_inst_rxrecclk1_sel_out_UNCONNECTED; wire [0:0]NLW_inst_rxrecclk1sel_out_UNCONNECTED; wire [0:0]NLW_inst_rxrecclkout_out_UNCONNECTED; wire [0:0]NLW_inst_rxresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxsliderdy_out_UNCONNECTED; wire [0:0]NLW_inst_rxslipdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxslipoutclkrdy_out_UNCONNECTED; wire [0:0]NLW_inst_rxslippmardy_out_UNCONNECTED; wire [1:0]NLW_inst_rxstartofseq_out_UNCONNECTED; wire [2:0]NLW_inst_rxstatus_out_UNCONNECTED; wire [0:0]NLW_inst_rxsyncdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxsyncout_out_UNCONNECTED; wire [0:0]NLW_inst_rxvalid_out_UNCONNECTED; wire [0:0]NLW_inst_sdm0finalout_out_UNCONNECTED; wire [0:0]NLW_inst_sdm0testdata_out_UNCONNECTED; wire [0:0]NLW_inst_sdm1finalout_out_UNCONNECTED; wire [0:0]NLW_inst_sdm1testdata_out_UNCONNECTED; wire [0:0]NLW_inst_tcongpo_out_UNCONNECTED; wire [0:0]NLW_inst_tconrsvdout0_out_UNCONNECTED; wire [0:0]NLW_inst_txbufstatus_out_UNCONNECTED; wire [0:0]NLW_inst_txcomfinish_out_UNCONNECTED; wire [0:0]NLW_inst_txdccdone_out_UNCONNECTED; wire [0:0]NLW_inst_txdlysresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_txoutclkfabric_out_UNCONNECTED; wire [0:0]NLW_inst_txoutclkpcs_out_UNCONNECTED; wire [0:0]NLW_inst_txphaligndone_out_UNCONNECTED; wire [0:0]NLW_inst_txphinitdone_out_UNCONNECTED; wire [0:0]NLW_inst_txpmaresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_txprgdivresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_txqpisenn_out_UNCONNECTED; wire [0:0]NLW_inst_txqpisenp_out_UNCONNECTED; wire [0:0]NLW_inst_txratedone_out_UNCONNECTED; wire [0:0]NLW_inst_txresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_txsyncdone_out_UNCONNECTED; wire [0:0]NLW_inst_txsyncout_out_UNCONNECTED; wire [0:0]NLW_inst_ubdaddr_out_UNCONNECTED; wire [0:0]NLW_inst_ubden_out_UNCONNECTED; wire [0:0]NLW_inst_ubdi_out_UNCONNECTED; wire [0:0]NLW_inst_ubdwe_out_UNCONNECTED; wire [0:0]NLW_inst_ubmdmtdo_out_UNCONNECTED; wire [0:0]NLW_inst_ubrsvdout_out_UNCONNECTED; wire [0:0]NLW_inst_ubtxuart_out_UNCONNECTED; assign dmonitorout_out[16] = \ ; assign dmonitorout_out[15] = \ ; assign dmonitorout_out[14] = \ ; assign dmonitorout_out[13] = \ ; assign dmonitorout_out[12] = \ ; assign dmonitorout_out[11] = \ ; assign dmonitorout_out[10] = \ ; assign dmonitorout_out[9] = \ ; assign dmonitorout_out[8] = \ ; assign dmonitorout_out[7] = \ ; assign dmonitorout_out[6] = \ ; assign dmonitorout_out[5] = \ ; assign dmonitorout_out[4] = \ ; assign dmonitorout_out[3] = \ ; assign dmonitorout_out[2] = \ ; assign dmonitorout_out[1] = \ ; assign dmonitorout_out[0] = \ ; assign drpdo_out[15] = \ ; assign drpdo_out[14] = \ ; assign drpdo_out[13] = \ ; assign drpdo_out[12] = \ ; assign drpdo_out[11] = \ ; assign drpdo_out[10] = \ ; assign drpdo_out[9] = \ ; assign drpdo_out[8] = \ ; assign drpdo_out[7] = \ ; assign drpdo_out[6] = \ ; assign drpdo_out[5] = \ ; assign drpdo_out[4] = \ ; assign drpdo_out[3] = \ ; assign drpdo_out[2] = \ ; assign drpdo_out[1] = \ ; assign drpdo_out[0] = \ ; assign drprdy_out[0] = \ ; assign eyescandataerror_out[0] = \ ; assign gtwiz_reset_rx_cdr_stable_out[0] = \ ; assign rxbufstatus_out[2] = \^rxbufstatus_out [2]; assign rxbufstatus_out[1] = \ ; assign rxbufstatus_out[0] = \ ; assign rxbyteisaligned_out[0] = \ ; assign rxbyterealign_out[0] = \ ; assign rxcommadet_out[0] = \ ; assign rxctrl0_out[15] = \ ; assign rxctrl0_out[14] = \ ; assign rxctrl0_out[13] = \ ; assign rxctrl0_out[12] = \ ; assign rxctrl0_out[11] = \ ; assign rxctrl0_out[10] = \ ; assign rxctrl0_out[9] = \ ; assign rxctrl0_out[8] = \ ; assign rxctrl0_out[7] = \ ; assign rxctrl0_out[6] = \ ; assign rxctrl0_out[5] = \ ; assign rxctrl0_out[4] = \ ; assign rxctrl0_out[3] = \ ; assign rxctrl0_out[2] = \ ; assign rxctrl0_out[1:0] = \^rxctrl0_out [1:0]; assign rxctrl1_out[15] = \ ; assign rxctrl1_out[14] = \ ; assign rxctrl1_out[13] = \ ; assign rxctrl1_out[12] = \ ; assign rxctrl1_out[11] = \ ; assign rxctrl1_out[10] = \ ; assign rxctrl1_out[9] = \ ; assign rxctrl1_out[8] = \ ; assign rxctrl1_out[7] = \ ; assign rxctrl1_out[6] = \ ; assign rxctrl1_out[5] = \ ; assign rxctrl1_out[4] = \ ; assign rxctrl1_out[3] = \ ; assign rxctrl1_out[2] = \ ; assign rxctrl1_out[1:0] = \^rxctrl1_out [1:0]; assign rxctrl2_out[7] = \ ; assign rxctrl2_out[6] = \ ; assign rxctrl2_out[5] = \ ; assign rxctrl2_out[4] = \ ; assign rxctrl2_out[3] = \ ; assign rxctrl2_out[2] = \ ; assign rxctrl2_out[1:0] = \^rxctrl2_out [1:0]; assign rxctrl3_out[7] = \ ; assign rxctrl3_out[6] = \ ; assign rxctrl3_out[5] = \ ; assign rxctrl3_out[4] = \ ; assign rxctrl3_out[3] = \ ; assign rxctrl3_out[2] = \ ; assign rxctrl3_out[1:0] = \^rxctrl3_out [1:0]; assign rxpmaresetdone_out[0] = \ ; assign rxprbserr_out[0] = \ ; assign rxresetdone_out[0] = \ ; assign txbufstatus_out[1] = \^txbufstatus_out [1]; assign txbufstatus_out[0] = \ ; assign txpmaresetdone_out[0] = \ ; assign txprgdivresetdone_out[0] = \ ; assign txresetdone_out[0] = \ ; GND GND (.G(\ )); (* C_CHANNEL_ENABLE = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_COMMON_SCALING_FACTOR = "1" *) (* C_CPLL_VCO_FREQUENCY = "2500.000000" *) (* C_ENABLE_COMMON_USRCLK = "0" *) (* C_FORCE_COMMONS = "0" *) (* C_FREERUN_FREQUENCY = "50.000000" *) (* C_GT_REV = "17" *) (* C_GT_TYPE = "0" *) (* C_INCLUDE_CPLL_CAL = "2" *) (* C_LOCATE_COMMON = "0" *) (* C_LOCATE_IN_SYSTEM_IBERT_CORE = "2" *) (* C_LOCATE_RESET_CONTROLLER = "0" *) (* C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER = "0" *) (* C_LOCATE_RX_USER_CLOCKING = "1" *) (* C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER = "0" *) (* C_LOCATE_TX_USER_CLOCKING = "1" *) (* C_LOCATE_USER_DATA_WIDTH_SIZING = "0" *) (* C_PCIE_CORECLK_FREQ = "250" *) (* C_PCIE_ENABLE = "0" *) (* C_RESET_CONTROLLER_INSTANCE_CTRL = "0" *) (* C_RESET_SEQUENCE_INTERVAL = "0" *) (* C_RX_BUFFBYPASS_MODE = "0" *) (* C_RX_BUFFER_BYPASS_INSTANCE_CTRL = "0" *) (* C_RX_BUFFER_MODE = "1" *) (* C_RX_CB_DISP = "8'b00000000" *) (* C_RX_CB_K = "8'b00000000" *) (* C_RX_CB_LEN_SEQ = "1" *) (* C_RX_CB_MAX_LEVEL = "1" *) (* C_RX_CB_NUM_SEQ = "0" *) (* C_RX_CB_VAL = "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_RX_CC_DISP = "8'b00000000" *) (* C_RX_CC_ENABLE = "1" *) (* C_RX_CC_K = "8'b00010001" *) (* C_RX_CC_LEN_SEQ = "2" *) (* C_RX_CC_NUM_SEQ = "2" *) (* C_RX_CC_PERIODICITY = "5000" *) (* C_RX_CC_VAL = "80'b00000000000000000000001011010100101111000000000000000000000000010100000010111100" *) (* C_RX_COMMA_M_ENABLE = "1" *) (* C_RX_COMMA_M_VAL = "10'b1010000011" *) (* C_RX_COMMA_P_ENABLE = "1" *) (* C_RX_COMMA_P_VAL = "10'b0101111100" *) (* C_RX_DATA_DECODING = "1" *) (* C_RX_ENABLE = "1" *) (* C_RX_INT_DATA_WIDTH = "20" *) (* C_RX_LINE_RATE = "1.250000" *) (* C_RX_MASTER_CHANNEL_IDX = "96" *) (* C_RX_OUTCLK_BUFG_GT_DIV = "1" *) (* C_RX_OUTCLK_FREQUENCY = "62.500000" *) (* C_RX_OUTCLK_SOURCE = "1" *) (* C_RX_PLL_TYPE = "2" *) (* C_RX_RECCLK_OUTPUT = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_RX_REFCLK_FREQUENCY = "125.000000" *) (* C_RX_SLIDE_MODE = "0" *) (* C_RX_USER_CLOCKING_CONTENTS = "0" *) (* C_RX_USER_CLOCKING_INSTANCE_CTRL = "0" *) (* C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK = "1" *) (* C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 = "1" *) (* C_RX_USER_CLOCKING_SOURCE = "0" *) (* C_RX_USER_DATA_WIDTH = "16" *) (* C_RX_USRCLK2_FREQUENCY = "62.500000" *) (* C_RX_USRCLK_FREQUENCY = "62.500000" *) (* C_SECONDARY_QPLL_ENABLE = "0" *) (* C_SECONDARY_QPLL_REFCLK_FREQUENCY = "257.812500" *) (* C_SIM_CPLL_CAL_BYPASS = "1" *) (* C_TOTAL_NUM_CHANNELS = "1" *) (* C_TOTAL_NUM_COMMONS = "0" *) (* C_TOTAL_NUM_COMMONS_EXAMPLE = "0" *) (* C_TXPROGDIV_FREQ_ENABLE = "1" *) (* C_TXPROGDIV_FREQ_SOURCE = "2" *) (* C_TXPROGDIV_FREQ_VAL = "125.000000" *) (* C_TX_BUFFBYPASS_MODE = "0" *) (* C_TX_BUFFER_BYPASS_INSTANCE_CTRL = "0" *) (* C_TX_BUFFER_MODE = "1" *) (* C_TX_DATA_ENCODING = "1" *) (* C_TX_ENABLE = "1" *) (* C_TX_INT_DATA_WIDTH = "20" *) (* C_TX_LINE_RATE = "1.250000" *) (* C_TX_MASTER_CHANNEL_IDX = "96" *) (* C_TX_OUTCLK_BUFG_GT_DIV = "2" *) (* C_TX_OUTCLK_FREQUENCY = "62.500000" *) (* C_TX_OUTCLK_SOURCE = "4" *) (* C_TX_PLL_TYPE = "2" *) (* C_TX_REFCLK_FREQUENCY = "125.000000" *) (* C_TX_USER_CLOCKING_CONTENTS = "0" *) (* C_TX_USER_CLOCKING_INSTANCE_CTRL = "0" *) (* C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK = "1" *) (* C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 = "1" *) (* C_TX_USER_CLOCKING_SOURCE = "0" *) (* C_TX_USER_DATA_WIDTH = "16" *) (* C_TX_USRCLK2_FREQUENCY = "62.500000" *) (* C_TX_USRCLK_FREQUENCY = "62.500000" *) (* C_USER_GTPOWERGOOD_DELAY_EN = "0" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_gt_gtwizard_top inst (.bgbypassb_in(1'b1), .bgmonitorenb_in(1'b1), .bgpdb_in(1'b1), .bgrcalovrd_in({1'b1,1'b1,1'b1,1'b1,1'b1}), .bgrcalovrdenb_in(1'b1), .bufgtce_out(NLW_inst_bufgtce_out_UNCONNECTED[2:0]), .bufgtcemask_out(NLW_inst_bufgtcemask_out_UNCONNECTED[2:0]), .bufgtdiv_out(NLW_inst_bufgtdiv_out_UNCONNECTED[8:0]), .bufgtreset_out(NLW_inst_bufgtreset_out_UNCONNECTED[2:0]), .bufgtrstmask_out(NLW_inst_bufgtrstmask_out_UNCONNECTED[2:0]), .cdrstepdir_in(1'b0), .cdrstepsq_in(1'b0), .cdrstepsx_in(1'b0), .cfgreset_in(1'b0), .clkrsvd0_in(1'b0), .clkrsvd1_in(1'b0), .cpllfbclklost_out(NLW_inst_cpllfbclklost_out_UNCONNECTED[0]), .cpllfreqlock_in(1'b0), .cplllock_out(cplllock_out), .cplllockdetclk_in(1'b0), .cplllocken_in(1'b1), .cpllpd_in(1'b0), .cpllrefclklost_out(NLW_inst_cpllrefclklost_out_UNCONNECTED[0]), .cpllrefclksel_in({1'b0,1'b0,1'b1}), .cpllreset_in(1'b0), .dmonfiforeset_in(1'b0), .dmonitorclk_in(1'b0), .dmonitorout_out(NLW_inst_dmonitorout_out_UNCONNECTED[16:0]), .dmonitoroutclk_out(NLW_inst_dmonitoroutclk_out_UNCONNECTED[0]), .drpaddr_common_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drpaddr_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drpclk_common_in(1'b0), .drpclk_in(drpclk_in), .drpdi_common_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drpdi_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drpdo_common_out(NLW_inst_drpdo_common_out_UNCONNECTED[15:0]), .drpdo_out(NLW_inst_drpdo_out_UNCONNECTED[15:0]), .drpen_common_in(1'b0), .drpen_in(1'b0), .drprdy_common_out(NLW_inst_drprdy_common_out_UNCONNECTED[0]), .drprdy_out(NLW_inst_drprdy_out_UNCONNECTED[0]), .drprst_in(1'b0), .drpwe_common_in(1'b0), .drpwe_in(1'b0), .elpcaldvorwren_in(1'b0), .elpcalpaorwren_in(1'b0), .evoddphicaldone_in(1'b0), .evoddphicalstart_in(1'b0), .evoddphidrden_in(1'b0), .evoddphidwren_in(1'b0), .evoddphixrden_in(1'b0), .evoddphixwren_in(1'b0), .eyescandataerror_out(NLW_inst_eyescandataerror_out_UNCONNECTED[0]), .eyescanmode_in(1'b0), .eyescanreset_in(1'b0), .eyescantrigger_in(1'b0), .freqos_in(1'b0), .gtgrefclk0_in(1'b0), .gtgrefclk1_in(1'b0), .gtgrefclk_in(1'b0), .gthrxn_in(gthrxn_in), .gthrxp_in(gthrxp_in), .gthtxn_out(gthtxn_out), .gthtxp_out(gthtxp_out), .gtnorthrefclk00_in(1'b0), .gtnorthrefclk01_in(1'b0), .gtnorthrefclk0_in(1'b0), .gtnorthrefclk10_in(1'b0), .gtnorthrefclk11_in(1'b0), .gtnorthrefclk1_in(1'b0), .gtpowergood_out(gtpowergood_out), .gtrefclk00_in(1'b0), .gtrefclk01_in(1'b0), .gtrefclk0_in(gtrefclk0_in), .gtrefclk10_in(1'b0), .gtrefclk11_in(1'b0), .gtrefclk1_in(1'b0), .gtrefclkmonitor_out(NLW_inst_gtrefclkmonitor_out_UNCONNECTED[0]), .gtresetsel_in(1'b0), .gtrsvd_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtrxreset_in(1'b0), .gtrxresetsel_in(1'b0), .gtsouthrefclk00_in(1'b0), .gtsouthrefclk01_in(1'b0), .gtsouthrefclk0_in(1'b0), .gtsouthrefclk10_in(1'b0), .gtsouthrefclk11_in(1'b0), .gtsouthrefclk1_in(1'b0), .gttxreset_in(1'b0), .gttxresetsel_in(1'b0), .gtwiz_buffbypass_rx_done_out(NLW_inst_gtwiz_buffbypass_rx_done_out_UNCONNECTED[0]), .gtwiz_buffbypass_rx_error_out(NLW_inst_gtwiz_buffbypass_rx_error_out_UNCONNECTED[0]), .gtwiz_buffbypass_rx_reset_in(1'b0), .gtwiz_buffbypass_rx_start_user_in(1'b0), .gtwiz_buffbypass_tx_done_out(NLW_inst_gtwiz_buffbypass_tx_done_out_UNCONNECTED[0]), .gtwiz_buffbypass_tx_error_out(NLW_inst_gtwiz_buffbypass_tx_error_out_UNCONNECTED[0]), .gtwiz_buffbypass_tx_reset_in(1'b0), .gtwiz_buffbypass_tx_start_user_in(1'b0), .gtwiz_gthe3_cpll_cal_bufg_ce_in(1'b0), .gtwiz_gthe3_cpll_cal_cnt_tol_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_gthe3_cpll_cal_txoutclk_period_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_gthe4_cpll_cal_bufg_ce_in(1'b0), .gtwiz_gthe4_cpll_cal_cnt_tol_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_gthe4_cpll_cal_txoutclk_period_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_gtye4_cpll_cal_bufg_ce_in(1'b0), .gtwiz_gtye4_cpll_cal_cnt_tol_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_gtye4_cpll_cal_txoutclk_period_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_reset_all_in(gtwiz_reset_all_in), .gtwiz_reset_clk_freerun_in(1'b0), .gtwiz_reset_qpll0lock_in(1'b0), .gtwiz_reset_qpll0reset_out(NLW_inst_gtwiz_reset_qpll0reset_out_UNCONNECTED[0]), .gtwiz_reset_qpll1lock_in(1'b0), .gtwiz_reset_qpll1reset_out(NLW_inst_gtwiz_reset_qpll1reset_out_UNCONNECTED[0]), .gtwiz_reset_rx_cdr_stable_out(NLW_inst_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED[0]), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), .gtwiz_reset_rx_done_in(1'b0), .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out), .gtwiz_reset_rx_pll_and_datapath_in(1'b0), .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in), .gtwiz_reset_tx_done_in(1'b0), .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out), .gtwiz_reset_tx_pll_and_datapath_in(1'b0), .gtwiz_userclk_rx_active_in(1'b0), .gtwiz_userclk_rx_active_out(NLW_inst_gtwiz_userclk_rx_active_out_UNCONNECTED[0]), .gtwiz_userclk_rx_reset_in(1'b0), .gtwiz_userclk_rx_srcclk_out(NLW_inst_gtwiz_userclk_rx_srcclk_out_UNCONNECTED[0]), .gtwiz_userclk_rx_usrclk2_out(NLW_inst_gtwiz_userclk_rx_usrclk2_out_UNCONNECTED[0]), .gtwiz_userclk_rx_usrclk_out(NLW_inst_gtwiz_userclk_rx_usrclk_out_UNCONNECTED[0]), .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in), .gtwiz_userclk_tx_active_out(NLW_inst_gtwiz_userclk_tx_active_out_UNCONNECTED[0]), .gtwiz_userclk_tx_reset_in(1'b0), .gtwiz_userclk_tx_srcclk_out(NLW_inst_gtwiz_userclk_tx_srcclk_out_UNCONNECTED[0]), .gtwiz_userclk_tx_usrclk2_out(NLW_inst_gtwiz_userclk_tx_usrclk2_out_UNCONNECTED[0]), .gtwiz_userclk_tx_usrclk_out(NLW_inst_gtwiz_userclk_tx_usrclk_out_UNCONNECTED[0]), .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out), .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in), .gtyrxn_in(1'b0), .gtyrxp_in(1'b0), .gtytxn_out(NLW_inst_gtytxn_out_UNCONNECTED[0]), .gtytxp_out(NLW_inst_gtytxp_out_UNCONNECTED[0]), .incpctrl_in(1'b0), .loopback_in({1'b0,1'b0,1'b0}), .looprsvd_in(1'b0), .lpbkrxtxseren_in(1'b0), .lpbktxrxseren_in(1'b0), .pcieeqrxeqadaptdone_in(1'b0), .pcierategen3_out(NLW_inst_pcierategen3_out_UNCONNECTED[0]), .pcierateidle_out(NLW_inst_pcierateidle_out_UNCONNECTED[0]), .pcierateqpll0_in(1'b0), .pcierateqpll1_in(1'b0), .pcierateqpllpd_out(NLW_inst_pcierateqpllpd_out_UNCONNECTED[1:0]), .pcierateqpllreset_out(NLW_inst_pcierateqpllreset_out_UNCONNECTED[1:0]), .pcierstidle_in(1'b0), .pciersttxsyncstart_in(1'b0), .pciesynctxsyncdone_out(NLW_inst_pciesynctxsyncdone_out_UNCONNECTED[0]), .pcieusergen3rdy_out(NLW_inst_pcieusergen3rdy_out_UNCONNECTED[0]), .pcieuserphystatusrst_out(NLW_inst_pcieuserphystatusrst_out_UNCONNECTED[0]), .pcieuserratedone_in(1'b0), .pcieuserratestart_out(NLW_inst_pcieuserratestart_out_UNCONNECTED[0]), .pcsrsvdin2_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .pcsrsvdin_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .pcsrsvdout_out(NLW_inst_pcsrsvdout_out_UNCONNECTED[11:0]), .phystatus_out(NLW_inst_phystatus_out_UNCONNECTED[0]), .pinrsrvdas_out(NLW_inst_pinrsrvdas_out_UNCONNECTED[7:0]), .pmarsvd0_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .pmarsvd1_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .pmarsvdin_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .pmarsvdout0_out(NLW_inst_pmarsvdout0_out_UNCONNECTED[7:0]), .pmarsvdout1_out(NLW_inst_pmarsvdout1_out_UNCONNECTED[7:0]), .powerpresent_out(NLW_inst_powerpresent_out_UNCONNECTED[0]), .qpll0clk_in(1'b0), .qpll0clkrsvd0_in(1'b0), .qpll0clkrsvd1_in(1'b0), .qpll0fbclklost_out(NLW_inst_qpll0fbclklost_out_UNCONNECTED[0]), .qpll0fbdiv_in(1'b0), .qpll0freqlock_in(1'b0), .qpll0lock_out(NLW_inst_qpll0lock_out_UNCONNECTED[0]), .qpll0lockdetclk_in(1'b0), .qpll0locken_in(1'b0), .qpll0outclk_out(NLW_inst_qpll0outclk_out_UNCONNECTED[0]), .qpll0outrefclk_out(NLW_inst_qpll0outrefclk_out_UNCONNECTED[0]), .qpll0pd_in(1'b1), .qpll0refclk_in(1'b0), .qpll0refclklost_out(NLW_inst_qpll0refclklost_out_UNCONNECTED[0]), .qpll0refclksel_in({1'b0,1'b0,1'b1}), .qpll0reset_in(1'b1), .qpll1clk_in(1'b0), .qpll1clkrsvd0_in(1'b0), .qpll1clkrsvd1_in(1'b0), .qpll1fbclklost_out(NLW_inst_qpll1fbclklost_out_UNCONNECTED[0]), .qpll1fbdiv_in(1'b0), .qpll1freqlock_in(1'b0), .qpll1lock_out(NLW_inst_qpll1lock_out_UNCONNECTED[0]), .qpll1lockdetclk_in(1'b0), .qpll1locken_in(1'b0), .qpll1outclk_out(NLW_inst_qpll1outclk_out_UNCONNECTED[0]), .qpll1outrefclk_out(NLW_inst_qpll1outrefclk_out_UNCONNECTED[0]), .qpll1pd_in(1'b1), .qpll1refclk_in(1'b0), .qpll1refclklost_out(NLW_inst_qpll1refclklost_out_UNCONNECTED[0]), .qpll1refclksel_in({1'b0,1'b0,1'b1}), .qpll1reset_in(1'b1), .qplldmonitor0_out(NLW_inst_qplldmonitor0_out_UNCONNECTED[7:0]), .qplldmonitor1_out(NLW_inst_qplldmonitor1_out_UNCONNECTED[7:0]), .qpllrsvd1_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .qpllrsvd2_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .qpllrsvd3_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .qpllrsvd4_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rcalenb_in(1'b1), .refclkoutmonitor0_out(NLW_inst_refclkoutmonitor0_out_UNCONNECTED[0]), .refclkoutmonitor1_out(NLW_inst_refclkoutmonitor1_out_UNCONNECTED[0]), .resetexception_out(NLW_inst_resetexception_out_UNCONNECTED[0]), .resetovrd_in(1'b0), .rstclkentx_in(1'b0), .rx8b10ben_in(1'b1), .rxafecfoken_in(1'b0), .rxbufreset_in(1'b0), .rxbufstatus_out({\^rxbufstatus_out ,NLW_inst_rxbufstatus_out_UNCONNECTED[1:0]}), .rxbyteisaligned_out(NLW_inst_rxbyteisaligned_out_UNCONNECTED[0]), .rxbyterealign_out(NLW_inst_rxbyterealign_out_UNCONNECTED[0]), .rxcdrfreqreset_in(1'b0), .rxcdrhold_in(1'b0), .rxcdrlock_out(NLW_inst_rxcdrlock_out_UNCONNECTED[0]), .rxcdrovrden_in(1'b0), .rxcdrphdone_out(NLW_inst_rxcdrphdone_out_UNCONNECTED[0]), .rxcdrreset_in(1'b0), .rxcdrresetrsv_in(1'b0), .rxchanbondseq_out(NLW_inst_rxchanbondseq_out_UNCONNECTED[0]), .rxchanisaligned_out(NLW_inst_rxchanisaligned_out_UNCONNECTED[0]), .rxchanrealign_out(NLW_inst_rxchanrealign_out_UNCONNECTED[0]), .rxchbonden_in(1'b0), .rxchbondi_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .rxchbondlevel_in({1'b0,1'b0,1'b0}), .rxchbondmaster_in(1'b0), .rxchbondo_out(NLW_inst_rxchbondo_out_UNCONNECTED[4:0]), .rxchbondslave_in(1'b0), .rxckcaldone_out(NLW_inst_rxckcaldone_out_UNCONNECTED[0]), .rxckcalreset_in(1'b0), .rxckcalstart_in(1'b0), .rxclkcorcnt_out(rxclkcorcnt_out), .rxcominitdet_out(NLW_inst_rxcominitdet_out_UNCONNECTED[0]), .rxcommadet_out(NLW_inst_rxcommadet_out_UNCONNECTED[0]), .rxcommadeten_in(1'b1), .rxcomsasdet_out(NLW_inst_rxcomsasdet_out_UNCONNECTED[0]), .rxcomwakedet_out(NLW_inst_rxcomwakedet_out_UNCONNECTED[0]), .rxctrl0_out({NLW_inst_rxctrl0_out_UNCONNECTED[15:2],\^rxctrl0_out }), .rxctrl1_out({NLW_inst_rxctrl1_out_UNCONNECTED[15:2],\^rxctrl1_out }), .rxctrl2_out({NLW_inst_rxctrl2_out_UNCONNECTED[7:2],\^rxctrl2_out }), .rxctrl3_out({NLW_inst_rxctrl3_out_UNCONNECTED[7:2],\^rxctrl3_out }), .rxdata_out(NLW_inst_rxdata_out_UNCONNECTED[127:0]), .rxdataextendrsvd_out(NLW_inst_rxdataextendrsvd_out_UNCONNECTED[7:0]), .rxdatavalid_out(NLW_inst_rxdatavalid_out_UNCONNECTED[1:0]), .rxdccforcestart_in(1'b0), .rxdfeagcctrl_in({1'b0,1'b1}), .rxdfeagchold_in(1'b0), .rxdfeagcovrden_in(1'b0), .rxdfecfokfcnum_in(1'b0), .rxdfecfokfen_in(1'b0), .rxdfecfokfpulse_in(1'b0), .rxdfecfokhold_in(1'b0), .rxdfecfokovren_in(1'b0), .rxdfekhhold_in(1'b0), .rxdfekhovrden_in(1'b0), .rxdfelfhold_in(1'b0), .rxdfelfovrden_in(1'b0), .rxdfelpmreset_in(1'b0), .rxdfetap10hold_in(1'b0), .rxdfetap10ovrden_in(1'b0), .rxdfetap11hold_in(1'b0), .rxdfetap11ovrden_in(1'b0), .rxdfetap12hold_in(1'b0), .rxdfetap12ovrden_in(1'b0), .rxdfetap13hold_in(1'b0), .rxdfetap13ovrden_in(1'b0), .rxdfetap14hold_in(1'b0), .rxdfetap14ovrden_in(1'b0), .rxdfetap15hold_in(1'b0), .rxdfetap15ovrden_in(1'b0), .rxdfetap2hold_in(1'b0), .rxdfetap2ovrden_in(1'b0), .rxdfetap3hold_in(1'b0), .rxdfetap3ovrden_in(1'b0), .rxdfetap4hold_in(1'b0), .rxdfetap4ovrden_in(1'b0), .rxdfetap5hold_in(1'b0), .rxdfetap5ovrden_in(1'b0), .rxdfetap6hold_in(1'b0), .rxdfetap6ovrden_in(1'b0), .rxdfetap7hold_in(1'b0), .rxdfetap7ovrden_in(1'b0), .rxdfetap8hold_in(1'b0), .rxdfetap8ovrden_in(1'b0), .rxdfetap9hold_in(1'b0), .rxdfetap9ovrden_in(1'b0), .rxdfeuthold_in(1'b0), .rxdfeutovrden_in(1'b0), .rxdfevphold_in(1'b0), .rxdfevpovrden_in(1'b0), .rxdfevsen_in(1'b0), .rxdfexyden_in(1'b1), .rxdlybypass_in(1'b1), .rxdlyen_in(1'b0), .rxdlyovrden_in(1'b0), .rxdlysreset_in(1'b0), .rxdlysresetdone_out(NLW_inst_rxdlysresetdone_out_UNCONNECTED[0]), .rxelecidle_out(NLW_inst_rxelecidle_out_UNCONNECTED[0]), .rxelecidlemode_in({1'b1,1'b1}), .rxeqtraining_in(1'b0), .rxgearboxslip_in(1'b0), .rxheader_out(NLW_inst_rxheader_out_UNCONNECTED[5:0]), .rxheadervalid_out(NLW_inst_rxheadervalid_out_UNCONNECTED[1:0]), .rxlatclk_in(1'b0), .rxlfpstresetdet_out(NLW_inst_rxlfpstresetdet_out_UNCONNECTED[0]), .rxlfpsu2lpexitdet_out(NLW_inst_rxlfpsu2lpexitdet_out_UNCONNECTED[0]), .rxlfpsu3wakedet_out(NLW_inst_rxlfpsu3wakedet_out_UNCONNECTED[0]), .rxlpmen_in(1'b1), .rxlpmgchold_in(1'b0), .rxlpmgcovrden_in(1'b0), .rxlpmhfhold_in(1'b0), .rxlpmhfovrden_in(1'b0), .rxlpmlfhold_in(1'b0), .rxlpmlfklovrden_in(1'b0), .rxlpmoshold_in(1'b0), .rxlpmosovrden_in(1'b0), .rxmcommaalignen_in(rxmcommaalignen_in), .rxmonitorout_out(NLW_inst_rxmonitorout_out_UNCONNECTED[6:0]), .rxmonitorsel_in({1'b0,1'b0}), .rxoobreset_in(1'b0), .rxoscalreset_in(1'b0), .rxoshold_in(1'b0), .rxosintcfg_in({1'b1,1'b1,1'b0,1'b1}), .rxosintdone_out(NLW_inst_rxosintdone_out_UNCONNECTED[0]), .rxosinten_in(1'b1), .rxosinthold_in(1'b0), .rxosintovrden_in(1'b0), .rxosintstarted_out(NLW_inst_rxosintstarted_out_UNCONNECTED[0]), .rxosintstrobe_in(1'b0), .rxosintstrobedone_out(NLW_inst_rxosintstrobedone_out_UNCONNECTED[0]), .rxosintstrobestarted_out(NLW_inst_rxosintstrobestarted_out_UNCONNECTED[0]), .rxosinttestovrden_in(1'b0), .rxosovrden_in(1'b0), .rxoutclk_out(rxoutclk_out), .rxoutclkfabric_out(NLW_inst_rxoutclkfabric_out_UNCONNECTED[0]), .rxoutclkpcs_out(NLW_inst_rxoutclkpcs_out_UNCONNECTED[0]), .rxoutclksel_in({1'b0,1'b1,1'b0}), .rxpcommaalignen_in(1'b0), .rxpcsreset_in(1'b0), .rxpd_in({rxpd_in[1],1'b0}), .rxphalign_in(1'b0), .rxphaligndone_out(NLW_inst_rxphaligndone_out_UNCONNECTED[0]), .rxphalignen_in(1'b0), .rxphalignerr_out(NLW_inst_rxphalignerr_out_UNCONNECTED[0]), .rxphdlypd_in(1'b1), .rxphdlyreset_in(1'b0), .rxphovrden_in(1'b0), .rxpllclksel_in({1'b0,1'b0}), .rxpmareset_in(1'b0), .rxpmaresetdone_out(NLW_inst_rxpmaresetdone_out_UNCONNECTED[0]), .rxpolarity_in(1'b0), .rxprbscntreset_in(1'b0), .rxprbserr_out(NLW_inst_rxprbserr_out_UNCONNECTED[0]), .rxprbslocked_out(NLW_inst_rxprbslocked_out_UNCONNECTED[0]), .rxprbssel_in({1'b0,1'b0,1'b0,1'b0}), .rxprgdivresetdone_out(NLW_inst_rxprgdivresetdone_out_UNCONNECTED[0]), .rxprogdivreset_in(1'b0), .rxqpien_in(1'b0), .rxqpisenn_out(NLW_inst_rxqpisenn_out_UNCONNECTED[0]), .rxqpisenp_out(NLW_inst_rxqpisenp_out_UNCONNECTED[0]), .rxrate_in({1'b0,1'b0,1'b0}), .rxratedone_out(NLW_inst_rxratedone_out_UNCONNECTED[0]), .rxratemode_in(1'b0), .rxrecclk0_sel_out(NLW_inst_rxrecclk0_sel_out_UNCONNECTED[1:0]), .rxrecclk0sel_out(NLW_inst_rxrecclk0sel_out_UNCONNECTED[0]), .rxrecclk1_sel_out(NLW_inst_rxrecclk1_sel_out_UNCONNECTED[1:0]), .rxrecclk1sel_out(NLW_inst_rxrecclk1sel_out_UNCONNECTED[0]), .rxrecclkout_out(NLW_inst_rxrecclkout_out_UNCONNECTED[0]), .rxresetdone_out(NLW_inst_rxresetdone_out_UNCONNECTED[0]), .rxslide_in(1'b0), .rxsliderdy_out(NLW_inst_rxsliderdy_out_UNCONNECTED[0]), .rxslipdone_out(NLW_inst_rxslipdone_out_UNCONNECTED[0]), .rxslipoutclk_in(1'b0), .rxslipoutclkrdy_out(NLW_inst_rxslipoutclkrdy_out_UNCONNECTED[0]), .rxslippma_in(1'b0), .rxslippmardy_out(NLW_inst_rxslippmardy_out_UNCONNECTED[0]), .rxstartofseq_out(NLW_inst_rxstartofseq_out_UNCONNECTED[1:0]), .rxstatus_out(NLW_inst_rxstatus_out_UNCONNECTED[2:0]), .rxsyncallin_in(1'b0), .rxsyncdone_out(NLW_inst_rxsyncdone_out_UNCONNECTED[0]), .rxsyncin_in(1'b0), .rxsyncmode_in(1'b0), .rxsyncout_out(NLW_inst_rxsyncout_out_UNCONNECTED[0]), .rxsysclksel_in({1'b0,1'b0}), .rxtermination_in(1'b0), .rxuserrdy_in(1'b1), .rxusrclk2_in(1'b0), .rxusrclk_in(rxusrclk_in), .rxvalid_out(NLW_inst_rxvalid_out_UNCONNECTED[0]), .sdm0data_in(1'b0), .sdm0finalout_out(NLW_inst_sdm0finalout_out_UNCONNECTED[0]), .sdm0reset_in(1'b0), .sdm0testdata_out(NLW_inst_sdm0testdata_out_UNCONNECTED[0]), .sdm0toggle_in(1'b0), .sdm0width_in(1'b0), .sdm1data_in(1'b0), .sdm1finalout_out(NLW_inst_sdm1finalout_out_UNCONNECTED[0]), .sdm1reset_in(1'b0), .sdm1testdata_out(NLW_inst_sdm1testdata_out_UNCONNECTED[0]), .sdm1toggle_in(1'b0), .sdm1width_in(1'b0), .sigvalidclk_in(1'b0), .tcongpi_in(1'b0), .tcongpo_out(NLW_inst_tcongpo_out_UNCONNECTED[0]), .tconpowerup_in(1'b0), .tconreset_in(1'b0), .tconrsvdin1_in(1'b0), .tconrsvdout0_out(NLW_inst_tconrsvdout0_out_UNCONNECTED[0]), .tstin_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .tx8b10bbypass_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .tx8b10ben_in(1'b1), .txbufdiffctrl_in({1'b0,1'b0,1'b0}), .txbufstatus_out({\^txbufstatus_out ,NLW_inst_txbufstatus_out_UNCONNECTED[0]}), .txcomfinish_out(NLW_inst_txcomfinish_out_UNCONNECTED[0]), .txcominit_in(1'b0), .txcomsas_in(1'b0), .txcomwake_in(1'b0), .txctrl0_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txctrl0_in[1:0]}), .txctrl1_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txctrl1_in[1:0]}), .txctrl2_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txctrl2_in[1:0]}), .txdata_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .txdataextendrsvd_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .txdccdone_out(NLW_inst_txdccdone_out_UNCONNECTED[0]), .txdccforcestart_in(1'b0), .txdccreset_in(1'b0), .txdeemph_in(1'b0), .txdetectrx_in(1'b0), .txdiffctrl_in({1'b1,1'b0,1'b0,1'b0}), .txdiffpd_in(1'b0), .txdlybypass_in(1'b1), .txdlyen_in(1'b0), .txdlyhold_in(1'b0), .txdlyovrden_in(1'b0), .txdlysreset_in(1'b0), .txdlysresetdone_out(NLW_inst_txdlysresetdone_out_UNCONNECTED[0]), .txdlyupdown_in(1'b0), .txelecidle_in(txelecidle_in), .txelforcestart_in(1'b0), .txheader_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .txinhibit_in(1'b0), .txlatclk_in(1'b0), .txlfpstreset_in(1'b0), .txlfpsu2lpexit_in(1'b0), .txlfpsu3wake_in(1'b0), .txmaincursor_in({1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .txmargin_in({1'b0,1'b0,1'b0}), .txmuxdcdexhold_in(1'b0), .txmuxdcdorwren_in(1'b0), .txoneszeros_in(1'b0), .txoutclk_out(txoutclk_out), .txoutclkfabric_out(NLW_inst_txoutclkfabric_out_UNCONNECTED[0]), .txoutclkpcs_out(NLW_inst_txoutclkpcs_out_UNCONNECTED[0]), .txoutclksel_in({1'b1,1'b0,1'b1}), .txpcsreset_in(1'b0), .txpd_in({1'b0,1'b0}), .txpdelecidlemode_in(1'b0), .txphalign_in(1'b0), .txphaligndone_out(NLW_inst_txphaligndone_out_UNCONNECTED[0]), .txphalignen_in(1'b0), .txphdlypd_in(1'b1), .txphdlyreset_in(1'b0), .txphdlytstclk_in(1'b0), .txphinit_in(1'b0), .txphinitdone_out(NLW_inst_txphinitdone_out_UNCONNECTED[0]), .txphovrden_in(1'b0), .txpippmen_in(1'b0), .txpippmovrden_in(1'b0), .txpippmpd_in(1'b0), .txpippmsel_in(1'b0), .txpippmstepsize_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .txpisopd_in(1'b0), .txpllclksel_in({1'b0,1'b0}), .txpmareset_in(1'b0), .txpmaresetdone_out(NLW_inst_txpmaresetdone_out_UNCONNECTED[0]), .txpolarity_in(1'b0), .txpostcursor_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .txpostcursorinv_in(1'b0), .txprbsforceerr_in(1'b0), .txprbssel_in({1'b0,1'b0,1'b0,1'b0}), .txprecursor_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .txprecursorinv_in(1'b0), .txprgdivresetdone_out(NLW_inst_txprgdivresetdone_out_UNCONNECTED[0]), .txprogdivreset_in(1'b0), .txqpibiasen_in(1'b0), .txqpisenn_out(NLW_inst_txqpisenn_out_UNCONNECTED[0]), .txqpisenp_out(NLW_inst_txqpisenp_out_UNCONNECTED[0]), .txqpistrongpdown_in(1'b0), .txqpiweakpup_in(1'b0), .txrate_in({1'b0,1'b0,1'b0}), .txratedone_out(NLW_inst_txratedone_out_UNCONNECTED[0]), .txratemode_in(1'b0), .txresetdone_out(NLW_inst_txresetdone_out_UNCONNECTED[0]), .txsequence_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .txswing_in(1'b0), .txsyncallin_in(1'b0), .txsyncdone_out(NLW_inst_txsyncdone_out_UNCONNECTED[0]), .txsyncin_in(1'b0), .txsyncmode_in(1'b0), .txsyncout_out(NLW_inst_txsyncout_out_UNCONNECTED[0]), .txsysclksel_in({1'b0,1'b0}), .txuserrdy_in(1'b1), .txusrclk2_in(1'b0), .txusrclk_in(1'b0), .ubcfgstreamen_in(1'b0), .ubdaddr_out(NLW_inst_ubdaddr_out_UNCONNECTED[0]), .ubden_out(NLW_inst_ubden_out_UNCONNECTED[0]), .ubdi_out(NLW_inst_ubdi_out_UNCONNECTED[0]), .ubdo_in(1'b0), .ubdrdy_in(1'b0), .ubdwe_out(NLW_inst_ubdwe_out_UNCONNECTED[0]), .ubenable_in(1'b0), .ubgpi_in(1'b0), .ubintr_in(1'b0), .ubiolmbrst_in(1'b0), .ubmbrst_in(1'b0), .ubmdmcapture_in(1'b0), .ubmdmdbgrst_in(1'b0), .ubmdmdbgupdate_in(1'b0), .ubmdmregen_in(1'b0), .ubmdmshift_in(1'b0), .ubmdmsysrst_in(1'b0), .ubmdmtck_in(1'b0), .ubmdmtdi_in(1'b0), .ubmdmtdo_out(NLW_inst_ubmdmtdo_out_UNCONNECTED[0]), .ubrsvdout_out(NLW_inst_ubrsvdout_out_UNCONNECTED[0]), .ubtxuart_out(NLW_inst_ubtxuart_out_UNCONNECTED[0])); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_gt_gthe3_channel_wrapper (cplllock_out, gthtxn_out, gthtxp_out, gtpowergood_out, rxcdrlock_out, rxoutclk_out, rxpmaresetdone_out, rxresetdone_out, txoutclk_out, txresetdone_out, gtwiz_userdata_rx_out, rxctrl0_out, rxctrl1_out, rxclkcorcnt_out, txbufstatus_out, rxbufstatus_out, rxctrl2_out, rxctrl3_out, rst_in0, \gen_gtwizard_gthe3.cpllpd_ch_int , drpclk_in, gthrxn_in, gthrxp_in, gtrefclk0_in, \gen_gtwizard_gthe3.gtrxreset_int , \gen_gtwizard_gthe3.gttxreset_int , rxmcommaalignen_in, \gen_gtwizard_gthe3.rxprogdivreset_int , \gen_gtwizard_gthe3.rxuserrdy_int , rxusrclk_in, txelecidle_in, \gen_gtwizard_gthe3.txprogdivreset_int , \gen_gtwizard_gthe3.txuserrdy_int , gtwiz_userdata_tx_in, txctrl0_in, txctrl1_in, rxpd_in, txctrl2_in); output [0:0]cplllock_out; output [0:0]gthtxn_out; output [0:0]gthtxp_out; output [0:0]gtpowergood_out; output [0:0]rxcdrlock_out; output [0:0]rxoutclk_out; output [0:0]rxpmaresetdone_out; output [0:0]rxresetdone_out; output [0:0]txoutclk_out; output [0:0]txresetdone_out; output [15:0]gtwiz_userdata_rx_out; output [1:0]rxctrl0_out; output [1:0]rxctrl1_out; output [1:0]rxclkcorcnt_out; output [0:0]txbufstatus_out; output [0:0]rxbufstatus_out; output [1:0]rxctrl2_out; output [1:0]rxctrl3_out; output rst_in0; input \gen_gtwizard_gthe3.cpllpd_ch_int ; input [0:0]drpclk_in; input [0:0]gthrxn_in; input [0:0]gthrxp_in; input [0:0]gtrefclk0_in; input \gen_gtwizard_gthe3.gtrxreset_int ; input \gen_gtwizard_gthe3.gttxreset_int ; input [0:0]rxmcommaalignen_in; input \gen_gtwizard_gthe3.rxprogdivreset_int ; input \gen_gtwizard_gthe3.rxuserrdy_int ; input [0:0]rxusrclk_in; input [0:0]txelecidle_in; input \gen_gtwizard_gthe3.txprogdivreset_int ; input \gen_gtwizard_gthe3.txuserrdy_int ; input [15:0]gtwiz_userdata_tx_in; input [1:0]txctrl0_in; input [1:0]txctrl1_in; input [0:0]rxpd_in; input [1:0]txctrl2_in; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.cpllpd_ch_int ; wire \gen_gtwizard_gthe3.gtrxreset_int ; wire \gen_gtwizard_gthe3.gttxreset_int ; wire \gen_gtwizard_gthe3.rxprogdivreset_int ; wire \gen_gtwizard_gthe3.rxuserrdy_int ; wire \gen_gtwizard_gthe3.txprogdivreset_int ; wire \gen_gtwizard_gthe3.txuserrdy_int ; wire [0:0]gthrxn_in; wire [0:0]gthrxp_in; wire [0:0]gthtxn_out; wire [0:0]gthtxp_out; wire [0:0]gtpowergood_out; wire [0:0]gtrefclk0_in; wire [15:0]gtwiz_userdata_rx_out; wire [15:0]gtwiz_userdata_tx_in; wire rst_in0; wire [0:0]rxbufstatus_out; wire [0:0]rxcdrlock_out; wire [1:0]rxclkcorcnt_out; wire [1:0]rxctrl0_out; wire [1:0]rxctrl1_out; wire [1:0]rxctrl2_out; wire [1:0]rxctrl3_out; wire [0:0]rxmcommaalignen_in; wire [0:0]rxoutclk_out; wire [0:0]rxpd_in; wire [0:0]rxpmaresetdone_out; wire [0:0]rxresetdone_out; wire [0:0]rxusrclk_in; wire [0:0]txbufstatus_out; wire [1:0]txctrl0_in; wire [1:0]txctrl1_in; wire [1:0]txctrl2_in; wire [0:0]txelecidle_in; wire [0:0]txoutclk_out; wire [0:0]txresetdone_out; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_gthe3_channel channel_inst (.cplllock_out(cplllock_out), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.cpllpd_ch_int (\gen_gtwizard_gthe3.cpllpd_ch_int ), .\gen_gtwizard_gthe3.gtrxreset_int (\gen_gtwizard_gthe3.gtrxreset_int ), .\gen_gtwizard_gthe3.gttxreset_int (\gen_gtwizard_gthe3.gttxreset_int ), .\gen_gtwizard_gthe3.rxprogdivreset_int (\gen_gtwizard_gthe3.rxprogdivreset_int ), .\gen_gtwizard_gthe3.rxuserrdy_int (\gen_gtwizard_gthe3.rxuserrdy_int ), .\gen_gtwizard_gthe3.txprogdivreset_int (\gen_gtwizard_gthe3.txprogdivreset_int ), .\gen_gtwizard_gthe3.txuserrdy_int (\gen_gtwizard_gthe3.txuserrdy_int ), .gthrxn_in(gthrxn_in), .gthrxp_in(gthrxp_in), .gthtxn_out(gthtxn_out), .gthtxp_out(gthtxp_out), .gtpowergood_out(gtpowergood_out), .gtrefclk0_in(gtrefclk0_in), .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out), .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in), .rst_in0(rst_in0), .rxbufstatus_out(rxbufstatus_out), .rxcdrlock_out(rxcdrlock_out), .rxclkcorcnt_out(rxclkcorcnt_out), .rxctrl0_out(rxctrl0_out), .rxctrl1_out(rxctrl1_out), .rxctrl2_out(rxctrl2_out), .rxctrl3_out(rxctrl3_out), .rxmcommaalignen_in(rxmcommaalignen_in), .rxoutclk_out(rxoutclk_out), .rxpd_in(rxpd_in), .rxpmaresetdone_out(rxpmaresetdone_out), .rxresetdone_out(rxresetdone_out), .rxusrclk_in(rxusrclk_in), .txbufstatus_out(txbufstatus_out), .txctrl0_in(txctrl0_in), .txctrl1_in(txctrl1_in), .txctrl2_in(txctrl2_in), .txelecidle_in(txelecidle_in), .txoutclk_out(txoutclk_out), .txresetdone_out(txresetdone_out)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3 (cplllock_out, gthtxn_out, gthtxp_out, gtpowergood_out, rxoutclk_out, txoutclk_out, gtwiz_userdata_rx_out, rxctrl0_out, rxctrl1_out, rxclkcorcnt_out, txbufstatus_out, rxbufstatus_out, rxctrl2_out, rxctrl3_out, gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out, drpclk_in, gthrxn_in, gthrxp_in, gtrefclk0_in, rxmcommaalignen_in, rxusrclk_in, txelecidle_in, gtwiz_userdata_tx_in, txctrl0_in, txctrl1_in, rxpd_in, txctrl2_in, gtwiz_userclk_tx_active_in, gtwiz_reset_all_in, gtwiz_reset_tx_datapath_in, gtwiz_reset_rx_datapath_in); output [0:0]cplllock_out; output [0:0]gthtxn_out; output [0:0]gthtxp_out; output [0:0]gtpowergood_out; output [0:0]rxoutclk_out; output [0:0]txoutclk_out; output [15:0]gtwiz_userdata_rx_out; output [1:0]rxctrl0_out; output [1:0]rxctrl1_out; output [1:0]rxclkcorcnt_out; output [0:0]txbufstatus_out; output [0:0]rxbufstatus_out; output [1:0]rxctrl2_out; output [1:0]rxctrl3_out; output [0:0]gtwiz_reset_tx_done_out; output [0:0]gtwiz_reset_rx_done_out; input [0:0]drpclk_in; input [0:0]gthrxn_in; input [0:0]gthrxp_in; input [0:0]gtrefclk0_in; input [0:0]rxmcommaalignen_in; input [0:0]rxusrclk_in; input [0:0]txelecidle_in; input [15:0]gtwiz_userdata_tx_in; input [1:0]txctrl0_in; input [1:0]txctrl1_in; input [0:0]rxpd_in; input [1:0]txctrl2_in; input [0:0]gtwiz_userclk_tx_active_in; input [0:0]gtwiz_reset_all_in; input [0:0]gtwiz_reset_tx_datapath_in; input [0:0]gtwiz_reset_rx_datapath_in; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.cpllpd_ch_int ; wire \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_4 ; wire \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_6 ; wire \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_7 ; wire \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_9 ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; wire \gen_gtwizard_gthe3.gtrxreset_int ; wire \gen_gtwizard_gthe3.gttxreset_int ; wire \gen_gtwizard_gthe3.rxprogdivreset_int ; wire \gen_gtwizard_gthe3.rxuserrdy_int ; wire \gen_gtwizard_gthe3.txprogdivreset_int ; wire \gen_gtwizard_gthe3.txuserrdy_int ; wire [0:0]gthrxn_in; wire [0:0]gthrxp_in; wire [0:0]gthtxn_out; wire [0:0]gthtxp_out; wire [0:0]gtpowergood_out; wire [0:0]gtrefclk0_in; wire [0:0]gtwiz_reset_all_in; wire [0:0]gtwiz_reset_rx_datapath_in; wire [0:0]gtwiz_reset_rx_done_out; wire [0:0]gtwiz_reset_tx_datapath_in; wire [0:0]gtwiz_reset_tx_done_out; wire [0:0]gtwiz_userclk_tx_active_in; wire [15:0]gtwiz_userdata_rx_out; wire [15:0]gtwiz_userdata_tx_in; wire rst_in0; wire [0:0]rxbufstatus_out; wire [1:0]rxclkcorcnt_out; wire [1:0]rxctrl0_out; wire [1:0]rxctrl1_out; wire [1:0]rxctrl2_out; wire [1:0]rxctrl3_out; wire [0:0]rxmcommaalignen_in; wire [0:0]rxoutclk_out; wire [0:0]rxpd_in; wire [0:0]rxusrclk_in; wire [0:0]txbufstatus_out; wire [1:0]txctrl0_in; wire [1:0]txctrl1_in; wire [1:0]txctrl2_in; wire [0:0]txelecidle_in; wire [0:0]txoutclk_out; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_gt_gthe3_channel_wrapper \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst (.cplllock_out(cplllock_out), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.cpllpd_ch_int (\gen_gtwizard_gthe3.cpllpd_ch_int ), .\gen_gtwizard_gthe3.gtrxreset_int (\gen_gtwizard_gthe3.gtrxreset_int ), .\gen_gtwizard_gthe3.gttxreset_int (\gen_gtwizard_gthe3.gttxreset_int ), .\gen_gtwizard_gthe3.rxprogdivreset_int (\gen_gtwizard_gthe3.rxprogdivreset_int ), .\gen_gtwizard_gthe3.rxuserrdy_int (\gen_gtwizard_gthe3.rxuserrdy_int ), .\gen_gtwizard_gthe3.txprogdivreset_int (\gen_gtwizard_gthe3.txprogdivreset_int ), .\gen_gtwizard_gthe3.txuserrdy_int (\gen_gtwizard_gthe3.txuserrdy_int ), .gthrxn_in(gthrxn_in), .gthrxp_in(gthrxp_in), .gthtxn_out(gthtxn_out), .gthtxp_out(gthtxp_out), .gtpowergood_out(gtpowergood_out), .gtrefclk0_in(gtrefclk0_in), .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out), .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in), .rst_in0(rst_in0), .rxbufstatus_out(rxbufstatus_out), .rxcdrlock_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_4 ), .rxclkcorcnt_out(rxclkcorcnt_out), .rxctrl0_out(rxctrl0_out), .rxctrl1_out(rxctrl1_out), .rxctrl2_out(rxctrl2_out), .rxctrl3_out(rxctrl3_out), .rxmcommaalignen_in(rxmcommaalignen_in), .rxoutclk_out(rxoutclk_out), .rxpd_in(rxpd_in), .rxpmaresetdone_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_6 ), .rxresetdone_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_7 ), .rxusrclk_in(rxusrclk_in), .txbufstatus_out(txbufstatus_out), .txctrl0_in(txctrl0_in), .txctrl1_in(txctrl1_in), .txctrl2_in(txctrl2_in), .txelecidle_in(txelecidle_in), .txoutclk_out(txoutclk_out), .txresetdone_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_9 )); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_rxresetdone_inst (.drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .rxresetdone_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_7 )); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_3 \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_txresetdone_inst (.drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .txresetdone_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_9 )); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_gtwiz_reset \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst (.cplllock_out(cplllock_out), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.cpllpd_ch_int (\gen_gtwizard_gthe3.cpllpd_ch_int ), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .\gen_gtwizard_gthe3.gtrxreset_int (\gen_gtwizard_gthe3.gtrxreset_int ), .\gen_gtwizard_gthe3.gttxreset_int (\gen_gtwizard_gthe3.gttxreset_int ), .\gen_gtwizard_gthe3.rxprogdivreset_int (\gen_gtwizard_gthe3.rxprogdivreset_int ), .\gen_gtwizard_gthe3.rxuserrdy_int (\gen_gtwizard_gthe3.rxuserrdy_int ), .\gen_gtwizard_gthe3.txprogdivreset_int (\gen_gtwizard_gthe3.txprogdivreset_int ), .\gen_gtwizard_gthe3.txuserrdy_int (\gen_gtwizard_gthe3.txuserrdy_int ), .gtpowergood_out(gtpowergood_out), .gtwiz_reset_all_in(gtwiz_reset_all_in), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out), .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in), .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out), .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in), .rst_in0(rst_in0), .rxcdrlock_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_4 ), .rxpmaresetdone_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_6 ), .rxusrclk_in(rxusrclk_in)); endmodule (* C_CHANNEL_ENABLE = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_COMMON_SCALING_FACTOR = "1" *) (* C_CPLL_VCO_FREQUENCY = "2500.000000" *) (* C_ENABLE_COMMON_USRCLK = "0" *) (* C_FORCE_COMMONS = "0" *) (* C_FREERUN_FREQUENCY = "50.000000" *) (* C_GT_REV = "17" *) (* C_GT_TYPE = "0" *) (* C_INCLUDE_CPLL_CAL = "2" *) (* C_LOCATE_COMMON = "0" *) (* C_LOCATE_IN_SYSTEM_IBERT_CORE = "2" *) (* C_LOCATE_RESET_CONTROLLER = "0" *) (* C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER = "0" *) (* C_LOCATE_RX_USER_CLOCKING = "1" *) (* C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER = "0" *) (* C_LOCATE_TX_USER_CLOCKING = "1" *) (* C_LOCATE_USER_DATA_WIDTH_SIZING = "0" *) (* C_PCIE_CORECLK_FREQ = "250" *) (* C_PCIE_ENABLE = "0" *) (* C_RESET_CONTROLLER_INSTANCE_CTRL = "0" *) (* C_RESET_SEQUENCE_INTERVAL = "0" *) (* C_RX_BUFFBYPASS_MODE = "0" *) (* C_RX_BUFFER_BYPASS_INSTANCE_CTRL = "0" *) (* C_RX_BUFFER_MODE = "1" *) (* C_RX_CB_DISP = "8'b00000000" *) (* C_RX_CB_K = "8'b00000000" *) (* C_RX_CB_LEN_SEQ = "1" *) (* C_RX_CB_MAX_LEVEL = "1" *) (* C_RX_CB_NUM_SEQ = "0" *) (* C_RX_CB_VAL = "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_RX_CC_DISP = "8'b00000000" *) (* C_RX_CC_ENABLE = "1" *) (* C_RX_CC_K = "8'b00010001" *) (* C_RX_CC_LEN_SEQ = "2" *) (* C_RX_CC_NUM_SEQ = "2" *) (* C_RX_CC_PERIODICITY = "5000" *) (* C_RX_CC_VAL = "80'b00000000000000000000001011010100101111000000000000000000000000010100000010111100" *) (* C_RX_COMMA_M_ENABLE = "1" *) (* C_RX_COMMA_M_VAL = "10'b1010000011" *) (* C_RX_COMMA_P_ENABLE = "1" *) (* C_RX_COMMA_P_VAL = "10'b0101111100" *) (* C_RX_DATA_DECODING = "1" *) (* C_RX_ENABLE = "1" *) (* C_RX_INT_DATA_WIDTH = "20" *) (* C_RX_LINE_RATE = "1.250000" *) (* C_RX_MASTER_CHANNEL_IDX = "96" *) (* C_RX_OUTCLK_BUFG_GT_DIV = "1" *) (* C_RX_OUTCLK_FREQUENCY = "62.500000" *) (* C_RX_OUTCLK_SOURCE = "1" *) (* C_RX_PLL_TYPE = "2" *) (* C_RX_RECCLK_OUTPUT = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_RX_REFCLK_FREQUENCY = "125.000000" *) (* C_RX_SLIDE_MODE = "0" *) (* C_RX_USER_CLOCKING_CONTENTS = "0" *) (* C_RX_USER_CLOCKING_INSTANCE_CTRL = "0" *) (* C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK = "1" *) (* C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 = "1" *) (* C_RX_USER_CLOCKING_SOURCE = "0" *) (* C_RX_USER_DATA_WIDTH = "16" *) (* C_RX_USRCLK2_FREQUENCY = "62.500000" *) (* C_RX_USRCLK_FREQUENCY = "62.500000" *) (* C_SECONDARY_QPLL_ENABLE = "0" *) (* C_SECONDARY_QPLL_REFCLK_FREQUENCY = "257.812500" *) (* C_SIM_CPLL_CAL_BYPASS = "1" *) (* C_TOTAL_NUM_CHANNELS = "1" *) (* C_TOTAL_NUM_COMMONS = "0" *) (* C_TOTAL_NUM_COMMONS_EXAMPLE = "0" *) (* C_TXPROGDIV_FREQ_ENABLE = "1" *) (* C_TXPROGDIV_FREQ_SOURCE = "2" *) (* C_TXPROGDIV_FREQ_VAL = "125.000000" *) (* C_TX_BUFFBYPASS_MODE = "0" *) (* C_TX_BUFFER_BYPASS_INSTANCE_CTRL = "0" *) (* C_TX_BUFFER_MODE = "1" *) (* C_TX_DATA_ENCODING = "1" *) (* C_TX_ENABLE = "1" *) (* C_TX_INT_DATA_WIDTH = "20" *) (* C_TX_LINE_RATE = "1.250000" *) (* C_TX_MASTER_CHANNEL_IDX = "96" *) (* C_TX_OUTCLK_BUFG_GT_DIV = "2" *) (* C_TX_OUTCLK_FREQUENCY = "62.500000" *) (* C_TX_OUTCLK_SOURCE = "4" *) (* C_TX_PLL_TYPE = "2" *) (* C_TX_REFCLK_FREQUENCY = "125.000000" *) (* C_TX_USER_CLOCKING_CONTENTS = "0" *) (* C_TX_USER_CLOCKING_INSTANCE_CTRL = "0" *) (* C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK = "1" *) (* C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 = "1" *) (* C_TX_USER_CLOCKING_SOURCE = "0" *) (* C_TX_USER_DATA_WIDTH = "16" *) (* C_TX_USRCLK2_FREQUENCY = "62.500000" *) (* C_TX_USRCLK_FREQUENCY = "62.500000" *) (* C_USER_GTPOWERGOOD_DELAY_EN = "0" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_gt_gtwizard_top (gtwiz_userclk_tx_reset_in, gtwiz_userclk_tx_active_in, gtwiz_userclk_tx_srcclk_out, gtwiz_userclk_tx_usrclk_out, gtwiz_userclk_tx_usrclk2_out, gtwiz_userclk_tx_active_out, gtwiz_userclk_rx_reset_in, gtwiz_userclk_rx_active_in, gtwiz_userclk_rx_srcclk_out, gtwiz_userclk_rx_usrclk_out, gtwiz_userclk_rx_usrclk2_out, gtwiz_userclk_rx_active_out, gtwiz_buffbypass_tx_reset_in, gtwiz_buffbypass_tx_start_user_in, gtwiz_buffbypass_tx_done_out, gtwiz_buffbypass_tx_error_out, gtwiz_buffbypass_rx_reset_in, gtwiz_buffbypass_rx_start_user_in, gtwiz_buffbypass_rx_done_out, gtwiz_buffbypass_rx_error_out, gtwiz_reset_clk_freerun_in, gtwiz_reset_all_in, gtwiz_reset_tx_pll_and_datapath_in, gtwiz_reset_tx_datapath_in, gtwiz_reset_rx_pll_and_datapath_in, gtwiz_reset_rx_datapath_in, gtwiz_reset_tx_done_in, gtwiz_reset_rx_done_in, gtwiz_reset_qpll0lock_in, gtwiz_reset_qpll1lock_in, gtwiz_reset_rx_cdr_stable_out, gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out, gtwiz_reset_qpll0reset_out, gtwiz_reset_qpll1reset_out, gtwiz_gthe3_cpll_cal_txoutclk_period_in, gtwiz_gthe3_cpll_cal_cnt_tol_in, gtwiz_gthe3_cpll_cal_bufg_ce_in, gtwiz_gthe4_cpll_cal_txoutclk_period_in, gtwiz_gthe4_cpll_cal_cnt_tol_in, gtwiz_gthe4_cpll_cal_bufg_ce_in, gtwiz_gtye4_cpll_cal_txoutclk_period_in, gtwiz_gtye4_cpll_cal_cnt_tol_in, gtwiz_gtye4_cpll_cal_bufg_ce_in, gtwiz_userdata_tx_in, gtwiz_userdata_rx_out, bgbypassb_in, bgmonitorenb_in, bgpdb_in, bgrcalovrd_in, bgrcalovrdenb_in, drpaddr_common_in, drpclk_common_in, drpdi_common_in, drpen_common_in, drpwe_common_in, gtgrefclk0_in, gtgrefclk1_in, gtnorthrefclk00_in, gtnorthrefclk01_in, gtnorthrefclk10_in, gtnorthrefclk11_in, gtrefclk00_in, gtrefclk01_in, gtrefclk10_in, gtrefclk11_in, gtsouthrefclk00_in, gtsouthrefclk01_in, gtsouthrefclk10_in, gtsouthrefclk11_in, pcierateqpll0_in, pcierateqpll1_in, pmarsvd0_in, pmarsvd1_in, qpll0clkrsvd0_in, qpll0clkrsvd1_in, qpll0fbdiv_in, qpll0lockdetclk_in, qpll0locken_in, qpll0pd_in, qpll0refclksel_in, qpll0reset_in, qpll1clkrsvd0_in, qpll1clkrsvd1_in, qpll1fbdiv_in, qpll1lockdetclk_in, qpll1locken_in, qpll1pd_in, qpll1refclksel_in, qpll1reset_in, qpllrsvd1_in, qpllrsvd2_in, qpllrsvd3_in, qpllrsvd4_in, rcalenb_in, sdm0data_in, sdm0reset_in, sdm0toggle_in, sdm0width_in, sdm1data_in, sdm1reset_in, sdm1toggle_in, sdm1width_in, tcongpi_in, tconpowerup_in, tconreset_in, tconrsvdin1_in, ubcfgstreamen_in, ubdo_in, ubdrdy_in, ubenable_in, ubgpi_in, ubintr_in, ubiolmbrst_in, ubmbrst_in, ubmdmcapture_in, ubmdmdbgrst_in, ubmdmdbgupdate_in, ubmdmregen_in, ubmdmshift_in, ubmdmsysrst_in, ubmdmtck_in, ubmdmtdi_in, drpdo_common_out, drprdy_common_out, pmarsvdout0_out, pmarsvdout1_out, qpll0fbclklost_out, qpll0lock_out, qpll0outclk_out, qpll0outrefclk_out, qpll0refclklost_out, qpll1fbclklost_out, qpll1lock_out, qpll1outclk_out, qpll1outrefclk_out, qpll1refclklost_out, qplldmonitor0_out, qplldmonitor1_out, refclkoutmonitor0_out, refclkoutmonitor1_out, rxrecclk0_sel_out, rxrecclk1_sel_out, rxrecclk0sel_out, rxrecclk1sel_out, sdm0finalout_out, sdm0testdata_out, sdm1finalout_out, sdm1testdata_out, tcongpo_out, tconrsvdout0_out, ubdaddr_out, ubden_out, ubdi_out, ubdwe_out, ubmdmtdo_out, ubrsvdout_out, ubtxuart_out, cdrstepdir_in, cdrstepsq_in, cdrstepsx_in, cfgreset_in, clkrsvd0_in, clkrsvd1_in, cpllfreqlock_in, cplllockdetclk_in, cplllocken_in, cpllpd_in, cpllrefclksel_in, cpllreset_in, dmonfiforeset_in, dmonitorclk_in, drpaddr_in, drpclk_in, drpdi_in, drpen_in, drprst_in, drpwe_in, elpcaldvorwren_in, elpcalpaorwren_in, evoddphicaldone_in, evoddphicalstart_in, evoddphidrden_in, evoddphidwren_in, evoddphixrden_in, evoddphixwren_in, eyescanmode_in, eyescanreset_in, eyescantrigger_in, freqos_in, gtgrefclk_in, gthrxn_in, gthrxp_in, gtnorthrefclk0_in, gtnorthrefclk1_in, gtrefclk0_in, gtrefclk1_in, gtresetsel_in, gtrsvd_in, gtrxreset_in, gtrxresetsel_in, gtsouthrefclk0_in, gtsouthrefclk1_in, gttxreset_in, gttxresetsel_in, incpctrl_in, gtyrxn_in, gtyrxp_in, loopback_in, looprsvd_in, lpbkrxtxseren_in, lpbktxrxseren_in, pcieeqrxeqadaptdone_in, pcierstidle_in, pciersttxsyncstart_in, pcieuserratedone_in, pcsrsvdin_in, pcsrsvdin2_in, pmarsvdin_in, qpll0clk_in, qpll0freqlock_in, qpll0refclk_in, qpll1clk_in, qpll1freqlock_in, qpll1refclk_in, resetovrd_in, rstclkentx_in, rx8b10ben_in, rxafecfoken_in, rxbufreset_in, rxcdrfreqreset_in, rxcdrhold_in, rxcdrovrden_in, rxcdrreset_in, rxcdrresetrsv_in, rxchbonden_in, rxchbondi_in, rxchbondlevel_in, rxchbondmaster_in, rxchbondslave_in, rxckcalreset_in, rxckcalstart_in, rxcommadeten_in, rxdfeagcctrl_in, rxdccforcestart_in, rxdfeagchold_in, rxdfeagcovrden_in, rxdfecfokfcnum_in, rxdfecfokfen_in, rxdfecfokfpulse_in, rxdfecfokhold_in, rxdfecfokovren_in, rxdfekhhold_in, rxdfekhovrden_in, rxdfelfhold_in, rxdfelfovrden_in, rxdfelpmreset_in, rxdfetap10hold_in, rxdfetap10ovrden_in, rxdfetap11hold_in, rxdfetap11ovrden_in, rxdfetap12hold_in, rxdfetap12ovrden_in, rxdfetap13hold_in, rxdfetap13ovrden_in, rxdfetap14hold_in, rxdfetap14ovrden_in, rxdfetap15hold_in, rxdfetap15ovrden_in, rxdfetap2hold_in, rxdfetap2ovrden_in, rxdfetap3hold_in, rxdfetap3ovrden_in, rxdfetap4hold_in, rxdfetap4ovrden_in, rxdfetap5hold_in, rxdfetap5ovrden_in, rxdfetap6hold_in, rxdfetap6ovrden_in, rxdfetap7hold_in, rxdfetap7ovrden_in, rxdfetap8hold_in, rxdfetap8ovrden_in, rxdfetap9hold_in, rxdfetap9ovrden_in, rxdfeuthold_in, rxdfeutovrden_in, rxdfevphold_in, rxdfevpovrden_in, rxdfevsen_in, rxdfexyden_in, rxdlybypass_in, rxdlyen_in, rxdlyovrden_in, rxdlysreset_in, rxelecidlemode_in, rxeqtraining_in, rxgearboxslip_in, rxlatclk_in, rxlpmen_in, rxlpmgchold_in, rxlpmgcovrden_in, rxlpmhfhold_in, rxlpmhfovrden_in, rxlpmlfhold_in, rxlpmlfklovrden_in, rxlpmoshold_in, rxlpmosovrden_in, rxmcommaalignen_in, rxmonitorsel_in, rxoobreset_in, rxoscalreset_in, rxoshold_in, rxosintcfg_in, rxosinten_in, rxosinthold_in, rxosintovrden_in, rxosintstrobe_in, rxosinttestovrden_in, rxosovrden_in, rxoutclksel_in, rxpcommaalignen_in, rxpcsreset_in, rxpd_in, rxphalign_in, rxphalignen_in, rxphdlypd_in, rxphdlyreset_in, rxphovrden_in, rxpllclksel_in, rxpmareset_in, rxpolarity_in, rxprbscntreset_in, rxprbssel_in, rxprogdivreset_in, rxqpien_in, rxrate_in, rxratemode_in, rxslide_in, rxslipoutclk_in, rxslippma_in, rxsyncallin_in, rxsyncin_in, rxsyncmode_in, rxsysclksel_in, rxtermination_in, rxuserrdy_in, rxusrclk_in, rxusrclk2_in, sigvalidclk_in, tstin_in, tx8b10bbypass_in, tx8b10ben_in, txbufdiffctrl_in, txcominit_in, txcomsas_in, txcomwake_in, txctrl0_in, txctrl1_in, txctrl2_in, txdata_in, txdataextendrsvd_in, txdccforcestart_in, txdccreset_in, txdeemph_in, txdetectrx_in, txdiffctrl_in, txdiffpd_in, txdlybypass_in, txdlyen_in, txdlyhold_in, txdlyovrden_in, txdlysreset_in, txdlyupdown_in, txelecidle_in, txelforcestart_in, txheader_in, txinhibit_in, txlatclk_in, txlfpstreset_in, txlfpsu2lpexit_in, txlfpsu3wake_in, txmaincursor_in, txmargin_in, txmuxdcdexhold_in, txmuxdcdorwren_in, txoneszeros_in, txoutclksel_in, txpcsreset_in, txpd_in, txpdelecidlemode_in, txphalign_in, txphalignen_in, txphdlypd_in, txphdlyreset_in, txphdlytstclk_in, txphinit_in, txphovrden_in, txpippmen_in, txpippmovrden_in, txpippmpd_in, txpippmsel_in, txpippmstepsize_in, txpisopd_in, txpllclksel_in, txpmareset_in, txpolarity_in, txpostcursor_in, txpostcursorinv_in, txprbsforceerr_in, txprbssel_in, txprecursor_in, txprecursorinv_in, txprogdivreset_in, txqpibiasen_in, txqpistrongpdown_in, txqpiweakpup_in, txrate_in, txratemode_in, txsequence_in, txswing_in, txsyncallin_in, txsyncin_in, txsyncmode_in, txsysclksel_in, txuserrdy_in, txusrclk_in, txusrclk2_in, bufgtce_out, bufgtcemask_out, bufgtdiv_out, bufgtreset_out, bufgtrstmask_out, cpllfbclklost_out, cplllock_out, cpllrefclklost_out, dmonitorout_out, dmonitoroutclk_out, drpdo_out, drprdy_out, eyescandataerror_out, gthtxn_out, gthtxp_out, gtpowergood_out, gtrefclkmonitor_out, gtytxn_out, gtytxp_out, pcierategen3_out, pcierateidle_out, pcierateqpllpd_out, pcierateqpllreset_out, pciesynctxsyncdone_out, pcieusergen3rdy_out, pcieuserphystatusrst_out, pcieuserratestart_out, pcsrsvdout_out, phystatus_out, pinrsrvdas_out, powerpresent_out, resetexception_out, rxbufstatus_out, rxbyteisaligned_out, rxbyterealign_out, rxcdrlock_out, rxcdrphdone_out, rxchanbondseq_out, rxchanisaligned_out, rxchanrealign_out, rxchbondo_out, rxckcaldone_out, rxclkcorcnt_out, rxcominitdet_out, rxcommadet_out, rxcomsasdet_out, rxcomwakedet_out, rxctrl0_out, rxctrl1_out, rxctrl2_out, rxctrl3_out, rxdata_out, rxdataextendrsvd_out, rxdatavalid_out, rxdlysresetdone_out, rxelecidle_out, rxheader_out, rxheadervalid_out, rxlfpstresetdet_out, rxlfpsu2lpexitdet_out, rxlfpsu3wakedet_out, rxmonitorout_out, rxosintdone_out, rxosintstarted_out, rxosintstrobedone_out, rxosintstrobestarted_out, rxoutclk_out, rxoutclkfabric_out, rxoutclkpcs_out, rxphaligndone_out, rxphalignerr_out, rxpmaresetdone_out, rxprbserr_out, rxprbslocked_out, rxprgdivresetdone_out, rxqpisenn_out, rxqpisenp_out, rxratedone_out, rxrecclkout_out, rxresetdone_out, rxsliderdy_out, rxslipdone_out, rxslipoutclkrdy_out, rxslippmardy_out, rxstartofseq_out, rxstatus_out, rxsyncdone_out, rxsyncout_out, rxvalid_out, txbufstatus_out, txcomfinish_out, txdccdone_out, txdlysresetdone_out, txoutclk_out, txoutclkfabric_out, txoutclkpcs_out, txphaligndone_out, txphinitdone_out, txpmaresetdone_out, txprgdivresetdone_out, txqpisenn_out, txqpisenp_out, txratedone_out, txresetdone_out, txsyncdone_out, txsyncout_out); input [0:0]gtwiz_userclk_tx_reset_in; input [0:0]gtwiz_userclk_tx_active_in; output [0:0]gtwiz_userclk_tx_srcclk_out; output [0:0]gtwiz_userclk_tx_usrclk_out; output [0:0]gtwiz_userclk_tx_usrclk2_out; output [0:0]gtwiz_userclk_tx_active_out; input [0:0]gtwiz_userclk_rx_reset_in; input [0:0]gtwiz_userclk_rx_active_in; output [0:0]gtwiz_userclk_rx_srcclk_out; output [0:0]gtwiz_userclk_rx_usrclk_out; output [0:0]gtwiz_userclk_rx_usrclk2_out; output [0:0]gtwiz_userclk_rx_active_out; input [0:0]gtwiz_buffbypass_tx_reset_in; input [0:0]gtwiz_buffbypass_tx_start_user_in; output [0:0]gtwiz_buffbypass_tx_done_out; output [0:0]gtwiz_buffbypass_tx_error_out; input [0:0]gtwiz_buffbypass_rx_reset_in; input [0:0]gtwiz_buffbypass_rx_start_user_in; output [0:0]gtwiz_buffbypass_rx_done_out; output [0:0]gtwiz_buffbypass_rx_error_out; input [0:0]gtwiz_reset_clk_freerun_in; input [0:0]gtwiz_reset_all_in; input [0:0]gtwiz_reset_tx_pll_and_datapath_in; input [0:0]gtwiz_reset_tx_datapath_in; input [0:0]gtwiz_reset_rx_pll_and_datapath_in; input [0:0]gtwiz_reset_rx_datapath_in; input [0:0]gtwiz_reset_tx_done_in; input [0:0]gtwiz_reset_rx_done_in; input [0:0]gtwiz_reset_qpll0lock_in; input [0:0]gtwiz_reset_qpll1lock_in; output [0:0]gtwiz_reset_rx_cdr_stable_out; output [0:0]gtwiz_reset_tx_done_out; output [0:0]gtwiz_reset_rx_done_out; output [0:0]gtwiz_reset_qpll0reset_out; output [0:0]gtwiz_reset_qpll1reset_out; input [17:0]gtwiz_gthe3_cpll_cal_txoutclk_period_in; input [17:0]gtwiz_gthe3_cpll_cal_cnt_tol_in; input [0:0]gtwiz_gthe3_cpll_cal_bufg_ce_in; input [17:0]gtwiz_gthe4_cpll_cal_txoutclk_period_in; input [17:0]gtwiz_gthe4_cpll_cal_cnt_tol_in; input [0:0]gtwiz_gthe4_cpll_cal_bufg_ce_in; input [17:0]gtwiz_gtye4_cpll_cal_txoutclk_period_in; input [17:0]gtwiz_gtye4_cpll_cal_cnt_tol_in; input [0:0]gtwiz_gtye4_cpll_cal_bufg_ce_in; input [15:0]gtwiz_userdata_tx_in; output [15:0]gtwiz_userdata_rx_out; input [0:0]bgbypassb_in; input [0:0]bgmonitorenb_in; input [0:0]bgpdb_in; input [4:0]bgrcalovrd_in; input [0:0]bgrcalovrdenb_in; input [8:0]drpaddr_common_in; input [0:0]drpclk_common_in; input [15:0]drpdi_common_in; input [0:0]drpen_common_in; input [0:0]drpwe_common_in; input [0:0]gtgrefclk0_in; input [0:0]gtgrefclk1_in; input [0:0]gtnorthrefclk00_in; input [0:0]gtnorthrefclk01_in; input [0:0]gtnorthrefclk10_in; input [0:0]gtnorthrefclk11_in; input [0:0]gtrefclk00_in; input [0:0]gtrefclk01_in; input [0:0]gtrefclk10_in; input [0:0]gtrefclk11_in; input [0:0]gtsouthrefclk00_in; input [0:0]gtsouthrefclk01_in; input [0:0]gtsouthrefclk10_in; input [0:0]gtsouthrefclk11_in; input [0:0]pcierateqpll0_in; input [0:0]pcierateqpll1_in; input [7:0]pmarsvd0_in; input [7:0]pmarsvd1_in; input [0:0]qpll0clkrsvd0_in; input [0:0]qpll0clkrsvd1_in; input [0:0]qpll0fbdiv_in; input [0:0]qpll0lockdetclk_in; input [0:0]qpll0locken_in; input [0:0]qpll0pd_in; input [2:0]qpll0refclksel_in; input [0:0]qpll0reset_in; input [0:0]qpll1clkrsvd0_in; input [0:0]qpll1clkrsvd1_in; input [0:0]qpll1fbdiv_in; input [0:0]qpll1lockdetclk_in; input [0:0]qpll1locken_in; input [0:0]qpll1pd_in; input [2:0]qpll1refclksel_in; input [0:0]qpll1reset_in; input [7:0]qpllrsvd1_in; input [4:0]qpllrsvd2_in; input [4:0]qpllrsvd3_in; input [7:0]qpllrsvd4_in; input [0:0]rcalenb_in; input [0:0]sdm0data_in; input [0:0]sdm0reset_in; input [0:0]sdm0toggle_in; input [0:0]sdm0width_in; input [0:0]sdm1data_in; input [0:0]sdm1reset_in; input [0:0]sdm1toggle_in; input [0:0]sdm1width_in; input [0:0]tcongpi_in; input [0:0]tconpowerup_in; input [0:0]tconreset_in; input [0:0]tconrsvdin1_in; input [0:0]ubcfgstreamen_in; input [0:0]ubdo_in; input [0:0]ubdrdy_in; input [0:0]ubenable_in; input [0:0]ubgpi_in; input [0:0]ubintr_in; input [0:0]ubiolmbrst_in; input [0:0]ubmbrst_in; input [0:0]ubmdmcapture_in; input [0:0]ubmdmdbgrst_in; input [0:0]ubmdmdbgupdate_in; input [0:0]ubmdmregen_in; input [0:0]ubmdmshift_in; input [0:0]ubmdmsysrst_in; input [0:0]ubmdmtck_in; input [0:0]ubmdmtdi_in; output [15:0]drpdo_common_out; output [0:0]drprdy_common_out; output [7:0]pmarsvdout0_out; output [7:0]pmarsvdout1_out; output [0:0]qpll0fbclklost_out; output [0:0]qpll0lock_out; output [0:0]qpll0outclk_out; output [0:0]qpll0outrefclk_out; output [0:0]qpll0refclklost_out; output [0:0]qpll1fbclklost_out; output [0:0]qpll1lock_out; output [0:0]qpll1outclk_out; output [0:0]qpll1outrefclk_out; output [0:0]qpll1refclklost_out; output [7:0]qplldmonitor0_out; output [7:0]qplldmonitor1_out; output [0:0]refclkoutmonitor0_out; output [0:0]refclkoutmonitor1_out; output [1:0]rxrecclk0_sel_out; output [1:0]rxrecclk1_sel_out; output [0:0]rxrecclk0sel_out; output [0:0]rxrecclk1sel_out; output [0:0]sdm0finalout_out; output [0:0]sdm0testdata_out; output [0:0]sdm1finalout_out; output [0:0]sdm1testdata_out; output [0:0]tcongpo_out; output [0:0]tconrsvdout0_out; output [0:0]ubdaddr_out; output [0:0]ubden_out; output [0:0]ubdi_out; output [0:0]ubdwe_out; output [0:0]ubmdmtdo_out; output [0:0]ubrsvdout_out; output [0:0]ubtxuart_out; input [0:0]cdrstepdir_in; input [0:0]cdrstepsq_in; input [0:0]cdrstepsx_in; input [0:0]cfgreset_in; input [0:0]clkrsvd0_in; input [0:0]clkrsvd1_in; input [0:0]cpllfreqlock_in; input [0:0]cplllockdetclk_in; input [0:0]cplllocken_in; input [0:0]cpllpd_in; input [2:0]cpllrefclksel_in; input [0:0]cpllreset_in; input [0:0]dmonfiforeset_in; input [0:0]dmonitorclk_in; input [8:0]drpaddr_in; input [0:0]drpclk_in; input [15:0]drpdi_in; input [0:0]drpen_in; input [0:0]drprst_in; input [0:0]drpwe_in; input [0:0]elpcaldvorwren_in; input [0:0]elpcalpaorwren_in; input [0:0]evoddphicaldone_in; input [0:0]evoddphicalstart_in; input [0:0]evoddphidrden_in; input [0:0]evoddphidwren_in; input [0:0]evoddphixrden_in; input [0:0]evoddphixwren_in; input [0:0]eyescanmode_in; input [0:0]eyescanreset_in; input [0:0]eyescantrigger_in; input [0:0]freqos_in; input [0:0]gtgrefclk_in; input [0:0]gthrxn_in; input [0:0]gthrxp_in; input [0:0]gtnorthrefclk0_in; input [0:0]gtnorthrefclk1_in; input [0:0]gtrefclk0_in; input [0:0]gtrefclk1_in; input [0:0]gtresetsel_in; input [15:0]gtrsvd_in; input [0:0]gtrxreset_in; input [0:0]gtrxresetsel_in; input [0:0]gtsouthrefclk0_in; input [0:0]gtsouthrefclk1_in; input [0:0]gttxreset_in; input [0:0]gttxresetsel_in; input [0:0]incpctrl_in; input [0:0]gtyrxn_in; input [0:0]gtyrxp_in; input [2:0]loopback_in; input [0:0]looprsvd_in; input [0:0]lpbkrxtxseren_in; input [0:0]lpbktxrxseren_in; input [0:0]pcieeqrxeqadaptdone_in; input [0:0]pcierstidle_in; input [0:0]pciersttxsyncstart_in; input [0:0]pcieuserratedone_in; input [15:0]pcsrsvdin_in; input [4:0]pcsrsvdin2_in; input [4:0]pmarsvdin_in; input [0:0]qpll0clk_in; input [0:0]qpll0freqlock_in; input [0:0]qpll0refclk_in; input [0:0]qpll1clk_in; input [0:0]qpll1freqlock_in; input [0:0]qpll1refclk_in; input [0:0]resetovrd_in; input [0:0]rstclkentx_in; input [0:0]rx8b10ben_in; input [0:0]rxafecfoken_in; input [0:0]rxbufreset_in; input [0:0]rxcdrfreqreset_in; input [0:0]rxcdrhold_in; input [0:0]rxcdrovrden_in; input [0:0]rxcdrreset_in; input [0:0]rxcdrresetrsv_in; input [0:0]rxchbonden_in; input [4:0]rxchbondi_in; input [2:0]rxchbondlevel_in; input [0:0]rxchbondmaster_in; input [0:0]rxchbondslave_in; input [0:0]rxckcalreset_in; input [0:0]rxckcalstart_in; input [0:0]rxcommadeten_in; input [1:0]rxdfeagcctrl_in; input [0:0]rxdccforcestart_in; input [0:0]rxdfeagchold_in; input [0:0]rxdfeagcovrden_in; input [0:0]rxdfecfokfcnum_in; input [0:0]rxdfecfokfen_in; input [0:0]rxdfecfokfpulse_in; input [0:0]rxdfecfokhold_in; input [0:0]rxdfecfokovren_in; input [0:0]rxdfekhhold_in; input [0:0]rxdfekhovrden_in; input [0:0]rxdfelfhold_in; input [0:0]rxdfelfovrden_in; input [0:0]rxdfelpmreset_in; input [0:0]rxdfetap10hold_in; input [0:0]rxdfetap10ovrden_in; input [0:0]rxdfetap11hold_in; input [0:0]rxdfetap11ovrden_in; input [0:0]rxdfetap12hold_in; input [0:0]rxdfetap12ovrden_in; input [0:0]rxdfetap13hold_in; input [0:0]rxdfetap13ovrden_in; input [0:0]rxdfetap14hold_in; input [0:0]rxdfetap14ovrden_in; input [0:0]rxdfetap15hold_in; input [0:0]rxdfetap15ovrden_in; input [0:0]rxdfetap2hold_in; input [0:0]rxdfetap2ovrden_in; input [0:0]rxdfetap3hold_in; input [0:0]rxdfetap3ovrden_in; input [0:0]rxdfetap4hold_in; input [0:0]rxdfetap4ovrden_in; input [0:0]rxdfetap5hold_in; input [0:0]rxdfetap5ovrden_in; input [0:0]rxdfetap6hold_in; input [0:0]rxdfetap6ovrden_in; input [0:0]rxdfetap7hold_in; input [0:0]rxdfetap7ovrden_in; input [0:0]rxdfetap8hold_in; input [0:0]rxdfetap8ovrden_in; input [0:0]rxdfetap9hold_in; input [0:0]rxdfetap9ovrden_in; input [0:0]rxdfeuthold_in; input [0:0]rxdfeutovrden_in; input [0:0]rxdfevphold_in; input [0:0]rxdfevpovrden_in; input [0:0]rxdfevsen_in; input [0:0]rxdfexyden_in; input [0:0]rxdlybypass_in; input [0:0]rxdlyen_in; input [0:0]rxdlyovrden_in; input [0:0]rxdlysreset_in; input [1:0]rxelecidlemode_in; input [0:0]rxeqtraining_in; input [0:0]rxgearboxslip_in; input [0:0]rxlatclk_in; input [0:0]rxlpmen_in; input [0:0]rxlpmgchold_in; input [0:0]rxlpmgcovrden_in; input [0:0]rxlpmhfhold_in; input [0:0]rxlpmhfovrden_in; input [0:0]rxlpmlfhold_in; input [0:0]rxlpmlfklovrden_in; input [0:0]rxlpmoshold_in; input [0:0]rxlpmosovrden_in; input [0:0]rxmcommaalignen_in; input [1:0]rxmonitorsel_in; input [0:0]rxoobreset_in; input [0:0]rxoscalreset_in; input [0:0]rxoshold_in; input [3:0]rxosintcfg_in; input [0:0]rxosinten_in; input [0:0]rxosinthold_in; input [0:0]rxosintovrden_in; input [0:0]rxosintstrobe_in; input [0:0]rxosinttestovrden_in; input [0:0]rxosovrden_in; input [2:0]rxoutclksel_in; input [0:0]rxpcommaalignen_in; input [0:0]rxpcsreset_in; input [1:0]rxpd_in; input [0:0]rxphalign_in; input [0:0]rxphalignen_in; input [0:0]rxphdlypd_in; input [0:0]rxphdlyreset_in; input [0:0]rxphovrden_in; input [1:0]rxpllclksel_in; input [0:0]rxpmareset_in; input [0:0]rxpolarity_in; input [0:0]rxprbscntreset_in; input [3:0]rxprbssel_in; input [0:0]rxprogdivreset_in; input [0:0]rxqpien_in; input [2:0]rxrate_in; input [0:0]rxratemode_in; input [0:0]rxslide_in; input [0:0]rxslipoutclk_in; input [0:0]rxslippma_in; input [0:0]rxsyncallin_in; input [0:0]rxsyncin_in; input [0:0]rxsyncmode_in; input [1:0]rxsysclksel_in; input [0:0]rxtermination_in; input [0:0]rxuserrdy_in; input [0:0]rxusrclk_in; input [0:0]rxusrclk2_in; input [0:0]sigvalidclk_in; input [19:0]tstin_in; input [7:0]tx8b10bbypass_in; input [0:0]tx8b10ben_in; input [2:0]txbufdiffctrl_in; input [0:0]txcominit_in; input [0:0]txcomsas_in; input [0:0]txcomwake_in; input [15:0]txctrl0_in; input [15:0]txctrl1_in; input [7:0]txctrl2_in; input [127:0]txdata_in; input [7:0]txdataextendrsvd_in; input [0:0]txdccforcestart_in; input [0:0]txdccreset_in; input [0:0]txdeemph_in; input [0:0]txdetectrx_in; input [3:0]txdiffctrl_in; input [0:0]txdiffpd_in; input [0:0]txdlybypass_in; input [0:0]txdlyen_in; input [0:0]txdlyhold_in; input [0:0]txdlyovrden_in; input [0:0]txdlysreset_in; input [0:0]txdlyupdown_in; input [0:0]txelecidle_in; input [0:0]txelforcestart_in; input [5:0]txheader_in; input [0:0]txinhibit_in; input [0:0]txlatclk_in; input [0:0]txlfpstreset_in; input [0:0]txlfpsu2lpexit_in; input [0:0]txlfpsu3wake_in; input [6:0]txmaincursor_in; input [2:0]txmargin_in; input [0:0]txmuxdcdexhold_in; input [0:0]txmuxdcdorwren_in; input [0:0]txoneszeros_in; input [2:0]txoutclksel_in; input [0:0]txpcsreset_in; input [1:0]txpd_in; input [0:0]txpdelecidlemode_in; input [0:0]txphalign_in; input [0:0]txphalignen_in; input [0:0]txphdlypd_in; input [0:0]txphdlyreset_in; input [0:0]txphdlytstclk_in; input [0:0]txphinit_in; input [0:0]txphovrden_in; input [0:0]txpippmen_in; input [0:0]txpippmovrden_in; input [0:0]txpippmpd_in; input [0:0]txpippmsel_in; input [4:0]txpippmstepsize_in; input [0:0]txpisopd_in; input [1:0]txpllclksel_in; input [0:0]txpmareset_in; input [0:0]txpolarity_in; input [4:0]txpostcursor_in; input [0:0]txpostcursorinv_in; input [0:0]txprbsforceerr_in; input [3:0]txprbssel_in; input [4:0]txprecursor_in; input [0:0]txprecursorinv_in; input [0:0]txprogdivreset_in; input [0:0]txqpibiasen_in; input [0:0]txqpistrongpdown_in; input [0:0]txqpiweakpup_in; input [2:0]txrate_in; input [0:0]txratemode_in; input [6:0]txsequence_in; input [0:0]txswing_in; input [0:0]txsyncallin_in; input [0:0]txsyncin_in; input [0:0]txsyncmode_in; input [1:0]txsysclksel_in; input [0:0]txuserrdy_in; input [0:0]txusrclk_in; input [0:0]txusrclk2_in; output [2:0]bufgtce_out; output [2:0]bufgtcemask_out; output [8:0]bufgtdiv_out; output [2:0]bufgtreset_out; output [2:0]bufgtrstmask_out; output [0:0]cpllfbclklost_out; output [0:0]cplllock_out; output [0:0]cpllrefclklost_out; output [16:0]dmonitorout_out; output [0:0]dmonitoroutclk_out; output [15:0]drpdo_out; output [0:0]drprdy_out; output [0:0]eyescandataerror_out; output [0:0]gthtxn_out; output [0:0]gthtxp_out; output [0:0]gtpowergood_out; output [0:0]gtrefclkmonitor_out; output [0:0]gtytxn_out; output [0:0]gtytxp_out; output [0:0]pcierategen3_out; output [0:0]pcierateidle_out; output [1:0]pcierateqpllpd_out; output [1:0]pcierateqpllreset_out; output [0:0]pciesynctxsyncdone_out; output [0:0]pcieusergen3rdy_out; output [0:0]pcieuserphystatusrst_out; output [0:0]pcieuserratestart_out; output [11:0]pcsrsvdout_out; output [0:0]phystatus_out; output [7:0]pinrsrvdas_out; output [0:0]powerpresent_out; output [0:0]resetexception_out; output [2:0]rxbufstatus_out; output [0:0]rxbyteisaligned_out; output [0:0]rxbyterealign_out; output [0:0]rxcdrlock_out; output [0:0]rxcdrphdone_out; output [0:0]rxchanbondseq_out; output [0:0]rxchanisaligned_out; output [0:0]rxchanrealign_out; output [4:0]rxchbondo_out; output [0:0]rxckcaldone_out; output [1:0]rxclkcorcnt_out; output [0:0]rxcominitdet_out; output [0:0]rxcommadet_out; output [0:0]rxcomsasdet_out; output [0:0]rxcomwakedet_out; output [15:0]rxctrl0_out; output [15:0]rxctrl1_out; output [7:0]rxctrl2_out; output [7:0]rxctrl3_out; output [127:0]rxdata_out; output [7:0]rxdataextendrsvd_out; output [1:0]rxdatavalid_out; output [0:0]rxdlysresetdone_out; output [0:0]rxelecidle_out; output [5:0]rxheader_out; output [1:0]rxheadervalid_out; output [0:0]rxlfpstresetdet_out; output [0:0]rxlfpsu2lpexitdet_out; output [0:0]rxlfpsu3wakedet_out; output [6:0]rxmonitorout_out; output [0:0]rxosintdone_out; output [0:0]rxosintstarted_out; output [0:0]rxosintstrobedone_out; output [0:0]rxosintstrobestarted_out; output [0:0]rxoutclk_out; output [0:0]rxoutclkfabric_out; output [0:0]rxoutclkpcs_out; output [0:0]rxphaligndone_out; output [0:0]rxphalignerr_out; output [0:0]rxpmaresetdone_out; output [0:0]rxprbserr_out; output [0:0]rxprbslocked_out; output [0:0]rxprgdivresetdone_out; output [0:0]rxqpisenn_out; output [0:0]rxqpisenp_out; output [0:0]rxratedone_out; output [0:0]rxrecclkout_out; output [0:0]rxresetdone_out; output [0:0]rxsliderdy_out; output [0:0]rxslipdone_out; output [0:0]rxslipoutclkrdy_out; output [0:0]rxslippmardy_out; output [1:0]rxstartofseq_out; output [2:0]rxstatus_out; output [0:0]rxsyncdone_out; output [0:0]rxsyncout_out; output [0:0]rxvalid_out; output [1:0]txbufstatus_out; output [0:0]txcomfinish_out; output [0:0]txdccdone_out; output [0:0]txdlysresetdone_out; output [0:0]txoutclk_out; output [0:0]txoutclkfabric_out; output [0:0]txoutclkpcs_out; output [0:0]txphaligndone_out; output [0:0]txphinitdone_out; output [0:0]txpmaresetdone_out; output [0:0]txprgdivresetdone_out; output [0:0]txqpisenn_out; output [0:0]txqpisenp_out; output [0:0]txratedone_out; output [0:0]txresetdone_out; output [0:0]txsyncdone_out; output [0:0]txsyncout_out; wire \ ; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire [0:0]gthrxn_in; wire [0:0]gthrxp_in; wire [0:0]gthtxn_out; wire [0:0]gthtxp_out; wire [0:0]gtpowergood_out; wire [0:0]gtrefclk0_in; wire [0:0]gtwiz_reset_all_in; wire [0:0]gtwiz_reset_rx_datapath_in; wire [0:0]gtwiz_reset_rx_done_out; wire [0:0]gtwiz_reset_tx_datapath_in; wire [0:0]gtwiz_reset_tx_done_out; wire [0:0]gtwiz_userclk_tx_active_in; wire [15:0]gtwiz_userdata_rx_out; wire [15:0]gtwiz_userdata_tx_in; wire [2:2]\^rxbufstatus_out ; wire [1:0]rxclkcorcnt_out; wire [1:0]\^rxctrl0_out ; wire [1:0]\^rxctrl1_out ; wire [1:0]\^rxctrl2_out ; wire [1:0]\^rxctrl3_out ; wire [0:0]rxmcommaalignen_in; wire [0:0]rxoutclk_out; wire [1:0]rxpd_in; wire [0:0]rxusrclk_in; wire [1:1]\^txbufstatus_out ; wire [15:0]txctrl0_in; wire [15:0]txctrl1_in; wire [7:0]txctrl2_in; wire [0:0]txelecidle_in; wire [0:0]txoutclk_out; assign bufgtce_out[2] = \ ; assign bufgtce_out[1] = \ ; assign bufgtce_out[0] = \ ; assign bufgtcemask_out[2] = \ ; assign bufgtcemask_out[1] = \ ; assign bufgtcemask_out[0] = \ ; assign bufgtdiv_out[8] = \ ; assign bufgtdiv_out[7] = \ ; assign bufgtdiv_out[6] = \ ; assign bufgtdiv_out[5] = \ ; assign bufgtdiv_out[4] = \ ; assign bufgtdiv_out[3] = \ ; assign bufgtdiv_out[2] = \ ; assign bufgtdiv_out[1] = \ ; assign bufgtdiv_out[0] = \ ; assign bufgtreset_out[2] = \ ; assign bufgtreset_out[1] = \ ; assign bufgtreset_out[0] = \ ; assign bufgtrstmask_out[2] = \ ; assign bufgtrstmask_out[1] = \ ; assign bufgtrstmask_out[0] = \ ; assign cpllfbclklost_out[0] = \ ; assign cpllrefclklost_out[0] = \ ; assign dmonitorout_out[16] = \ ; assign dmonitorout_out[15] = \ ; assign dmonitorout_out[14] = \ ; assign dmonitorout_out[13] = \ ; assign dmonitorout_out[12] = \ ; assign dmonitorout_out[11] = \ ; assign dmonitorout_out[10] = \ ; assign dmonitorout_out[9] = \ ; assign dmonitorout_out[8] = \ ; assign dmonitorout_out[7] = \ ; assign dmonitorout_out[6] = \ ; assign dmonitorout_out[5] = \ ; assign dmonitorout_out[4] = \ ; assign dmonitorout_out[3] = \ ; assign dmonitorout_out[2] = \ ; assign dmonitorout_out[1] = \ ; assign dmonitorout_out[0] = \ ; assign dmonitoroutclk_out[0] = \ ; assign drpdo_common_out[15] = \ ; assign drpdo_common_out[14] = \ ; assign drpdo_common_out[13] = \ ; assign drpdo_common_out[12] = \ ; assign drpdo_common_out[11] = \ ; assign drpdo_common_out[10] = \ ; assign drpdo_common_out[9] = \ ; assign drpdo_common_out[8] = \ ; assign drpdo_common_out[7] = \ ; assign drpdo_common_out[6] = \ ; assign drpdo_common_out[5] = \ ; assign drpdo_common_out[4] = \ ; assign drpdo_common_out[3] = \ ; assign drpdo_common_out[2] = \ ; assign drpdo_common_out[1] = \ ; assign drpdo_common_out[0] = \ ; assign drpdo_out[15] = \ ; assign drpdo_out[14] = \ ; assign drpdo_out[13] = \ ; assign drpdo_out[12] = \ ; assign drpdo_out[11] = \ ; assign drpdo_out[10] = \ ; assign drpdo_out[9] = \ ; assign drpdo_out[8] = \ ; assign drpdo_out[7] = \ ; assign drpdo_out[6] = \ ; assign drpdo_out[5] = \ ; assign drpdo_out[4] = \ ; assign drpdo_out[3] = \ ; assign drpdo_out[2] = \ ; assign drpdo_out[1] = \ ; assign drpdo_out[0] = \ ; assign drprdy_common_out[0] = \ ; assign drprdy_out[0] = \ ; assign eyescandataerror_out[0] = \ ; assign gtrefclkmonitor_out[0] = \ ; assign gtwiz_buffbypass_rx_done_out[0] = \ ; assign gtwiz_buffbypass_rx_error_out[0] = \ ; assign gtwiz_buffbypass_tx_done_out[0] = \ ; assign gtwiz_buffbypass_tx_error_out[0] = \ ; assign gtwiz_reset_qpll0reset_out[0] = \ ; assign gtwiz_reset_qpll1reset_out[0] = \ ; assign gtwiz_reset_rx_cdr_stable_out[0] = \ ; assign gtwiz_userclk_rx_active_out[0] = \ ; assign gtwiz_userclk_rx_srcclk_out[0] = \ ; assign gtwiz_userclk_rx_usrclk2_out[0] = \ ; assign gtwiz_userclk_rx_usrclk_out[0] = \ ; assign gtwiz_userclk_tx_active_out[0] = \ ; assign gtwiz_userclk_tx_srcclk_out[0] = \ ; assign gtwiz_userclk_tx_usrclk2_out[0] = \ ; assign gtwiz_userclk_tx_usrclk_out[0] = \ ; assign gtytxn_out[0] = \ ; assign gtytxp_out[0] = \ ; assign pcierategen3_out[0] = \ ; assign pcierateidle_out[0] = \ ; assign pcierateqpllpd_out[1] = \ ; assign pcierateqpllpd_out[0] = \ ; assign pcierateqpllreset_out[1] = \ ; assign pcierateqpllreset_out[0] = \ ; assign pciesynctxsyncdone_out[0] = \ ; assign pcieusergen3rdy_out[0] = \ ; assign pcieuserphystatusrst_out[0] = \ ; assign pcieuserratestart_out[0] = \ ; assign pcsrsvdout_out[11] = \ ; assign pcsrsvdout_out[10] = \ ; assign pcsrsvdout_out[9] = \ ; assign pcsrsvdout_out[8] = \ ; assign pcsrsvdout_out[7] = \ ; assign pcsrsvdout_out[6] = \ ; assign pcsrsvdout_out[5] = \ ; assign pcsrsvdout_out[4] = \ ; assign pcsrsvdout_out[3] = \ ; assign pcsrsvdout_out[2] = \ ; assign pcsrsvdout_out[1] = \ ; assign pcsrsvdout_out[0] = \ ; assign phystatus_out[0] = \ ; assign pinrsrvdas_out[7] = \ ; assign pinrsrvdas_out[6] = \ ; assign pinrsrvdas_out[5] = \ ; assign pinrsrvdas_out[4] = \ ; assign pinrsrvdas_out[3] = \ ; assign pinrsrvdas_out[2] = \ ; assign pinrsrvdas_out[1] = \ ; assign pinrsrvdas_out[0] = \ ; assign pmarsvdout0_out[7] = \ ; assign pmarsvdout0_out[6] = \ ; assign pmarsvdout0_out[5] = \ ; assign pmarsvdout0_out[4] = \ ; assign pmarsvdout0_out[3] = \ ; assign pmarsvdout0_out[2] = \ ; assign pmarsvdout0_out[1] = \ ; assign pmarsvdout0_out[0] = \ ; assign pmarsvdout1_out[7] = \ ; assign pmarsvdout1_out[6] = \ ; assign pmarsvdout1_out[5] = \ ; assign pmarsvdout1_out[4] = \ ; assign pmarsvdout1_out[3] = \ ; assign pmarsvdout1_out[2] = \ ; assign pmarsvdout1_out[1] = \ ; assign pmarsvdout1_out[0] = \ ; assign powerpresent_out[0] = \ ; assign qpll0fbclklost_out[0] = \ ; assign qpll0lock_out[0] = \ ; assign qpll0outclk_out[0] = \ ; assign qpll0outrefclk_out[0] = \ ; assign qpll0refclklost_out[0] = \ ; assign qpll1fbclklost_out[0] = \ ; assign qpll1lock_out[0] = \ ; assign qpll1outclk_out[0] = \ ; assign qpll1outrefclk_out[0] = \ ; assign qpll1refclklost_out[0] = \ ; assign qplldmonitor0_out[7] = \ ; assign qplldmonitor0_out[6] = \ ; assign qplldmonitor0_out[5] = \ ; assign qplldmonitor0_out[4] = \ ; assign qplldmonitor0_out[3] = \ ; assign qplldmonitor0_out[2] = \ ; assign qplldmonitor0_out[1] = \ ; assign qplldmonitor0_out[0] = \ ; assign qplldmonitor1_out[7] = \ ; assign qplldmonitor1_out[6] = \ ; assign qplldmonitor1_out[5] = \ ; assign qplldmonitor1_out[4] = \ ; assign qplldmonitor1_out[3] = \ ; assign qplldmonitor1_out[2] = \ ; assign qplldmonitor1_out[1] = \ ; assign qplldmonitor1_out[0] = \ ; assign refclkoutmonitor0_out[0] = \ ; assign refclkoutmonitor1_out[0] = \ ; assign resetexception_out[0] = \ ; assign rxbufstatus_out[2] = \^rxbufstatus_out [2]; assign rxbufstatus_out[1] = \ ; assign rxbufstatus_out[0] = \ ; assign rxbyteisaligned_out[0] = \ ; assign rxbyterealign_out[0] = \ ; assign rxcdrlock_out[0] = \ ; assign rxcdrphdone_out[0] = \ ; assign rxchanbondseq_out[0] = \ ; assign rxchanisaligned_out[0] = \ ; assign rxchanrealign_out[0] = \ ; assign rxchbondo_out[4] = \ ; assign rxchbondo_out[3] = \ ; assign rxchbondo_out[2] = \ ; assign rxchbondo_out[1] = \ ; assign rxchbondo_out[0] = \ ; assign rxckcaldone_out[0] = \ ; assign rxcominitdet_out[0] = \ ; assign rxcommadet_out[0] = \ ; assign rxcomsasdet_out[0] = \ ; assign rxcomwakedet_out[0] = \ ; assign rxctrl0_out[15] = \ ; assign rxctrl0_out[14] = \ ; assign rxctrl0_out[13] = \ ; assign rxctrl0_out[12] = \ ; assign rxctrl0_out[11] = \ ; assign rxctrl0_out[10] = \ ; assign rxctrl0_out[9] = \ ; assign rxctrl0_out[8] = \ ; assign rxctrl0_out[7] = \ ; assign rxctrl0_out[6] = \ ; assign rxctrl0_out[5] = \ ; assign rxctrl0_out[4] = \ ; assign rxctrl0_out[3] = \ ; assign rxctrl0_out[2] = \ ; assign rxctrl0_out[1:0] = \^rxctrl0_out [1:0]; assign rxctrl1_out[15] = \ ; assign rxctrl1_out[14] = \ ; assign rxctrl1_out[13] = \ ; assign rxctrl1_out[12] = \ ; assign rxctrl1_out[11] = \ ; assign rxctrl1_out[10] = \ ; assign rxctrl1_out[9] = \ ; assign rxctrl1_out[8] = \ ; assign rxctrl1_out[7] = \ ; assign rxctrl1_out[6] = \ ; assign rxctrl1_out[5] = \ ; assign rxctrl1_out[4] = \ ; assign rxctrl1_out[3] = \ ; assign rxctrl1_out[2] = \ ; assign rxctrl1_out[1:0] = \^rxctrl1_out [1:0]; assign rxctrl2_out[7] = \ ; assign rxctrl2_out[6] = \ ; assign rxctrl2_out[5] = \ ; assign rxctrl2_out[4] = \ ; assign rxctrl2_out[3] = \ ; assign rxctrl2_out[2] = \ ; assign rxctrl2_out[1:0] = \^rxctrl2_out [1:0]; assign rxctrl3_out[7] = \ ; assign rxctrl3_out[6] = \ ; assign rxctrl3_out[5] = \ ; assign rxctrl3_out[4] = \ ; assign rxctrl3_out[3] = \ ; assign rxctrl3_out[2] = \ ; assign rxctrl3_out[1:0] = \^rxctrl3_out [1:0]; assign rxdata_out[127] = \ ; assign rxdata_out[126] = \ ; assign rxdata_out[125] = \ ; assign rxdata_out[124] = \ ; assign rxdata_out[123] = \ ; assign rxdata_out[122] = \ ; assign rxdata_out[121] = \ ; assign rxdata_out[120] = \ ; assign rxdata_out[119] = \ ; assign rxdata_out[118] = \ ; assign rxdata_out[117] = \ ; assign rxdata_out[116] = \ ; assign rxdata_out[115] = \ ; assign rxdata_out[114] = \ ; assign rxdata_out[113] = \ ; assign rxdata_out[112] = \ ; assign rxdata_out[111] = \ ; assign rxdata_out[110] = \ ; assign rxdata_out[109] = \ ; assign rxdata_out[108] = \ ; assign rxdata_out[107] = \ ; assign rxdata_out[106] = \ ; assign rxdata_out[105] = \ ; assign rxdata_out[104] = \ ; assign rxdata_out[103] = \ ; assign rxdata_out[102] = \ ; assign rxdata_out[101] = \ ; assign rxdata_out[100] = \ ; assign rxdata_out[99] = \ ; assign rxdata_out[98] = \ ; assign rxdata_out[97] = \ ; assign rxdata_out[96] = \ ; assign rxdata_out[95] = \ ; assign rxdata_out[94] = \ ; assign rxdata_out[93] = \ ; assign rxdata_out[92] = \ ; assign rxdata_out[91] = \ ; assign rxdata_out[90] = \ ; assign rxdata_out[89] = \ ; assign rxdata_out[88] = \ ; assign rxdata_out[87] = \ ; assign rxdata_out[86] = \ ; assign rxdata_out[85] = \ ; assign rxdata_out[84] = \ ; assign rxdata_out[83] = \ ; assign rxdata_out[82] = \ ; assign rxdata_out[81] = \ ; assign rxdata_out[80] = \ ; assign rxdata_out[79] = \ ; assign rxdata_out[78] = \ ; assign rxdata_out[77] = \ ; assign rxdata_out[76] = \ ; assign rxdata_out[75] = \ ; assign rxdata_out[74] = \ ; assign rxdata_out[73] = \ ; assign rxdata_out[72] = \ ; assign rxdata_out[71] = \ ; assign rxdata_out[70] = \ ; assign rxdata_out[69] = \ ; assign rxdata_out[68] = \ ; assign rxdata_out[67] = \ ; assign rxdata_out[66] = \ ; assign rxdata_out[65] = \ ; assign rxdata_out[64] = \ ; assign rxdata_out[63] = \ ; assign rxdata_out[62] = \ ; assign rxdata_out[61] = \ ; assign rxdata_out[60] = \ ; assign rxdata_out[59] = \ ; assign rxdata_out[58] = \ ; assign rxdata_out[57] = \ ; assign rxdata_out[56] = \ ; assign rxdata_out[55] = \ ; assign rxdata_out[54] = \ ; assign rxdata_out[53] = \ ; assign rxdata_out[52] = \ ; assign rxdata_out[51] = \ ; assign rxdata_out[50] = \ ; assign rxdata_out[49] = \ ; assign rxdata_out[48] = \ ; assign rxdata_out[47] = \ ; assign rxdata_out[46] = \ ; assign rxdata_out[45] = \ ; assign rxdata_out[44] = \ ; assign rxdata_out[43] = \ ; assign rxdata_out[42] = \ ; assign rxdata_out[41] = \ ; assign rxdata_out[40] = \ ; assign rxdata_out[39] = \ ; assign rxdata_out[38] = \ ; assign rxdata_out[37] = \ ; assign rxdata_out[36] = \ ; assign rxdata_out[35] = \ ; assign rxdata_out[34] = \ ; assign rxdata_out[33] = \ ; assign rxdata_out[32] = \ ; assign rxdata_out[31] = \ ; assign rxdata_out[30] = \ ; assign rxdata_out[29] = \ ; assign rxdata_out[28] = \ ; assign rxdata_out[27] = \ ; assign rxdata_out[26] = \ ; assign rxdata_out[25] = \ ; assign rxdata_out[24] = \ ; assign rxdata_out[23] = \ ; assign rxdata_out[22] = \ ; assign rxdata_out[21] = \ ; assign rxdata_out[20] = \ ; assign rxdata_out[19] = \ ; assign rxdata_out[18] = \ ; assign rxdata_out[17] = \ ; assign rxdata_out[16] = \ ; assign rxdata_out[15] = \ ; assign rxdata_out[14] = \ ; assign rxdata_out[13] = \ ; assign rxdata_out[12] = \ ; assign rxdata_out[11] = \ ; assign rxdata_out[10] = \ ; assign rxdata_out[9] = \ ; assign rxdata_out[8] = \ ; assign rxdata_out[7] = \ ; assign rxdata_out[6] = \ ; assign rxdata_out[5] = \ ; assign rxdata_out[4] = \ ; assign rxdata_out[3] = \ ; assign rxdata_out[2] = \ ; assign rxdata_out[1] = \ ; assign rxdata_out[0] = \ ; assign rxdataextendrsvd_out[7] = \ ; assign rxdataextendrsvd_out[6] = \ ; assign rxdataextendrsvd_out[5] = \ ; assign rxdataextendrsvd_out[4] = \ ; assign rxdataextendrsvd_out[3] = \ ; assign rxdataextendrsvd_out[2] = \ ; assign rxdataextendrsvd_out[1] = \ ; assign rxdataextendrsvd_out[0] = \ ; assign rxdatavalid_out[1] = \ ; assign rxdatavalid_out[0] = \ ; assign rxdlysresetdone_out[0] = \ ; assign rxelecidle_out[0] = \ ; assign rxheader_out[5] = \ ; assign rxheader_out[4] = \ ; assign rxheader_out[3] = \ ; assign rxheader_out[2] = \ ; assign rxheader_out[1] = \ ; assign rxheader_out[0] = \ ; assign rxheadervalid_out[1] = \ ; assign rxheadervalid_out[0] = \ ; assign rxlfpstresetdet_out[0] = \ ; assign rxlfpsu2lpexitdet_out[0] = \ ; assign rxlfpsu3wakedet_out[0] = \ ; assign rxmonitorout_out[6] = \ ; assign rxmonitorout_out[5] = \ ; assign rxmonitorout_out[4] = \ ; assign rxmonitorout_out[3] = \ ; assign rxmonitorout_out[2] = \ ; assign rxmonitorout_out[1] = \ ; assign rxmonitorout_out[0] = \ ; assign rxosintdone_out[0] = \ ; assign rxosintstarted_out[0] = \ ; assign rxosintstrobedone_out[0] = \ ; assign rxosintstrobestarted_out[0] = \ ; assign rxoutclkfabric_out[0] = \ ; assign rxoutclkpcs_out[0] = \ ; assign rxphaligndone_out[0] = \ ; assign rxphalignerr_out[0] = \ ; assign rxpmaresetdone_out[0] = \ ; assign rxprbserr_out[0] = \ ; assign rxprbslocked_out[0] = \ ; assign rxprgdivresetdone_out[0] = \ ; assign rxqpisenn_out[0] = \ ; assign rxqpisenp_out[0] = \ ; assign rxratedone_out[0] = \ ; assign rxrecclk0_sel_out[1] = \ ; assign rxrecclk0_sel_out[0] = \ ; assign rxrecclk0sel_out[0] = \ ; assign rxrecclk1_sel_out[1] = \ ; assign rxrecclk1_sel_out[0] = \ ; assign rxrecclk1sel_out[0] = \ ; assign rxrecclkout_out[0] = \ ; assign rxresetdone_out[0] = \ ; assign rxsliderdy_out[0] = \ ; assign rxslipdone_out[0] = \ ; assign rxslipoutclkrdy_out[0] = \ ; assign rxslippmardy_out[0] = \ ; assign rxstartofseq_out[1] = \ ; assign rxstartofseq_out[0] = \ ; assign rxstatus_out[2] = \ ; assign rxstatus_out[1] = \ ; assign rxstatus_out[0] = \ ; assign rxsyncdone_out[0] = \ ; assign rxsyncout_out[0] = \ ; assign rxvalid_out[0] = \ ; assign sdm0finalout_out[0] = \ ; assign sdm0testdata_out[0] = \ ; assign sdm1finalout_out[0] = \ ; assign sdm1testdata_out[0] = \ ; assign tcongpo_out[0] = \ ; assign tconrsvdout0_out[0] = \ ; assign txbufstatus_out[1] = \^txbufstatus_out [1]; assign txbufstatus_out[0] = \ ; assign txcomfinish_out[0] = \ ; assign txdccdone_out[0] = \ ; assign txdlysresetdone_out[0] = \ ; assign txoutclkfabric_out[0] = \ ; assign txoutclkpcs_out[0] = \ ; assign txphaligndone_out[0] = \ ; assign txphinitdone_out[0] = \ ; assign txpmaresetdone_out[0] = \ ; assign txprgdivresetdone_out[0] = \ ; assign txqpisenn_out[0] = \ ; assign txqpisenp_out[0] = \ ; assign txratedone_out[0] = \ ; assign txresetdone_out[0] = \ ; assign txsyncdone_out[0] = \ ; assign txsyncout_out[0] = \ ; assign ubdaddr_out[0] = \ ; assign ubden_out[0] = \ ; assign ubdi_out[0] = \ ; assign ubdwe_out[0] = \ ; assign ubmdmtdo_out[0] = \ ; assign ubrsvdout_out[0] = \ ; assign ubtxuart_out[0] = \ ; GND GND (.G(\ )); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3 \gen_gtwizard_gthe3_top.gig_ethernet_pcs_pma_0_gt_gtwizard_gthe3_inst (.cplllock_out(cplllock_out), .drpclk_in(drpclk_in), .gthrxn_in(gthrxn_in), .gthrxp_in(gthrxp_in), .gthtxn_out(gthtxn_out), .gthtxp_out(gthtxp_out), .gtpowergood_out(gtpowergood_out), .gtrefclk0_in(gtrefclk0_in), .gtwiz_reset_all_in(gtwiz_reset_all_in), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out), .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in), .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out), .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in), .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out), .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in), .rxbufstatus_out(\^rxbufstatus_out ), .rxclkcorcnt_out(rxclkcorcnt_out), .rxctrl0_out(\^rxctrl0_out ), .rxctrl1_out(\^rxctrl1_out ), .rxctrl2_out(\^rxctrl2_out ), .rxctrl3_out(\^rxctrl3_out ), .rxmcommaalignen_in(rxmcommaalignen_in), .rxoutclk_out(rxoutclk_out), .rxpd_in(rxpd_in[1]), .rxusrclk_in(rxusrclk_in), .txbufstatus_out(\^txbufstatus_out ), .txctrl0_in(txctrl0_in[1:0]), .txctrl1_in(txctrl1_in[1:0]), .txctrl2_in(txctrl2_in[1:0]), .txelecidle_in(txelecidle_in), .txoutclk_out(txoutclk_out)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_reset_sync (reset_out, rxuserclk2, gtwiz_reset_rx_done_out); output reset_out; input rxuserclk2; input [0:0]gtwiz_reset_rx_done_out; wire [0:0]gtwiz_reset_rx_done_out; wire reset_out; wire reset_sync_reg1; wire reset_sync_reg2; wire reset_sync_reg3; wire reset_sync_reg4; wire reset_sync_reg5; wire rxuserclk2; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync1 (.C(rxuserclk2), .CE(1'b1), .D(1'b0), .PRE(gtwiz_reset_rx_done_out), .Q(reset_sync_reg1)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync2 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg1), .PRE(gtwiz_reset_rx_done_out), .Q(reset_sync_reg2)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync3 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg2), .PRE(gtwiz_reset_rx_done_out), .Q(reset_sync_reg3)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync4 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg3), .PRE(gtwiz_reset_rx_done_out), .Q(reset_sync_reg4)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync5 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg4), .PRE(gtwiz_reset_rx_done_out), .Q(reset_sync_reg5)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync6 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg5), .PRE(1'b0), .Q(reset_out)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_0_reset_sync" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_reset_sync_0 (gtwiz_reset_rx_done_out_int_reg0, reset_out, rxuserclk2, SR); output gtwiz_reset_rx_done_out_int_reg0; input reset_out; input rxuserclk2; input [0:0]SR; wire [0:0]SR; wire gtwiz_reset_rx_done_out_int_reg0; wire reset_out; wire reset_sync_reg1; wire reset_sync_reg2; wire reset_sync_reg3; wire reset_sync_reg4; wire reset_sync_reg5; wire rxreset_int; wire rxuserclk2; LUT2 #( .INIT(4'h8)) gtwiz_reset_rx_done_out_int_reg_i_1 (.I0(rxreset_int), .I1(reset_out), .O(gtwiz_reset_rx_done_out_int_reg0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync1 (.C(rxuserclk2), .CE(1'b1), .D(1'b0), .PRE(SR), .Q(reset_sync_reg1)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync2 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg1), .PRE(SR), .Q(reset_sync_reg2)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync3 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg2), .PRE(SR), .Q(reset_sync_reg3)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync4 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg3), .PRE(SR), .Q(reset_sync_reg4)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync5 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg4), .PRE(SR), .Q(reset_sync_reg5)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync6 (.C(rxuserclk2), .CE(1'b1), .D(reset_sync_reg5), .PRE(1'b0), .Q(rxreset_int)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_0_reset_sync" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_reset_sync_1 (gtwiz_reset_tx_done_out_int_reg0, gtwiz_reset_tx_done_out, userclk, txreset); output gtwiz_reset_tx_done_out_int_reg0; input [0:0]gtwiz_reset_tx_done_out; input userclk; input txreset; wire [0:0]gtwiz_reset_tx_done_out; wire gtwiz_reset_tx_done_out_int_reg0; wire reset_sync_reg1; wire reset_sync_reg2; wire reset_sync_reg3; wire reset_sync_reg4; wire reset_sync_reg5; wire txreset; wire txreset_int; wire userclk; LUT2 #( .INIT(4'h8)) gtwiz_reset_tx_done_out_int_reg_i_1 (.I0(txreset_int), .I1(gtwiz_reset_tx_done_out), .O(gtwiz_reset_tx_done_out_int_reg0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync1 (.C(userclk), .CE(1'b1), .D(1'b0), .PRE(txreset), .Q(reset_sync_reg1)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync2 (.C(userclk), .CE(1'b1), .D(reset_sync_reg1), .PRE(txreset), .Q(reset_sync_reg2)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync3 (.C(userclk), .CE(1'b1), .D(reset_sync_reg2), .PRE(txreset), .Q(reset_sync_reg3)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync4 (.C(userclk), .CE(1'b1), .D(reset_sync_reg3), .PRE(txreset), .Q(reset_sync_reg4)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync5 (.C(userclk), .CE(1'b1), .D(reset_sync_reg4), .PRE(txreset), .Q(reset_sync_reg5)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync6 (.C(userclk), .CE(1'b1), .D(reset_sync_reg5), .PRE(1'b0), .Q(txreset_int)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_0_reset_sync" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_reset_sync_2 (reset_out, userclk2, enablealign); output reset_out; input userclk2; input enablealign; wire enablealign; wire reset_out; wire reset_sync_reg1; wire reset_sync_reg2; wire reset_sync_reg3; wire reset_sync_reg4; wire reset_sync_reg5; wire userclk2; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync1 (.C(userclk2), .CE(1'b1), .D(1'b0), .PRE(enablealign), .Q(reset_sync_reg1)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync2 (.C(userclk2), .CE(1'b1), .D(reset_sync_reg1), .PRE(enablealign), .Q(reset_sync_reg2)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync3 (.C(userclk2), .CE(1'b1), .D(reset_sync_reg2), .PRE(enablealign), .Q(reset_sync_reg3)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync4 (.C(userclk2), .CE(1'b1), .D(reset_sync_reg3), .PRE(enablealign), .Q(reset_sync_reg4)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync5 (.C(userclk2), .CE(1'b1), .D(reset_sync_reg4), .PRE(enablealign), .Q(reset_sync_reg5)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync6 (.C(userclk2), .CE(1'b1), .D(reset_sync_reg5), .PRE(1'b0), .Q(reset_out)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_sync_block (resetdone, data_in, userclk2); output resetdone; input data_in; input userclk2; wire data_in; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire resetdone; wire userclk2; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(userclk2), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(userclk2), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(userclk2), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(userclk2), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(userclk2), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(userclk2), .CE(1'b1), .D(data_sync5), .Q(resetdone), .R(1'b0)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_transceiver (cplllock, txn, txp, gtpowergood, rxoutclk, txoutclk, rxchariscomma, rxcharisk, Q, \rxdata_reg[7]_0 , rxdisperr, rxnotintable, rxbuferr, txbuferr, data_in, mmcm_reset, userclk2, enablealign, userclk, txreset, rxuserclk2, SR, mmcm_locked, pma_reset, independent_clock_bufg, rxn, rxp, gtrefclk, D, powerdown, txchardispval_reg_reg_0, txchardispmode_reg_reg_0, txcharisk_reg_reg_0); output cplllock; output txn; output txp; output gtpowergood; output rxoutclk; output txoutclk; output rxchariscomma; output rxcharisk; output [1:0]Q; output [7:0]\rxdata_reg[7]_0 ; output rxdisperr; output rxnotintable; output rxbuferr; output txbuferr; output data_in; output mmcm_reset; input userclk2; input enablealign; input userclk; input txreset; input rxuserclk2; input [0:0]SR; input mmcm_locked; input pma_reset; input independent_clock_bufg; input rxn; input rxp; input gtrefclk; input [7:0]D; input powerdown; input [0:0]txchardispval_reg_reg_0; input [0:0]txchardispmode_reg_reg_0; input [0:0]txcharisk_reg_reg_0; wire [7:0]D; wire [1:0]Q; wire [0:0]SR; wire cplllock; wire data_in; wire enablealign; wire encommaalign_int; wire gig_ethernet_pcs_pma_0_gt_i_n_118; wire gig_ethernet_pcs_pma_0_gt_i_n_58; wire gtpowergood; wire gtrefclk; wire gtwiz_reset_rx_done_out_int; wire gtwiz_reset_rx_done_out_int_reg; wire gtwiz_reset_rx_done_out_int_reg0; wire gtwiz_reset_rx_done_out_reg; wire gtwiz_reset_tx_done_out_int; wire gtwiz_reset_tx_done_out_int_reg; wire gtwiz_reset_tx_done_out_int_reg0; wire independent_clock_bufg; wire mmcm_locked; wire mmcm_reset; wire p_0_in; wire [7:0]p_1_in; wire [0:0]p_1_in__0; wire [0:0]p_1_in__1; wire [0:0]p_1_in__2; wire pma_reset; wire powerdown; wire rxbuferr; wire rxchariscomma; wire [1:0]rxchariscomma_double; wire rxchariscomma_i_1_n_0; wire [1:0]rxchariscomma_reg__0; wire rxcharisk; wire [1:0]rxcharisk_double; wire rxcharisk_i_1_n_0; wire [1:0]rxcharisk_reg__0; wire [1:0]rxclkcorcnt_double; wire [1:0]rxclkcorcnt_int; wire [1:0]rxclkcorcnt_reg; wire [1:0]rxctrl0_out; wire [1:0]rxctrl1_out; wire [1:0]rxctrl2_out; wire [1:0]rxctrl3_out; wire \rxdata[0]_i_1_n_0 ; wire \rxdata[1]_i_1_n_0 ; wire \rxdata[2]_i_1_n_0 ; wire \rxdata[3]_i_1_n_0 ; wire \rxdata[4]_i_1_n_0 ; wire \rxdata[5]_i_1_n_0 ; wire \rxdata[6]_i_1_n_0 ; wire \rxdata[7]_i_1_n_0 ; wire [15:0]rxdata_double; wire [15:0]rxdata_int; wire [15:0]rxdata_reg; wire [7:0]\rxdata_reg[7]_0 ; wire rxdisperr; wire [1:0]rxdisperr_double; wire rxdisperr_i_1_n_0; wire [1:0]rxdisperr_reg__0; wire rxn; wire rxnotintable; wire [1:0]rxnotintable_double; wire rxnotintable_i_1_n_0; wire [1:0]rxnotintable_reg__0; wire rxoutclk; wire rxp; wire rxpowerdown; wire rxpowerdown_double; wire rxpowerdown_reg__0; wire rxuserclk2; wire toggle; wire toggle_i_1_n_0; wire txbuferr; wire [1:1]txbufstatus_reg; wire [1:0]txchardispmode_double; wire [1:0]txchardispmode_int; wire [0:0]txchardispmode_reg_reg_0; wire [1:0]txchardispval_double; wire [1:0]txchardispval_int; wire [0:0]txchardispval_reg_reg_0; wire [1:0]txcharisk_double; wire [1:0]txcharisk_int; wire [0:0]txcharisk_reg_reg_0; wire [15:0]txdata_double; wire [15:0]txdata_int; wire txn; wire txoutclk; wire txp; wire txpowerdown; wire txpowerdown_double; wire txpowerdown_reg__0; wire txreset; wire userclk; wire userclk2; wire [16:0]NLW_gig_ethernet_pcs_pma_0_gt_i_dmonitorout_out_UNCONNECTED; wire [15:0]NLW_gig_ethernet_pcs_pma_0_gt_i_drpdo_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_drprdy_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_eyescandataerror_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED; wire [1:0]NLW_gig_ethernet_pcs_pma_0_gt_i_rxbufstatus_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_rxbyteisaligned_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_rxbyterealign_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_rxcommadet_out_UNCONNECTED; wire [15:2]NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl0_out_UNCONNECTED; wire [15:2]NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl1_out_UNCONNECTED; wire [7:2]NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl2_out_UNCONNECTED; wire [7:2]NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl3_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_rxpmaresetdone_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_rxprbserr_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_rxresetdone_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_txbufstatus_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_txpmaresetdone_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_txprgdivresetdone_out_UNCONNECTED; wire [0:0]NLW_gig_ethernet_pcs_pma_0_gt_i_txresetdone_out_UNCONNECTED; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_reset_sync SYNC_ASYNC_RESET_GT_RX (.gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out_int), .reset_out(gtwiz_reset_rx_done_out_reg), .rxuserclk2(rxuserclk2)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_reset_sync_0 SYNC_ASYNC_RESET_RX (.SR(SR), .gtwiz_reset_rx_done_out_int_reg0(gtwiz_reset_rx_done_out_int_reg0), .reset_out(gtwiz_reset_rx_done_out_reg), .rxuserclk2(rxuserclk2)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_reset_sync_1 SYNC_ASYNC_RESET_TX (.gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out_int), .gtwiz_reset_tx_done_out_int_reg0(gtwiz_reset_tx_done_out_int_reg0), .txreset(txreset), .userclk(userclk)); LUT2 #( .INIT(4'h8)) data_sync1_i_1 (.I0(gtwiz_reset_tx_done_out_int), .I1(gtwiz_reset_rx_done_out_int), .O(data_in)); (* CHECK_LICENSE_TYPE = "gig_ethernet_pcs_pma_0_gt,gig_ethernet_pcs_pma_0_gt_gtwizard_top,{}" *) (* X_CORE_INFO = "gig_ethernet_pcs_pma_0_gt_gtwizard_top,Vivado 2020.2" *) (* downgradeipidentifiedwarnings = "yes" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_gt gig_ethernet_pcs_pma_0_gt_i (.cplllock_out(cplllock), .cpllrefclksel_in({1'b0,1'b0,1'b1}), .dmonitorout_out(NLW_gig_ethernet_pcs_pma_0_gt_i_dmonitorout_out_UNCONNECTED[16:0]), .drpaddr_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drpclk_in(independent_clock_bufg), .drpdi_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drpdo_out(NLW_gig_ethernet_pcs_pma_0_gt_i_drpdo_out_UNCONNECTED[15:0]), .drpen_in(1'b0), .drprdy_out(NLW_gig_ethernet_pcs_pma_0_gt_i_drprdy_out_UNCONNECTED[0]), .drpwe_in(1'b0), .eyescandataerror_out(NLW_gig_ethernet_pcs_pma_0_gt_i_eyescandataerror_out_UNCONNECTED[0]), .eyescanreset_in(1'b0), .eyescantrigger_in(1'b0), .gthrxn_in(rxn), .gthrxp_in(rxp), .gthtxn_out(txn), .gthtxp_out(txp), .gtpowergood_out(gtpowergood), .gtrefclk0_in(gtrefclk), .gtrefclk1_in(1'b0), .gtwiz_reset_all_in(pma_reset), .gtwiz_reset_clk_freerun_in(1'b0), .gtwiz_reset_rx_cdr_stable_out(NLW_gig_ethernet_pcs_pma_0_gt_i_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED[0]), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_done_out_int_reg), .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out_int), .gtwiz_reset_rx_pll_and_datapath_in(1'b0), .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_done_out_int_reg), .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out_int), .gtwiz_reset_tx_pll_and_datapath_in(1'b0), .gtwiz_userclk_rx_active_in(1'b0), .gtwiz_userclk_tx_active_in(mmcm_locked), .gtwiz_userdata_rx_out(rxdata_int), .gtwiz_userdata_tx_in(txdata_int), .loopback_in({1'b0,1'b0,1'b0}), .pcsrsvdin_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rx8b10ben_in(1'b1), .rxbufreset_in(1'b0), .rxbufstatus_out({gig_ethernet_pcs_pma_0_gt_i_n_58,NLW_gig_ethernet_pcs_pma_0_gt_i_rxbufstatus_out_UNCONNECTED[1:0]}), .rxbyteisaligned_out(NLW_gig_ethernet_pcs_pma_0_gt_i_rxbyteisaligned_out_UNCONNECTED[0]), .rxbyterealign_out(NLW_gig_ethernet_pcs_pma_0_gt_i_rxbyterealign_out_UNCONNECTED[0]), .rxcdrhold_in(1'b0), .rxclkcorcnt_out(rxclkcorcnt_int), .rxcommadet_out(NLW_gig_ethernet_pcs_pma_0_gt_i_rxcommadet_out_UNCONNECTED[0]), .rxcommadeten_in(1'b1), .rxctrl0_out({NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl0_out_UNCONNECTED[15:2],rxctrl0_out}), .rxctrl1_out({NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl1_out_UNCONNECTED[15:2],rxctrl1_out}), .rxctrl2_out({NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl2_out_UNCONNECTED[7:2],rxctrl2_out}), .rxctrl3_out({NLW_gig_ethernet_pcs_pma_0_gt_i_rxctrl3_out_UNCONNECTED[7:2],rxctrl3_out}), .rxdfelpmreset_in(1'b0), .rxlpmen_in(1'b1), .rxmcommaalignen_in(encommaalign_int), .rxoutclk_out(rxoutclk), .rxpcommaalignen_in(1'b0), .rxpcsreset_in(1'b0), .rxpd_in({rxpowerdown,1'b0}), .rxpmareset_in(1'b0), .rxpmaresetdone_out(NLW_gig_ethernet_pcs_pma_0_gt_i_rxpmaresetdone_out_UNCONNECTED[0]), .rxpolarity_in(1'b0), .rxprbscntreset_in(1'b0), .rxprbserr_out(NLW_gig_ethernet_pcs_pma_0_gt_i_rxprbserr_out_UNCONNECTED[0]), .rxprbssel_in({1'b0,1'b0,1'b0,1'b0}), .rxrate_in({1'b0,1'b0,1'b0}), .rxresetdone_out(NLW_gig_ethernet_pcs_pma_0_gt_i_rxresetdone_out_UNCONNECTED[0]), .rxusrclk2_in(1'b0), .rxusrclk_in(userclk), .tx8b10ben_in(1'b1), .txbufstatus_out({gig_ethernet_pcs_pma_0_gt_i_n_118,NLW_gig_ethernet_pcs_pma_0_gt_i_txbufstatus_out_UNCONNECTED[0]}), .txctrl0_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txchardispval_int}), .txctrl1_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txchardispmode_int}), .txctrl2_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txcharisk_int}), .txdiffctrl_in({1'b1,1'b0,1'b0,1'b0}), .txelecidle_in(txpowerdown), .txinhibit_in(1'b0), .txoutclk_out(txoutclk), .txpcsreset_in(1'b0), .txpd_in({1'b0,1'b0}), .txpmareset_in(1'b0), .txpmaresetdone_out(NLW_gig_ethernet_pcs_pma_0_gt_i_txpmaresetdone_out_UNCONNECTED[0]), .txpolarity_in(1'b0), .txpostcursor_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .txprbsforceerr_in(1'b0), .txprbssel_in({1'b0,1'b0,1'b0,1'b0}), .txprecursor_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .txprgdivresetdone_out(NLW_gig_ethernet_pcs_pma_0_gt_i_txprgdivresetdone_out_UNCONNECTED[0]), .txresetdone_out(NLW_gig_ethernet_pcs_pma_0_gt_i_txresetdone_out_UNCONNECTED[0]), .txusrclk2_in(1'b0), .txusrclk_in(1'b0)); FDRE #( .INIT(1'b0)) gtwiz_reset_rx_done_out_int_reg_reg (.C(rxuserclk2), .CE(1'b1), .D(gtwiz_reset_rx_done_out_int_reg0), .Q(gtwiz_reset_rx_done_out_int_reg), .R(1'b0)); FDRE #( .INIT(1'b0)) gtwiz_reset_tx_done_out_int_reg_reg (.C(userclk), .CE(1'b1), .D(gtwiz_reset_tx_done_out_int_reg0), .Q(gtwiz_reset_tx_done_out_int_reg), .R(1'b0)); LUT1 #( .INIT(2'h1)) mmcm_reset_INST_0 (.I0(cplllock), .O(mmcm_reset)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_0_reset_sync_2 reclock_encommaalign (.enablealign(enablealign), .reset_out(encommaalign_int), .userclk2(userclk2)); FDRE rxbuferr_reg (.C(userclk2), .CE(1'b1), .D(p_0_in), .Q(rxbuferr), .R(1'b0)); FDRE \rxbufstatus_reg_reg[2] (.C(userclk), .CE(1'b1), .D(gig_ethernet_pcs_pma_0_gt_i_n_58), .Q(p_0_in), .R(1'b0)); FDRE \rxchariscomma_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxchariscomma_reg__0[0]), .Q(rxchariscomma_double[0]), .R(SR)); FDRE \rxchariscomma_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxchariscomma_reg__0[1]), .Q(rxchariscomma_double[1]), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT3 #( .INIT(8'hB8)) rxchariscomma_i_1 (.I0(rxchariscomma_double[1]), .I1(toggle), .I2(rxchariscomma_double[0]), .O(rxchariscomma_i_1_n_0)); FDRE rxchariscomma_reg (.C(userclk2), .CE(1'b1), .D(rxchariscomma_i_1_n_0), .Q(rxchariscomma), .R(SR)); FDRE \rxchariscomma_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxctrl2_out[0]), .Q(rxchariscomma_reg__0[0]), .R(1'b0)); FDRE \rxchariscomma_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxctrl2_out[1]), .Q(rxchariscomma_reg__0[1]), .R(1'b0)); FDRE \rxcharisk_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxcharisk_reg__0[0]), .Q(rxcharisk_double[0]), .R(SR)); FDRE \rxcharisk_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxcharisk_reg__0[1]), .Q(rxcharisk_double[1]), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT3 #( .INIT(8'hB8)) rxcharisk_i_1 (.I0(rxcharisk_double[1]), .I1(toggle), .I2(rxcharisk_double[0]), .O(rxcharisk_i_1_n_0)); FDRE rxcharisk_reg (.C(userclk2), .CE(1'b1), .D(rxcharisk_i_1_n_0), .Q(rxcharisk), .R(SR)); FDRE \rxcharisk_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxctrl0_out[0]), .Q(rxcharisk_reg__0[0]), .R(1'b0)); FDRE \rxcharisk_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxctrl0_out[1]), .Q(rxcharisk_reg__0[1]), .R(1'b0)); FDRE \rxclkcorcnt_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxclkcorcnt_reg[0]), .Q(rxclkcorcnt_double[0]), .R(SR)); FDRE \rxclkcorcnt_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxclkcorcnt_reg[1]), .Q(rxclkcorcnt_double[1]), .R(SR)); FDRE \rxclkcorcnt_reg[0] (.C(userclk2), .CE(1'b1), .D(rxclkcorcnt_double[0]), .Q(Q[0]), .R(SR)); FDRE \rxclkcorcnt_reg[1] (.C(userclk2), .CE(1'b1), .D(rxclkcorcnt_double[1]), .Q(Q[1]), .R(SR)); FDRE \rxclkcorcnt_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxclkcorcnt_int[0]), .Q(rxclkcorcnt_reg[0]), .R(1'b0)); FDRE \rxclkcorcnt_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxclkcorcnt_int[1]), .Q(rxclkcorcnt_reg[1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT3 #( .INIT(8'hB8)) \rxdata[0]_i_1 (.I0(rxdata_double[8]), .I1(toggle), .I2(rxdata_double[0]), .O(\rxdata[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT3 #( .INIT(8'hB8)) \rxdata[1]_i_1 (.I0(rxdata_double[9]), .I1(toggle), .I2(rxdata_double[1]), .O(\rxdata[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT3 #( .INIT(8'hB8)) \rxdata[2]_i_1 (.I0(rxdata_double[10]), .I1(toggle), .I2(rxdata_double[2]), .O(\rxdata[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT3 #( .INIT(8'hB8)) \rxdata[3]_i_1 (.I0(rxdata_double[11]), .I1(toggle), .I2(rxdata_double[3]), .O(\rxdata[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT3 #( .INIT(8'hB8)) \rxdata[4]_i_1 (.I0(rxdata_double[12]), .I1(toggle), .I2(rxdata_double[4]), .O(\rxdata[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT3 #( .INIT(8'hB8)) \rxdata[5]_i_1 (.I0(rxdata_double[13]), .I1(toggle), .I2(rxdata_double[5]), .O(\rxdata[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT3 #( .INIT(8'hB8)) \rxdata[6]_i_1 (.I0(rxdata_double[14]), .I1(toggle), .I2(rxdata_double[6]), .O(\rxdata[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT3 #( .INIT(8'hB8)) \rxdata[7]_i_1 (.I0(rxdata_double[15]), .I1(toggle), .I2(rxdata_double[7]), .O(\rxdata[7]_i_1_n_0 )); FDRE \rxdata_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxdata_reg[0]), .Q(rxdata_double[0]), .R(SR)); FDRE \rxdata_double_reg[10] (.C(userclk2), .CE(toggle), .D(rxdata_reg[10]), .Q(rxdata_double[10]), .R(SR)); FDRE \rxdata_double_reg[11] (.C(userclk2), .CE(toggle), .D(rxdata_reg[11]), .Q(rxdata_double[11]), .R(SR)); FDRE \rxdata_double_reg[12] (.C(userclk2), .CE(toggle), .D(rxdata_reg[12]), .Q(rxdata_double[12]), .R(SR)); FDRE \rxdata_double_reg[13] (.C(userclk2), .CE(toggle), .D(rxdata_reg[13]), .Q(rxdata_double[13]), .R(SR)); FDRE \rxdata_double_reg[14] (.C(userclk2), .CE(toggle), .D(rxdata_reg[14]), .Q(rxdata_double[14]), .R(SR)); FDRE \rxdata_double_reg[15] (.C(userclk2), .CE(toggle), .D(rxdata_reg[15]), .Q(rxdata_double[15]), .R(SR)); FDRE \rxdata_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxdata_reg[1]), .Q(rxdata_double[1]), .R(SR)); FDRE \rxdata_double_reg[2] (.C(userclk2), .CE(toggle), .D(rxdata_reg[2]), .Q(rxdata_double[2]), .R(SR)); FDRE \rxdata_double_reg[3] (.C(userclk2), .CE(toggle), .D(rxdata_reg[3]), .Q(rxdata_double[3]), .R(SR)); FDRE \rxdata_double_reg[4] (.C(userclk2), .CE(toggle), .D(rxdata_reg[4]), .Q(rxdata_double[4]), .R(SR)); FDRE \rxdata_double_reg[5] (.C(userclk2), .CE(toggle), .D(rxdata_reg[5]), .Q(rxdata_double[5]), .R(SR)); FDRE \rxdata_double_reg[6] (.C(userclk2), .CE(toggle), .D(rxdata_reg[6]), .Q(rxdata_double[6]), .R(SR)); FDRE \rxdata_double_reg[7] (.C(userclk2), .CE(toggle), .D(rxdata_reg[7]), .Q(rxdata_double[7]), .R(SR)); FDRE \rxdata_double_reg[8] (.C(userclk2), .CE(toggle), .D(rxdata_reg[8]), .Q(rxdata_double[8]), .R(SR)); FDRE \rxdata_double_reg[9] (.C(userclk2), .CE(toggle), .D(rxdata_reg[9]), .Q(rxdata_double[9]), .R(SR)); FDRE \rxdata_reg[0] (.C(userclk2), .CE(1'b1), .D(\rxdata[0]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [0]), .R(SR)); FDRE \rxdata_reg[1] (.C(userclk2), .CE(1'b1), .D(\rxdata[1]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [1]), .R(SR)); FDRE \rxdata_reg[2] (.C(userclk2), .CE(1'b1), .D(\rxdata[2]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [2]), .R(SR)); FDRE \rxdata_reg[3] (.C(userclk2), .CE(1'b1), .D(\rxdata[3]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [3]), .R(SR)); FDRE \rxdata_reg[4] (.C(userclk2), .CE(1'b1), .D(\rxdata[4]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [4]), .R(SR)); FDRE \rxdata_reg[5] (.C(userclk2), .CE(1'b1), .D(\rxdata[5]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [5]), .R(SR)); FDRE \rxdata_reg[6] (.C(userclk2), .CE(1'b1), .D(\rxdata[6]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [6]), .R(SR)); FDRE \rxdata_reg[7] (.C(userclk2), .CE(1'b1), .D(\rxdata[7]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [7]), .R(SR)); FDRE \rxdata_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxdata_int[0]), .Q(rxdata_reg[0]), .R(1'b0)); FDRE \rxdata_reg_reg[10] (.C(userclk), .CE(1'b1), .D(rxdata_int[10]), .Q(rxdata_reg[10]), .R(1'b0)); FDRE \rxdata_reg_reg[11] (.C(userclk), .CE(1'b1), .D(rxdata_int[11]), .Q(rxdata_reg[11]), .R(1'b0)); FDRE \rxdata_reg_reg[12] (.C(userclk), .CE(1'b1), .D(rxdata_int[12]), .Q(rxdata_reg[12]), .R(1'b0)); FDRE \rxdata_reg_reg[13] (.C(userclk), .CE(1'b1), .D(rxdata_int[13]), .Q(rxdata_reg[13]), .R(1'b0)); FDRE \rxdata_reg_reg[14] (.C(userclk), .CE(1'b1), .D(rxdata_int[14]), .Q(rxdata_reg[14]), .R(1'b0)); FDRE \rxdata_reg_reg[15] (.C(userclk), .CE(1'b1), .D(rxdata_int[15]), .Q(rxdata_reg[15]), .R(1'b0)); FDRE \rxdata_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxdata_int[1]), .Q(rxdata_reg[1]), .R(1'b0)); FDRE \rxdata_reg_reg[2] (.C(userclk), .CE(1'b1), .D(rxdata_int[2]), .Q(rxdata_reg[2]), .R(1'b0)); FDRE \rxdata_reg_reg[3] (.C(userclk), .CE(1'b1), .D(rxdata_int[3]), .Q(rxdata_reg[3]), .R(1'b0)); FDRE \rxdata_reg_reg[4] (.C(userclk), .CE(1'b1), .D(rxdata_int[4]), .Q(rxdata_reg[4]), .R(1'b0)); FDRE \rxdata_reg_reg[5] (.C(userclk), .CE(1'b1), .D(rxdata_int[5]), .Q(rxdata_reg[5]), .R(1'b0)); FDRE \rxdata_reg_reg[6] (.C(userclk), .CE(1'b1), .D(rxdata_int[6]), .Q(rxdata_reg[6]), .R(1'b0)); FDRE \rxdata_reg_reg[7] (.C(userclk), .CE(1'b1), .D(rxdata_int[7]), .Q(rxdata_reg[7]), .R(1'b0)); FDRE \rxdata_reg_reg[8] (.C(userclk), .CE(1'b1), .D(rxdata_int[8]), .Q(rxdata_reg[8]), .R(1'b0)); FDRE \rxdata_reg_reg[9] (.C(userclk), .CE(1'b1), .D(rxdata_int[9]), .Q(rxdata_reg[9]), .R(1'b0)); FDRE \rxdisperr_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxdisperr_reg__0[0]), .Q(rxdisperr_double[0]), .R(SR)); FDRE \rxdisperr_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxdisperr_reg__0[1]), .Q(rxdisperr_double[1]), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT3 #( .INIT(8'hB8)) rxdisperr_i_1 (.I0(rxdisperr_double[1]), .I1(toggle), .I2(rxdisperr_double[0]), .O(rxdisperr_i_1_n_0)); FDRE rxdisperr_reg (.C(userclk2), .CE(1'b1), .D(rxdisperr_i_1_n_0), .Q(rxdisperr), .R(SR)); FDRE \rxdisperr_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxctrl1_out[0]), .Q(rxdisperr_reg__0[0]), .R(1'b0)); FDRE \rxdisperr_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxctrl1_out[1]), .Q(rxdisperr_reg__0[1]), .R(1'b0)); FDRE \rxnotintable_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxnotintable_reg__0[0]), .Q(rxnotintable_double[0]), .R(SR)); FDRE \rxnotintable_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxnotintable_reg__0[1]), .Q(rxnotintable_double[1]), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT3 #( .INIT(8'hB8)) rxnotintable_i_1 (.I0(rxnotintable_double[1]), .I1(toggle), .I2(rxnotintable_double[0]), .O(rxnotintable_i_1_n_0)); FDRE rxnotintable_reg (.C(userclk2), .CE(1'b1), .D(rxnotintable_i_1_n_0), .Q(rxnotintable), .R(SR)); FDRE \rxnotintable_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxctrl3_out[0]), .Q(rxnotintable_reg__0[0]), .R(1'b0)); FDRE \rxnotintable_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxctrl3_out[1]), .Q(rxnotintable_reg__0[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) rxpowerdown_double_reg (.C(userclk2), .CE(toggle), .D(rxpowerdown_reg__0), .Q(rxpowerdown_double), .R(SR)); FDRE #( .INIT(1'b0)) rxpowerdown_reg (.C(userclk), .CE(1'b1), .D(rxpowerdown_double), .Q(rxpowerdown), .R(1'b0)); FDRE #( .INIT(1'b0)) rxpowerdown_reg_reg (.C(userclk2), .CE(1'b1), .D(powerdown), .Q(rxpowerdown_reg__0), .R(SR)); LUT1 #( .INIT(2'h1)) toggle_i_1 (.I0(toggle), .O(toggle_i_1_n_0)); FDRE #( .INIT(1'b0)) toggle_reg (.C(userclk2), .CE(1'b1), .D(toggle_i_1_n_0), .Q(toggle), .R(1'b0)); FDRE txbuferr_reg (.C(userclk2), .CE(1'b1), .D(txbufstatus_reg), .Q(txbuferr), .R(1'b0)); FDRE \txbufstatus_reg_reg[1] (.C(userclk), .CE(1'b1), .D(gig_ethernet_pcs_pma_0_gt_i_n_118), .Q(txbufstatus_reg), .R(1'b0)); FDRE \txchardispmode_double_reg[0] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in__1), .Q(txchardispmode_double[0]), .R(txreset)); FDRE \txchardispmode_double_reg[1] (.C(userclk2), .CE(toggle_i_1_n_0), .D(txchardispmode_reg_reg_0), .Q(txchardispmode_double[1]), .R(txreset)); FDRE \txchardispmode_int_reg[0] (.C(userclk), .CE(1'b1), .D(txchardispmode_double[0]), .Q(txchardispmode_int[0]), .R(1'b0)); FDRE \txchardispmode_int_reg[1] (.C(userclk), .CE(1'b1), .D(txchardispmode_double[1]), .Q(txchardispmode_int[1]), .R(1'b0)); FDRE txchardispmode_reg_reg (.C(userclk2), .CE(1'b1), .D(txchardispmode_reg_reg_0), .Q(p_1_in__1), .R(txreset)); FDRE \txchardispval_double_reg[0] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in__0), .Q(txchardispval_double[0]), .R(txreset)); FDRE \txchardispval_double_reg[1] (.C(userclk2), .CE(toggle_i_1_n_0), .D(txchardispval_reg_reg_0), .Q(txchardispval_double[1]), .R(txreset)); FDRE \txchardispval_int_reg[0] (.C(userclk), .CE(1'b1), .D(txchardispval_double[0]), .Q(txchardispval_int[0]), .R(1'b0)); FDRE \txchardispval_int_reg[1] (.C(userclk), .CE(1'b1), .D(txchardispval_double[1]), .Q(txchardispval_int[1]), .R(1'b0)); FDRE txchardispval_reg_reg (.C(userclk2), .CE(1'b1), .D(txchardispval_reg_reg_0), .Q(p_1_in__0), .R(txreset)); FDRE \txcharisk_double_reg[0] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in__2), .Q(txcharisk_double[0]), .R(txreset)); FDRE \txcharisk_double_reg[1] (.C(userclk2), .CE(toggle_i_1_n_0), .D(txcharisk_reg_reg_0), .Q(txcharisk_double[1]), .R(txreset)); FDRE \txcharisk_int_reg[0] (.C(userclk), .CE(1'b1), .D(txcharisk_double[0]), .Q(txcharisk_int[0]), .R(1'b0)); FDRE \txcharisk_int_reg[1] (.C(userclk), .CE(1'b1), .D(txcharisk_double[1]), .Q(txcharisk_int[1]), .R(1'b0)); FDRE txcharisk_reg_reg (.C(userclk2), .CE(1'b1), .D(txcharisk_reg_reg_0), .Q(p_1_in__2), .R(txreset)); FDRE \txdata_double_reg[0] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in[0]), .Q(txdata_double[0]), .R(txreset)); FDRE \txdata_double_reg[10] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D[2]), .Q(txdata_double[10]), .R(txreset)); FDRE \txdata_double_reg[11] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D[3]), .Q(txdata_double[11]), .R(txreset)); FDRE \txdata_double_reg[12] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D[4]), .Q(txdata_double[12]), .R(txreset)); FDRE \txdata_double_reg[13] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D[5]), .Q(txdata_double[13]), .R(txreset)); FDRE \txdata_double_reg[14] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D[6]), .Q(txdata_double[14]), .R(txreset)); FDRE \txdata_double_reg[15] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D[7]), .Q(txdata_double[15]), .R(txreset)); FDRE \txdata_double_reg[1] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in[1]), .Q(txdata_double[1]), .R(txreset)); FDRE \txdata_double_reg[2] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in[2]), .Q(txdata_double[2]), .R(txreset)); FDRE \txdata_double_reg[3] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in[3]), .Q(txdata_double[3]), .R(txreset)); FDRE \txdata_double_reg[4] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in[4]), .Q(txdata_double[4]), .R(txreset)); FDRE \txdata_double_reg[5] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in[5]), .Q(txdata_double[5]), .R(txreset)); FDRE \txdata_double_reg[6] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in[6]), .Q(txdata_double[6]), .R(txreset)); FDRE \txdata_double_reg[7] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in[7]), .Q(txdata_double[7]), .R(txreset)); FDRE \txdata_double_reg[8] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D[0]), .Q(txdata_double[8]), .R(txreset)); FDRE \txdata_double_reg[9] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D[1]), .Q(txdata_double[9]), .R(txreset)); FDRE \txdata_int_reg[0] (.C(userclk), .CE(1'b1), .D(txdata_double[0]), .Q(txdata_int[0]), .R(1'b0)); FDRE \txdata_int_reg[10] (.C(userclk), .CE(1'b1), .D(txdata_double[10]), .Q(txdata_int[10]), .R(1'b0)); FDRE \txdata_int_reg[11] (.C(userclk), .CE(1'b1), .D(txdata_double[11]), .Q(txdata_int[11]), .R(1'b0)); FDRE \txdata_int_reg[12] (.C(userclk), .CE(1'b1), .D(txdata_double[12]), .Q(txdata_int[12]), .R(1'b0)); FDRE \txdata_int_reg[13] (.C(userclk), .CE(1'b1), .D(txdata_double[13]), .Q(txdata_int[13]), .R(1'b0)); FDRE \txdata_int_reg[14] (.C(userclk), .CE(1'b1), .D(txdata_double[14]), .Q(txdata_int[14]), .R(1'b0)); FDRE \txdata_int_reg[15] (.C(userclk), .CE(1'b1), .D(txdata_double[15]), .Q(txdata_int[15]), .R(1'b0)); FDRE \txdata_int_reg[1] (.C(userclk), .CE(1'b1), .D(txdata_double[1]), .Q(txdata_int[1]), .R(1'b0)); FDRE \txdata_int_reg[2] (.C(userclk), .CE(1'b1), .D(txdata_double[2]), .Q(txdata_int[2]), .R(1'b0)); FDRE \txdata_int_reg[3] (.C(userclk), .CE(1'b1), .D(txdata_double[3]), .Q(txdata_int[3]), .R(1'b0)); FDRE \txdata_int_reg[4] (.C(userclk), .CE(1'b1), .D(txdata_double[4]), .Q(txdata_int[4]), .R(1'b0)); FDRE \txdata_int_reg[5] (.C(userclk), .CE(1'b1), .D(txdata_double[5]), .Q(txdata_int[5]), .R(1'b0)); FDRE \txdata_int_reg[6] (.C(userclk), .CE(1'b1), .D(txdata_double[6]), .Q(txdata_int[6]), .R(1'b0)); FDRE \txdata_int_reg[7] (.C(userclk), .CE(1'b1), .D(txdata_double[7]), .Q(txdata_int[7]), .R(1'b0)); FDRE \txdata_int_reg[8] (.C(userclk), .CE(1'b1), .D(txdata_double[8]), .Q(txdata_int[8]), .R(1'b0)); FDRE \txdata_int_reg[9] (.C(userclk), .CE(1'b1), .D(txdata_double[9]), .Q(txdata_int[9]), .R(1'b0)); FDRE \txdata_reg_reg[0] (.C(userclk2), .CE(1'b1), .D(D[0]), .Q(p_1_in[0]), .R(txreset)); FDRE \txdata_reg_reg[1] (.C(userclk2), .CE(1'b1), .D(D[1]), .Q(p_1_in[1]), .R(txreset)); FDRE \txdata_reg_reg[2] (.C(userclk2), .CE(1'b1), .D(D[2]), .Q(p_1_in[2]), .R(txreset)); FDRE \txdata_reg_reg[3] (.C(userclk2), .CE(1'b1), .D(D[3]), .Q(p_1_in[3]), .R(txreset)); FDRE \txdata_reg_reg[4] (.C(userclk2), .CE(1'b1), .D(D[4]), .Q(p_1_in[4]), .R(txreset)); FDRE \txdata_reg_reg[5] (.C(userclk2), .CE(1'b1), .D(D[5]), .Q(p_1_in[5]), .R(txreset)); FDRE \txdata_reg_reg[6] (.C(userclk2), .CE(1'b1), .D(D[6]), .Q(p_1_in[6]), .R(txreset)); FDRE \txdata_reg_reg[7] (.C(userclk2), .CE(1'b1), .D(D[7]), .Q(p_1_in[7]), .R(txreset)); FDRE #( .INIT(1'b0)) txpowerdown_double_reg (.C(userclk2), .CE(1'b1), .D(txpowerdown_reg__0), .Q(txpowerdown_double), .R(txreset)); FDRE #( .INIT(1'b0)) txpowerdown_reg (.C(userclk), .CE(1'b1), .D(txpowerdown_double), .Q(txpowerdown), .R(1'b0)); FDRE #( .INIT(1'b0)) txpowerdown_reg_reg (.C(userclk2), .CE(1'b1), .D(powerdown), .Q(txpowerdown_reg__0), .R(txreset)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync , rxresetdone_out, drpclk_in); output \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; input [0:0]rxresetdone_out; input [0:0]drpclk_in; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire [0:0]rxresetdone_out; (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(rxresetdone_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_10 (gtwiz_reset_userclk_tx_active_sync, \FSM_sequential_sm_reset_tx_reg[2] , i_in_out_reg_0, gtwiz_userclk_tx_active_in, drpclk_in, Q, sm_reset_tx_timer_clr_reg, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync , sm_reset_tx_timer_clr_reg_0, plllock_tx_sync, \FSM_sequential_sm_reset_tx_reg[0] , \FSM_sequential_sm_reset_tx_reg[0]_0 , \FSM_sequential_sm_reset_tx_reg[0]_1 , sm_reset_tx_pll_timer_sat); output gtwiz_reset_userclk_tx_active_sync; output \FSM_sequential_sm_reset_tx_reg[2] ; output i_in_out_reg_0; input [0:0]gtwiz_userclk_tx_active_in; input [0:0]drpclk_in; input [2:0]Q; input sm_reset_tx_timer_clr_reg; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; input sm_reset_tx_timer_clr_reg_0; input plllock_tx_sync; input \FSM_sequential_sm_reset_tx_reg[0] ; input \FSM_sequential_sm_reset_tx_reg[0]_0 ; input \FSM_sequential_sm_reset_tx_reg[0]_1 ; input sm_reset_tx_pll_timer_sat; wire \FSM_sequential_sm_reset_tx_reg[0] ; wire \FSM_sequential_sm_reset_tx_reg[0]_0 ; wire \FSM_sequential_sm_reset_tx_reg[0]_1 ; wire \FSM_sequential_sm_reset_tx_reg[2] ; wire [2:0]Q; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; wire gtwiz_reset_userclk_tx_active_sync; wire [0:0]gtwiz_userclk_tx_active_in; (* async_reg = "true" *) wire i_in_meta; wire i_in_out_reg_0; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire plllock_tx_sync; wire sm_reset_tx_pll_timer_sat; wire sm_reset_tx_timer_clr_i_2_n_0; wire sm_reset_tx_timer_clr_reg; wire sm_reset_tx_timer_clr_reg_0; LUT6 #( .INIT(64'h000F000088888888)) \FSM_sequential_sm_reset_tx[2]_i_5 (.I0(\FSM_sequential_sm_reset_tx_reg[0] ), .I1(gtwiz_reset_userclk_tx_active_sync), .I2(\FSM_sequential_sm_reset_tx_reg[0]_0 ), .I3(\FSM_sequential_sm_reset_tx_reg[0]_1 ), .I4(sm_reset_tx_pll_timer_sat), .I5(Q[0]), .O(i_in_out_reg_0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(gtwiz_userclk_tx_active_in), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_userclk_tx_active_sync), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); LUT5 #( .INIT(32'hEBEB282B)) sm_reset_tx_timer_clr_i_1 (.I0(sm_reset_tx_timer_clr_i_2_n_0), .I1(Q[2]), .I2(Q[1]), .I3(Q[0]), .I4(sm_reset_tx_timer_clr_reg), .O(\FSM_sequential_sm_reset_tx_reg[2] )); LUT6 #( .INIT(64'hA0C0A0C0F0F000F0)) sm_reset_tx_timer_clr_i_2 (.I0(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .I1(gtwiz_reset_userclk_tx_active_sync), .I2(sm_reset_tx_timer_clr_reg_0), .I3(Q[0]), .I4(plllock_tx_sync), .I5(Q[2]), .O(sm_reset_tx_timer_clr_i_2_n_0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_11 (plllock_rx_sync, i_in_out_reg_0, \FSM_sequential_sm_reset_rx_reg[1] , cplllock_out, drpclk_in, gtwiz_reset_rx_done_int_reg, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync , Q, gtwiz_reset_rx_done_int_reg_0); output plllock_rx_sync; output i_in_out_reg_0; output \FSM_sequential_sm_reset_rx_reg[1] ; input [0:0]cplllock_out; input [0:0]drpclk_in; input gtwiz_reset_rx_done_int_reg; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; input [2:0]Q; input gtwiz_reset_rx_done_int_reg_0; wire \FSM_sequential_sm_reset_rx_reg[1] ; wire [2:0]Q; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; wire gtwiz_reset_rx_done_int; wire gtwiz_reset_rx_done_int_reg; wire gtwiz_reset_rx_done_int_reg_0; (* async_reg = "true" *) wire i_in_meta; wire i_in_out_reg_0; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire plllock_rx_sync; LUT6 #( .INIT(64'hAAC0FFFFAAC00000)) gtwiz_reset_rx_done_int_i_1 (.I0(plllock_rx_sync), .I1(gtwiz_reset_rx_done_int_reg), .I2(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I3(Q[0]), .I4(gtwiz_reset_rx_done_int), .I5(gtwiz_reset_rx_done_int_reg_0), .O(i_in_out_reg_0)); LUT6 #( .INIT(64'h4C40000040400000)) gtwiz_reset_rx_done_int_i_2 (.I0(plllock_rx_sync), .I1(Q[2]), .I2(Q[0]), .I3(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I4(Q[1]), .I5(gtwiz_reset_rx_done_int_reg), .O(gtwiz_reset_rx_done_int)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(cplllock_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(plllock_rx_sync), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); LUT6 #( .INIT(64'h88880000F5FF5555)) sm_reset_rx_timer_clr_i_3 (.I0(Q[1]), .I1(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I2(plllock_rx_sync), .I3(Q[0]), .I4(gtwiz_reset_rx_done_int_reg), .I5(Q[2]), .O(\FSM_sequential_sm_reset_rx_reg[1] )); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_12 (plllock_tx_sync, gtwiz_reset_tx_done_int_reg, i_in_out_reg_0, cplllock_out, drpclk_in, gtwiz_reset_tx_done_int_reg_0, Q, sm_reset_tx_timer_sat, gtwiz_reset_tx_done_int_reg_1, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync , \FSM_sequential_sm_reset_tx_reg[0] ); output plllock_tx_sync; output gtwiz_reset_tx_done_int_reg; output i_in_out_reg_0; input [0:0]cplllock_out; input [0:0]drpclk_in; input gtwiz_reset_tx_done_int_reg_0; input [2:0]Q; input sm_reset_tx_timer_sat; input gtwiz_reset_tx_done_int_reg_1; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; input \FSM_sequential_sm_reset_tx_reg[0] ; wire \FSM_sequential_sm_reset_tx_reg[0] ; wire [2:0]Q; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; wire gtwiz_reset_tx_done_int; wire gtwiz_reset_tx_done_int_i_2_n_0; wire gtwiz_reset_tx_done_int_reg; wire gtwiz_reset_tx_done_int_reg_0; wire gtwiz_reset_tx_done_int_reg_1; (* async_reg = "true" *) wire i_in_meta; wire i_in_out_reg_0; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire plllock_tx_sync; wire sm_reset_tx_timer_sat; LUT6 #( .INIT(64'h00CFA00000000000)) \FSM_sequential_sm_reset_tx[2]_i_4 (.I0(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .I1(plllock_tx_sync), .I2(Q[0]), .I3(Q[2]), .I4(Q[1]), .I5(\FSM_sequential_sm_reset_tx_reg[0] ), .O(i_in_out_reg_0)); LUT3 #( .INIT(8'hB8)) gtwiz_reset_tx_done_int_i_1 (.I0(gtwiz_reset_tx_done_int_i_2_n_0), .I1(gtwiz_reset_tx_done_int), .I2(gtwiz_reset_tx_done_int_reg_0), .O(gtwiz_reset_tx_done_int_reg)); LUT6 #( .INIT(64'h4444444444F44444)) gtwiz_reset_tx_done_int_i_2 (.I0(Q[0]), .I1(plllock_tx_sync), .I2(sm_reset_tx_timer_sat), .I3(gtwiz_reset_tx_done_int_reg_1), .I4(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .I5(Q[1]), .O(gtwiz_reset_tx_done_int_i_2_n_0)); LUT6 #( .INIT(64'h3000404000004040)) gtwiz_reset_tx_done_int_i_3 (.I0(plllock_tx_sync), .I1(Q[1]), .I2(Q[2]), .I3(\FSM_sequential_sm_reset_tx_reg[0] ), .I4(Q[0]), .I5(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .O(gtwiz_reset_tx_done_int)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(cplllock_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(plllock_tx_sync), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_13 (\FSM_sequential_sm_reset_rx_reg[2] , \FSM_sequential_sm_reset_rx_reg[1] , sm_reset_rx_cdr_to_sat_reg, rxcdrlock_out, drpclk_in, sm_reset_rx_cdr_to_clr_reg, Q, plllock_rx_sync, sm_reset_rx_cdr_to_clr, \FSM_sequential_sm_reset_rx_reg[0] , sm_reset_rx_cdr_to_sat); output \FSM_sequential_sm_reset_rx_reg[2] ; output \FSM_sequential_sm_reset_rx_reg[1] ; output sm_reset_rx_cdr_to_sat_reg; input [0:0]rxcdrlock_out; input [0:0]drpclk_in; input sm_reset_rx_cdr_to_clr_reg; input [2:0]Q; input plllock_rx_sync; input sm_reset_rx_cdr_to_clr; input \FSM_sequential_sm_reset_rx_reg[0] ; input sm_reset_rx_cdr_to_sat; wire \FSM_sequential_sm_reset_rx_reg[0] ; wire \FSM_sequential_sm_reset_rx_reg[1] ; wire \FSM_sequential_sm_reset_rx_reg[2] ; wire [2:0]Q; wire [0:0]drpclk_in; (* async_reg = "true" *) wire i_in_meta; wire i_in_out_reg_n_0; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire plllock_rx_sync; wire [0:0]rxcdrlock_out; wire sm_reset_rx_cdr_to_clr; wire sm_reset_rx_cdr_to_clr_i_2_n_0; wire sm_reset_rx_cdr_to_clr_reg; wire sm_reset_rx_cdr_to_sat; wire sm_reset_rx_cdr_to_sat_reg; LUT6 #( .INIT(64'h000A000AC0C000C0)) \FSM_sequential_sm_reset_rx[2]_i_4 (.I0(sm_reset_rx_cdr_to_sat_reg), .I1(\FSM_sequential_sm_reset_rx_reg[0] ), .I2(Q[1]), .I3(Q[0]), .I4(plllock_rx_sync), .I5(Q[2]), .O(\FSM_sequential_sm_reset_rx_reg[1] )); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(rxcdrlock_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(i_in_out_reg_n_0), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT2 #( .INIT(4'hE)) rxprogdivreset_out_i_2 (.I0(sm_reset_rx_cdr_to_sat), .I1(i_in_out_reg_n_0), .O(sm_reset_rx_cdr_to_sat_reg)); LUT6 #( .INIT(64'hFBFFFFFF0800AAAA)) sm_reset_rx_cdr_to_clr_i_1 (.I0(sm_reset_rx_cdr_to_clr_i_2_n_0), .I1(sm_reset_rx_cdr_to_clr_reg), .I2(Q[2]), .I3(plllock_rx_sync), .I4(Q[0]), .I5(sm_reset_rx_cdr_to_clr), .O(\FSM_sequential_sm_reset_rx_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT4 #( .INIT(16'h00EF)) sm_reset_rx_cdr_to_clr_i_2 (.I0(sm_reset_rx_cdr_to_sat), .I1(i_in_out_reg_n_0), .I2(Q[2]), .I3(Q[1]), .O(sm_reset_rx_cdr_to_clr_i_2_n_0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_3 (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync , txresetdone_out, drpclk_in); output \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; input [0:0]txresetdone_out; input [0:0]drpclk_in; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire [0:0]txresetdone_out; (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(txresetdone_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_4 (E, gtpowergood_out, drpclk_in, \FSM_sequential_sm_reset_all_reg[0] , Q, \FSM_sequential_sm_reset_all_reg[0]_0 ); output [0:0]E; input [0:0]gtpowergood_out; input [0:0]drpclk_in; input \FSM_sequential_sm_reset_all_reg[0] ; input [2:0]Q; input \FSM_sequential_sm_reset_all_reg[0]_0 ; wire [0:0]E; wire \FSM_sequential_sm_reset_all_reg[0] ; wire \FSM_sequential_sm_reset_all_reg[0]_0 ; wire [2:0]Q; wire [0:0]drpclk_in; wire [0:0]gtpowergood_out; wire gtpowergood_sync; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; LUT6 #( .INIT(64'hAF0FAF00CFFFCFFF)) \FSM_sequential_sm_reset_all[2]_i_1 (.I0(gtpowergood_sync), .I1(\FSM_sequential_sm_reset_all_reg[0] ), .I2(Q[2]), .I3(Q[0]), .I4(\FSM_sequential_sm_reset_all_reg[0]_0 ), .I5(Q[1]), .O(E)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(gtpowergood_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtpowergood_sync), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_5 (gtwiz_reset_rx_datapath_dly, in0, drpclk_in); output gtwiz_reset_rx_datapath_dly; input in0; input [0:0]drpclk_in; wire [0:0]drpclk_in; wire gtwiz_reset_rx_datapath_dly; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire in0; (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(in0), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_rx_datapath_dly), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_6 (D, i_in_out_reg_0, in0, drpclk_in, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync , \FSM_sequential_sm_reset_rx_reg[0] , Q, gtwiz_reset_rx_datapath_dly, \FSM_sequential_sm_reset_rx_reg[0]_0 ); output [1:0]D; output i_in_out_reg_0; input in0; input [0:0]drpclk_in; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; input \FSM_sequential_sm_reset_rx_reg[0] ; input [2:0]Q; input gtwiz_reset_rx_datapath_dly; input \FSM_sequential_sm_reset_rx_reg[0]_0 ; wire [1:0]D; wire \FSM_sequential_sm_reset_rx_reg[0] ; wire \FSM_sequential_sm_reset_rx_reg[0]_0 ; wire [2:0]Q; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; wire gtwiz_reset_rx_datapath_dly; wire gtwiz_reset_rx_pll_and_datapath_dly; (* async_reg = "true" *) wire i_in_meta; wire i_in_out_reg_0; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire in0; LUT6 #( .INIT(64'hFF0088FF00FFFFF0)) \FSM_sequential_sm_reset_rx[0]_i_1 (.I0(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I1(\FSM_sequential_sm_reset_rx_reg[0] ), .I2(gtwiz_reset_rx_pll_and_datapath_dly), .I3(Q[2]), .I4(Q[0]), .I5(Q[1]), .O(D[0])); LUT6 #( .INIT(64'h0000FFFF8F8F000F)) \FSM_sequential_sm_reset_rx[1]_i_1 (.I0(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I1(\FSM_sequential_sm_reset_rx_reg[0] ), .I2(Q[2]), .I3(gtwiz_reset_rx_pll_and_datapath_dly), .I4(Q[1]), .I5(Q[0]), .O(D[1])); LUT6 #( .INIT(64'hFFFFFFFF0000000E)) \FSM_sequential_sm_reset_rx[2]_i_5 (.I0(gtwiz_reset_rx_pll_and_datapath_dly), .I1(gtwiz_reset_rx_datapath_dly), .I2(Q[2]), .I3(Q[1]), .I4(Q[0]), .I5(\FSM_sequential_sm_reset_rx_reg[0]_0 ), .O(i_in_out_reg_0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(in0), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_rx_pll_and_datapath_dly), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_7 (E, in0, drpclk_in, Q, \FSM_sequential_sm_reset_tx_reg[0] , gtwiz_reset_tx_pll_and_datapath_dly, \FSM_sequential_sm_reset_tx_reg[0]_0 , \FSM_sequential_sm_reset_tx_reg[0]_1 ); output [0:0]E; input in0; input [0:0]drpclk_in; input [0:0]Q; input \FSM_sequential_sm_reset_tx_reg[0] ; input gtwiz_reset_tx_pll_and_datapath_dly; input \FSM_sequential_sm_reset_tx_reg[0]_0 ; input \FSM_sequential_sm_reset_tx_reg[0]_1 ; wire [0:0]E; wire \FSM_sequential_sm_reset_tx_reg[0] ; wire \FSM_sequential_sm_reset_tx_reg[0]_0 ; wire \FSM_sequential_sm_reset_tx_reg[0]_1 ; wire [0:0]Q; wire [0:0]drpclk_in; wire gtwiz_reset_tx_datapath_dly; wire gtwiz_reset_tx_pll_and_datapath_dly; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire in0; LUT6 #( .INIT(64'hFFFFFFFFFFFF1110)) \FSM_sequential_sm_reset_tx[2]_i_1 (.I0(Q), .I1(\FSM_sequential_sm_reset_tx_reg[0] ), .I2(gtwiz_reset_tx_datapath_dly), .I3(gtwiz_reset_tx_pll_and_datapath_dly), .I4(\FSM_sequential_sm_reset_tx_reg[0]_0 ), .I5(\FSM_sequential_sm_reset_tx_reg[0]_1 ), .O(E)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(in0), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_tx_datapath_dly), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_8 (gtwiz_reset_tx_pll_and_datapath_dly, D, in0, drpclk_in, Q); output gtwiz_reset_tx_pll_and_datapath_dly; output [1:0]D; input in0; input [0:0]drpclk_in; input [2:0]Q; wire [1:0]D; wire [2:0]Q; wire [0:0]drpclk_in; wire gtwiz_reset_tx_pll_and_datapath_dly; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire in0; (* SOFT_HLUTNM = "soft_lutpair38" *) LUT4 #( .INIT(16'h1F1E)) \FSM_sequential_sm_reset_tx[0]_i_1 (.I0(Q[1]), .I1(Q[2]), .I2(Q[0]), .I3(gtwiz_reset_tx_pll_and_datapath_dly), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT4 #( .INIT(16'h0FF1)) \FSM_sequential_sm_reset_tx[1]_i_1 (.I0(Q[2]), .I1(gtwiz_reset_tx_pll_and_datapath_dly), .I2(Q[1]), .I3(Q[0]), .O(D[1])); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(in0), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_tx_pll_and_datapath_dly), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_9 (\FSM_sequential_sm_reset_rx_reg[0] , \FSM_sequential_sm_reset_rx_reg[2] , E, rxpmaresetdone_out, drpclk_in, sm_reset_rx_timer_clr_reg, Q, sm_reset_rx_timer_clr_reg_0, gtwiz_reset_rx_any_sync, \gen_gtwizard_gthe3.rxuserrdy_int , \FSM_sequential_sm_reset_rx_reg[0]_0 , \FSM_sequential_sm_reset_rx_reg[0]_1 , \FSM_sequential_sm_reset_rx_reg[0]_2 , sm_reset_rx_pll_timer_sat, sm_reset_rx_timer_sat); output \FSM_sequential_sm_reset_rx_reg[0] ; output \FSM_sequential_sm_reset_rx_reg[2] ; output [0:0]E; input [0:0]rxpmaresetdone_out; input [0:0]drpclk_in; input sm_reset_rx_timer_clr_reg; input [2:0]Q; input sm_reset_rx_timer_clr_reg_0; input gtwiz_reset_rx_any_sync; input \gen_gtwizard_gthe3.rxuserrdy_int ; input \FSM_sequential_sm_reset_rx_reg[0]_0 ; input \FSM_sequential_sm_reset_rx_reg[0]_1 ; input \FSM_sequential_sm_reset_rx_reg[0]_2 ; input sm_reset_rx_pll_timer_sat; input sm_reset_rx_timer_sat; wire [0:0]E; wire \FSM_sequential_sm_reset_rx[2]_i_3_n_0 ; wire \FSM_sequential_sm_reset_rx_reg[0] ; wire \FSM_sequential_sm_reset_rx_reg[0]_0 ; wire \FSM_sequential_sm_reset_rx_reg[0]_1 ; wire \FSM_sequential_sm_reset_rx_reg[0]_2 ; wire \FSM_sequential_sm_reset_rx_reg[2] ; wire [2:0]Q; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.rxuserrdy_int ; wire gtwiz_reset_rx_any_sync; wire gtwiz_reset_userclk_rx_active_sync; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire [0:0]rxpmaresetdone_out; wire sm_reset_rx_pll_timer_sat; wire sm_reset_rx_timer_clr_i_2_n_0; wire sm_reset_rx_timer_clr_reg; wire sm_reset_rx_timer_clr_reg_0; wire sm_reset_rx_timer_sat; LUT3 #( .INIT(8'hFE)) \FSM_sequential_sm_reset_rx[2]_i_1 (.I0(\FSM_sequential_sm_reset_rx[2]_i_3_n_0 ), .I1(\FSM_sequential_sm_reset_rx_reg[0]_0 ), .I2(\FSM_sequential_sm_reset_rx_reg[0]_1 ), .O(E)); LUT6 #( .INIT(64'h2023202000000000)) \FSM_sequential_sm_reset_rx[2]_i_3 (.I0(sm_reset_rx_timer_clr_i_2_n_0), .I1(Q[1]), .I2(Q[2]), .I3(\FSM_sequential_sm_reset_rx_reg[0]_2 ), .I4(sm_reset_rx_pll_timer_sat), .I5(Q[0]), .O(\FSM_sequential_sm_reset_rx[2]_i_3_n_0 )); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(rxpmaresetdone_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_userclk_rx_active_sync), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFAAF00000800)) rxuserrdy_out_i_1 (.I0(Q[2]), .I1(sm_reset_rx_timer_clr_i_2_n_0), .I2(Q[1]), .I3(Q[0]), .I4(gtwiz_reset_rx_any_sync), .I5(\gen_gtwizard_gthe3.rxuserrdy_int ), .O(\FSM_sequential_sm_reset_rx_reg[2] )); LUT6 #( .INIT(64'hFCCCEFFE0CCCE00E)) sm_reset_rx_timer_clr_i_1 (.I0(sm_reset_rx_timer_clr_i_2_n_0), .I1(sm_reset_rx_timer_clr_reg), .I2(Q[0]), .I3(Q[2]), .I4(Q[1]), .I5(sm_reset_rx_timer_clr_reg_0), .O(\FSM_sequential_sm_reset_rx_reg[0] )); LUT3 #( .INIT(8'h40)) sm_reset_rx_timer_clr_i_2 (.I0(sm_reset_rx_timer_clr_reg_0), .I1(sm_reset_rx_timer_sat), .I2(gtwiz_reset_userclk_rx_active_sync), .O(sm_reset_rx_timer_clr_i_2_n_0)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_gthe3_channel (cplllock_out, gthtxn_out, gthtxp_out, gtpowergood_out, rxcdrlock_out, rxoutclk_out, rxpmaresetdone_out, rxresetdone_out, txoutclk_out, txresetdone_out, gtwiz_userdata_rx_out, rxctrl0_out, rxctrl1_out, rxclkcorcnt_out, txbufstatus_out, rxbufstatus_out, rxctrl2_out, rxctrl3_out, rst_in0, \gen_gtwizard_gthe3.cpllpd_ch_int , drpclk_in, gthrxn_in, gthrxp_in, gtrefclk0_in, \gen_gtwizard_gthe3.gtrxreset_int , \gen_gtwizard_gthe3.gttxreset_int , rxmcommaalignen_in, \gen_gtwizard_gthe3.rxprogdivreset_int , \gen_gtwizard_gthe3.rxuserrdy_int , rxusrclk_in, txelecidle_in, \gen_gtwizard_gthe3.txprogdivreset_int , \gen_gtwizard_gthe3.txuserrdy_int , gtwiz_userdata_tx_in, txctrl0_in, txctrl1_in, rxpd_in, txctrl2_in); output [0:0]cplllock_out; output [0:0]gthtxn_out; output [0:0]gthtxp_out; output [0:0]gtpowergood_out; output [0:0]rxcdrlock_out; output [0:0]rxoutclk_out; output [0:0]rxpmaresetdone_out; output [0:0]rxresetdone_out; output [0:0]txoutclk_out; output [0:0]txresetdone_out; output [15:0]gtwiz_userdata_rx_out; output [1:0]rxctrl0_out; output [1:0]rxctrl1_out; output [1:0]rxclkcorcnt_out; output [0:0]txbufstatus_out; output [0:0]rxbufstatus_out; output [1:0]rxctrl2_out; output [1:0]rxctrl3_out; output rst_in0; input \gen_gtwizard_gthe3.cpllpd_ch_int ; input [0:0]drpclk_in; input [0:0]gthrxn_in; input [0:0]gthrxp_in; input [0:0]gtrefclk0_in; input \gen_gtwizard_gthe3.gtrxreset_int ; input \gen_gtwizard_gthe3.gttxreset_int ; input [0:0]rxmcommaalignen_in; input \gen_gtwizard_gthe3.rxprogdivreset_int ; input \gen_gtwizard_gthe3.rxuserrdy_int ; input [0:0]rxusrclk_in; input [0:0]txelecidle_in; input \gen_gtwizard_gthe3.txprogdivreset_int ; input \gen_gtwizard_gthe3.txuserrdy_int ; input [15:0]gtwiz_userdata_tx_in; input [1:0]txctrl0_in; input [1:0]txctrl1_in; input [0:0]rxpd_in; input [1:0]txctrl2_in; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.cpllpd_ch_int ; wire \gen_gtwizard_gthe3.gtrxreset_int ; wire \gen_gtwizard_gthe3.gttxreset_int ; wire \gen_gtwizard_gthe3.rxprogdivreset_int ; wire \gen_gtwizard_gthe3.rxuserrdy_int ; wire \gen_gtwizard_gthe3.txprogdivreset_int ; wire \gen_gtwizard_gthe3.txuserrdy_int ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_0 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_10 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_100 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_101 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_102 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_103 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_104 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_105 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_106 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_107 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_108 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_109 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_11 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_110 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_111 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_112 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_113 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_114 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_115 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_116 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_117 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_118 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_119 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_12 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_120 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_121 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_122 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_123 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_124 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_125 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_126 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_127 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_128 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_129 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_13 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_130 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_131 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_132 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_133 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_134 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_135 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_136 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_137 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_138 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_139 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_14 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_140 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_141 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_142 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_143 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_144 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_145 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_146 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_147 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_148 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_149 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_15 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_150 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_151 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_152 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_153 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_154 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_155 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_156 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_157 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_158 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_159 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_16 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_160 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_161 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_162 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_163 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_164 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_165 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_166 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_167 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_168 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_169 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_17 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_170 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_171 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_172 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_173 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_174 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_175 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_176 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_177 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_178 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_179 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_18 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_180 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_181 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_182 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_183 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_184 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_185 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_186 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_187 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_188 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_189 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_190 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_191 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_192 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_193 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_2 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_20 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_21 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_210 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_211 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_212 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_213 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_214 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_215 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_216 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_217 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_218 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_219 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_22 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_220 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_221 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_222 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_223 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_224 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_225 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_226 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_227 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_228 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_229 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_23 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_230 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_231 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_232 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_233 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_234 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_235 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_236 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_237 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_238 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_239 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_24 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_242 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_243 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_244 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_245 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_246 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_247 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_248 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_249 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_25 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_250 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_251 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_252 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_253 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_254 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_255 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_258 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_259 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_26 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_260 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_261 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_262 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_263 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_264 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_265 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_266 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_267 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_268 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_269 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_27 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_270 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_271 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_272 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_273 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_274 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_275 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_276 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_277 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_278 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_28 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_281 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_282 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_283 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_284 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_285 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_286 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_288 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_289 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_29 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_290 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_291 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_292 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_293 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_294 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_295 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_296 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_297 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_298 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_299 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_3 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_30 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_300 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_302 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_303 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_304 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_305 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_306 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_307 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_308 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_309 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_31 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_310 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_311 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_312 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_313 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_314 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_315 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_316 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_317 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_318 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_319 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_32 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_320 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_321 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_322 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_323 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_324 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_325 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_326 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_327 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_328 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_329 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_33 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_330 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_331 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_332 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_333 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_334 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_335 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_336 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_337 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_338 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_341 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_342 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_343 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_344 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_345 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_346 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_349 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_35 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_350 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_351 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_352 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_353 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_354 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_355 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_356 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_357 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_358 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_359 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_36 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_360 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_361 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_362 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_363 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_364 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_365 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_37 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_38 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_4 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_40 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_41 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_42 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_43 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_44 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_45 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_46 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_48 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_49 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_50 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_51 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_52 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_53 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_54 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_55 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_56 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_58 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_59 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_60 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_61 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_62 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_63 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_64 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_65 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_66 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_68 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_70 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_71 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_72 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_73 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_74 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_75 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_76 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_77 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_78 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_79 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_8 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_80 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_81 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_82 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_83 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_84 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_85 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_86 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_87 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_88 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_89 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_9 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_90 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_91 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_92 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_93 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_94 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_95 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_96 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_97 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_98 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_99 ; wire [0:0]gthrxn_in; wire [0:0]gthrxp_in; wire [0:0]gthtxn_out; wire [0:0]gthtxp_out; wire [0:0]gtpowergood_out; wire [0:0]gtrefclk0_in; wire [15:0]gtwiz_userdata_rx_out; wire [15:0]gtwiz_userdata_tx_in; wire rst_in0; wire [0:0]rxbufstatus_out; wire [0:0]rxcdrlock_out; wire [1:0]rxclkcorcnt_out; wire [1:0]rxctrl0_out; wire [1:0]rxctrl1_out; wire [1:0]rxctrl2_out; wire [1:0]rxctrl3_out; wire [0:0]rxmcommaalignen_in; wire [0:0]rxoutclk_out; wire [0:0]rxpd_in; wire [0:0]rxpmaresetdone_out; wire [0:0]rxresetdone_out; wire [0:0]rxusrclk_in; wire [0:0]txbufstatus_out; wire [1:0]txctrl0_in; wire [1:0]txctrl1_in; wire [1:0]txctrl2_in; wire [0:0]txelecidle_in; wire [0:0]txoutclk_out; wire [0:0]txresetdone_out; (* box_type = "PRIMITIVE" *) GTHE3_CHANNEL #( .ACJTAG_DEBUG_MODE(1'b0), .ACJTAG_MODE(1'b0), .ACJTAG_RESET(1'b0), .ADAPT_CFG0(16'hF800), .ADAPT_CFG1(16'h0000), .ALIGN_COMMA_DOUBLE("FALSE"), .ALIGN_COMMA_ENABLE(10'b1111111111), .ALIGN_COMMA_WORD(2), .ALIGN_MCOMMA_DET("TRUE"), .ALIGN_MCOMMA_VALUE(10'b1010000011), .ALIGN_PCOMMA_DET("TRUE"), .ALIGN_PCOMMA_VALUE(10'b0101111100), .A_RXOSCALRESET(1'b0), .A_RXPROGDIVRESET(1'b0), .A_TXPROGDIVRESET(1'b0), .CBCC_DATA_SOURCE_SEL("DECODED"), .CDR_SWAP_MODE_EN(1'b0), .CHAN_BOND_KEEP_ALIGN("FALSE"), .CHAN_BOND_MAX_SKEW(1), .CHAN_BOND_SEQ_1_1(10'b0000000000), .CHAN_BOND_SEQ_1_2(10'b0000000000), .CHAN_BOND_SEQ_1_3(10'b0000000000), .CHAN_BOND_SEQ_1_4(10'b0000000000), .CHAN_BOND_SEQ_1_ENABLE(4'b1111), .CHAN_BOND_SEQ_2_1(10'b0000000000), .CHAN_BOND_SEQ_2_2(10'b0000000000), .CHAN_BOND_SEQ_2_3(10'b0000000000), .CHAN_BOND_SEQ_2_4(10'b0000000000), .CHAN_BOND_SEQ_2_ENABLE(4'b1111), .CHAN_BOND_SEQ_2_USE("FALSE"), .CHAN_BOND_SEQ_LEN(1), .CLK_CORRECT_USE("TRUE"), .CLK_COR_KEEP_IDLE("FALSE"), .CLK_COR_MAX_LAT(15), .CLK_COR_MIN_LAT(12), .CLK_COR_PRECEDENCE("TRUE"), .CLK_COR_REPEAT_WAIT(0), .CLK_COR_SEQ_1_1(10'b0110111100), .CLK_COR_SEQ_1_2(10'b0001010000), .CLK_COR_SEQ_1_3(10'b0000000000), .CLK_COR_SEQ_1_4(10'b0000000000), .CLK_COR_SEQ_1_ENABLE(4'b1111), .CLK_COR_SEQ_2_1(10'b0110111100), .CLK_COR_SEQ_2_2(10'b0010110101), .CLK_COR_SEQ_2_3(10'b0000000000), .CLK_COR_SEQ_2_4(10'b0000000000), .CLK_COR_SEQ_2_ENABLE(4'b1111), .CLK_COR_SEQ_2_USE("TRUE"), .CLK_COR_SEQ_LEN(2), .CPLL_CFG0(16'h67F8), .CPLL_CFG1(16'hA4AC), .CPLL_CFG2(16'h0007), .CPLL_CFG3(6'h00), .CPLL_FBDIV(5), .CPLL_FBDIV_45(4), .CPLL_INIT_CFG0(16'h02B2), .CPLL_INIT_CFG1(8'h00), .CPLL_LOCK_CFG(16'h01E8), .CPLL_REFCLK_DIV(1), .DDI_CTRL(2'b00), .DDI_REALIGN_WAIT(15), .DEC_MCOMMA_DETECT("TRUE"), .DEC_PCOMMA_DETECT("TRUE"), .DEC_VALID_COMMA_ONLY("FALSE"), .DFE_D_X_REL_POS(1'b0), .DFE_VCM_COMP_EN(1'b0), .DMONITOR_CFG0(10'h000), .DMONITOR_CFG1(8'h00), .ES_CLK_PHASE_SEL(1'b0), .ES_CONTROL(6'b000000), .ES_ERRDET_EN("FALSE"), .ES_EYE_SCAN_EN("FALSE"), .ES_HORZ_OFFSET(12'h000), .ES_PMA_CFG(10'b0000000000), .ES_PRESCALE(5'b00000), .ES_QUALIFIER0(16'h0000), .ES_QUALIFIER1(16'h0000), .ES_QUALIFIER2(16'h0000), .ES_QUALIFIER3(16'h0000), .ES_QUALIFIER4(16'h0000), .ES_QUAL_MASK0(16'h0000), .ES_QUAL_MASK1(16'h0000), .ES_QUAL_MASK2(16'h0000), .ES_QUAL_MASK3(16'h0000), .ES_QUAL_MASK4(16'h0000), .ES_SDATA_MASK0(16'h0000), .ES_SDATA_MASK1(16'h0000), .ES_SDATA_MASK2(16'h0000), .ES_SDATA_MASK3(16'h0000), .ES_SDATA_MASK4(16'h0000), .EVODD_PHI_CFG(11'b00000000000), .EYE_SCAN_SWAP_EN(1'b0), .FTS_DESKEW_SEQ_ENABLE(4'b1111), .FTS_LANE_DESKEW_CFG(4'b1111), .FTS_LANE_DESKEW_EN("FALSE"), .GEARBOX_MODE(5'b00000), .GM_BIAS_SELECT(1'b0), .LOCAL_MASTER(1'b1), .OOBDIVCTL(2'b00), .OOB_PWRUP(1'b0), .PCI3_AUTO_REALIGN("OVR_1K_BLK"), .PCI3_PIPE_RX_ELECIDLE(1'b0), .PCI3_RX_ASYNC_EBUF_BYPASS(2'b00), .PCI3_RX_ELECIDLE_EI2_ENABLE(1'b0), .PCI3_RX_ELECIDLE_H2L_COUNT(6'b000000), .PCI3_RX_ELECIDLE_H2L_DISABLE(3'b000), .PCI3_RX_ELECIDLE_HI_COUNT(6'b000000), .PCI3_RX_ELECIDLE_LP4_DISABLE(1'b0), .PCI3_RX_FIFO_DISABLE(1'b0), .PCIE_BUFG_DIV_CTRL(16'h1000), .PCIE_RXPCS_CFG_GEN3(16'h02A4), .PCIE_RXPMA_CFG(16'h000A), .PCIE_TXPCS_CFG_GEN3(16'h2CA4), .PCIE_TXPMA_CFG(16'h000A), .PCS_PCIE_EN("FALSE"), .PCS_RSVD0(16'b0000000000000000), .PCS_RSVD1(3'b000), .PD_TRANS_TIME_FROM_P2(12'h03C), .PD_TRANS_TIME_NONE_P2(8'h19), .PD_TRANS_TIME_TO_P2(8'h64), .PLL_SEL_MODE_GEN12(2'h0), .PLL_SEL_MODE_GEN3(2'h3), .PMA_RSV1(16'hF000), .PROCESS_PAR(3'b010), .RATE_SW_USE_DRP(1'b1), .RESET_POWERSAVE_DISABLE(1'b0), .RXBUFRESET_TIME(5'b00011), .RXBUF_ADDR_MODE("FULL"), .RXBUF_EIDLE_HI_CNT(4'b1000), .RXBUF_EIDLE_LO_CNT(4'b0000), .RXBUF_EN("TRUE"), .RXBUF_RESET_ON_CB_CHANGE("TRUE"), .RXBUF_RESET_ON_COMMAALIGN("FALSE"), .RXBUF_RESET_ON_EIDLE("FALSE"), .RXBUF_RESET_ON_RATE_CHANGE("TRUE"), .RXBUF_THRESH_OVFLW(0), .RXBUF_THRESH_OVRD("FALSE"), .RXBUF_THRESH_UNDFLW(0), .RXCDRFREQRESET_TIME(5'b00001), .RXCDRPHRESET_TIME(5'b00001), .RXCDR_CFG0(16'h0000), .RXCDR_CFG0_GEN3(16'h0000), .RXCDR_CFG1(16'h0000), .RXCDR_CFG1_GEN3(16'h0000), .RXCDR_CFG2(16'h0746), .RXCDR_CFG2_GEN3(16'h07E6), .RXCDR_CFG3(16'h0000), .RXCDR_CFG3_GEN3(16'h0000), .RXCDR_CFG4(16'h0000), .RXCDR_CFG4_GEN3(16'h0000), .RXCDR_CFG5(16'h0000), .RXCDR_CFG5_GEN3(16'h0000), .RXCDR_FR_RESET_ON_EIDLE(1'b0), .RXCDR_HOLD_DURING_EIDLE(1'b0), .RXCDR_LOCK_CFG0(16'h4480), .RXCDR_LOCK_CFG1(16'h5FFF), .RXCDR_LOCK_CFG2(16'h77C3), .RXCDR_PH_RESET_ON_EIDLE(1'b0), .RXCFOK_CFG0(16'h4000), .RXCFOK_CFG1(16'h0065), .RXCFOK_CFG2(16'h002E), .RXDFELPMRESET_TIME(7'b0001111), .RXDFELPM_KL_CFG0(16'h0000), .RXDFELPM_KL_CFG1(16'h0032), .RXDFELPM_KL_CFG2(16'h0000), .RXDFE_CFG0(16'h0A00), .RXDFE_CFG1(16'h0000), .RXDFE_GC_CFG0(16'h0000), .RXDFE_GC_CFG1(16'h7870), .RXDFE_GC_CFG2(16'h0000), .RXDFE_H2_CFG0(16'h0000), .RXDFE_H2_CFG1(16'h0000), .RXDFE_H3_CFG0(16'h4000), .RXDFE_H3_CFG1(16'h0000), .RXDFE_H4_CFG0(16'h2000), .RXDFE_H4_CFG1(16'h0003), .RXDFE_H5_CFG0(16'h2000), .RXDFE_H5_CFG1(16'h0003), .RXDFE_H6_CFG0(16'h2000), .RXDFE_H6_CFG1(16'h0000), .RXDFE_H7_CFG0(16'h2000), .RXDFE_H7_CFG1(16'h0000), .RXDFE_H8_CFG0(16'h2000), .RXDFE_H8_CFG1(16'h0000), .RXDFE_H9_CFG0(16'h2000), .RXDFE_H9_CFG1(16'h0000), .RXDFE_HA_CFG0(16'h2000), .RXDFE_HA_CFG1(16'h0000), .RXDFE_HB_CFG0(16'h2000), .RXDFE_HB_CFG1(16'h0000), .RXDFE_HC_CFG0(16'h0000), .RXDFE_HC_CFG1(16'h0000), .RXDFE_HD_CFG0(16'h0000), .RXDFE_HD_CFG1(16'h0000), .RXDFE_HE_CFG0(16'h0000), .RXDFE_HE_CFG1(16'h0000), .RXDFE_HF_CFG0(16'h0000), .RXDFE_HF_CFG1(16'h0000), .RXDFE_OS_CFG0(16'h8000), .RXDFE_OS_CFG1(16'h0000), .RXDFE_UT_CFG0(16'h8000), .RXDFE_UT_CFG1(16'h0003), .RXDFE_VP_CFG0(16'hAA00), .RXDFE_VP_CFG1(16'h0033), .RXDLY_CFG(16'h001F), .RXDLY_LCFG(16'h0030), .RXELECIDLE_CFG("Sigcfg_4"), .RXGBOX_FIFO_INIT_RD_ADDR(4), .RXGEARBOX_EN("FALSE"), .RXISCANRESET_TIME(5'b00001), .RXLPM_CFG(16'h0000), .RXLPM_GC_CFG(16'h1000), .RXLPM_KH_CFG0(16'h0000), .RXLPM_KH_CFG1(16'h0002), .RXLPM_OS_CFG0(16'h8000), .RXLPM_OS_CFG1(16'h0002), .RXOOB_CFG(9'b000000110), .RXOOB_CLK_CFG("PMA"), .RXOSCALRESET_TIME(5'b00011), .RXOUT_DIV(4), .RXPCSRESET_TIME(5'b00011), .RXPHBEACON_CFG(16'h0000), .RXPHDLY_CFG(16'h2020), .RXPHSAMP_CFG(16'h2100), .RXPHSLIP_CFG(16'h6622), .RXPH_MONITOR_SEL(5'b00000), .RXPI_CFG0(2'b01), .RXPI_CFG1(2'b01), .RXPI_CFG2(2'b01), .RXPI_CFG3(2'b01), .RXPI_CFG4(1'b1), .RXPI_CFG5(1'b1), .RXPI_CFG6(3'b011), .RXPI_LPM(1'b0), .RXPI_VREFSEL(1'b0), .RXPMACLK_SEL("DATA"), .RXPMARESET_TIME(5'b00011), .RXPRBS_ERR_LOOPBACK(1'b0), .RXPRBS_LINKACQ_CNT(15), .RXSLIDE_AUTO_WAIT(7), .RXSLIDE_MODE("OFF"), .RXSYNC_MULTILANE(1'b0), .RXSYNC_OVRD(1'b0), .RXSYNC_SKIP_DA(1'b0), .RX_AFE_CM_EN(1'b0), .RX_BIAS_CFG0(16'h0AB4), .RX_BUFFER_CFG(6'b000000), .RX_CAPFF_SARC_ENB(1'b0), .RX_CLK25_DIV(5), .RX_CLKMUX_EN(1'b1), .RX_CLK_SLIP_OVRD(5'b00000), .RX_CM_BUF_CFG(4'b1010), .RX_CM_BUF_PD(1'b0), .RX_CM_SEL(2'b11), .RX_CM_TRIM(4'b1010), .RX_CTLE3_LPF(8'b00000001), .RX_DATA_WIDTH(20), .RX_DDI_SEL(6'b000000), .RX_DEFER_RESET_BUF_EN("TRUE"), .RX_DFELPM_CFG0(4'b0110), .RX_DFELPM_CFG1(1'b1), .RX_DFELPM_KLKH_AGC_STUP_EN(1'b1), .RX_DFE_AGC_CFG0(2'b10), .RX_DFE_AGC_CFG1(3'b000), .RX_DFE_KL_LPM_KH_CFG0(2'b01), .RX_DFE_KL_LPM_KH_CFG1(3'b000), .RX_DFE_KL_LPM_KL_CFG0(2'b01), .RX_DFE_KL_LPM_KL_CFG1(3'b000), .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b0), .RX_DISPERR_SEQ_MATCH("TRUE"), .RX_DIVRESET_TIME(5'b00001), .RX_EN_HI_LR(1'b0), .RX_EYESCAN_VS_CODE(7'b0000000), .RX_EYESCAN_VS_NEG_DIR(1'b0), .RX_EYESCAN_VS_RANGE(2'b00), .RX_EYESCAN_VS_UT_SIGN(1'b0), .RX_FABINT_USRCLK_FLOP(1'b0), .RX_INT_DATAWIDTH(0), .RX_PMA_POWER_SAVE(1'b0), .RX_PROGDIV_CFG(0.000000), .RX_SAMPLE_PERIOD(3'b111), .RX_SIG_VALID_DLY(11), .RX_SUM_DFETAPREP_EN(1'b0), .RX_SUM_IREF_TUNE(4'b1100), .RX_SUM_RES_CTRL(2'b11), .RX_SUM_VCMTUNE(4'b0000), .RX_SUM_VCM_OVWR(1'b0), .RX_SUM_VREF_TUNE(3'b000), .RX_TUNE_AFE_OS(2'b10), .RX_WIDEMODE_CDR(1'b0), .RX_XCLK_SEL("RXDES"), .SAS_MAX_COM(64), .SAS_MIN_COM(36), .SATA_BURST_SEQ_LEN(4'b1110), .SATA_BURST_VAL(3'b100), .SATA_CPLL_CFG("VCO_3000MHZ"), .SATA_EIDLE_VAL(3'b100), .SATA_MAX_BURST(8), .SATA_MAX_INIT(21), .SATA_MAX_WAKE(7), .SATA_MIN_BURST(4), .SATA_MIN_INIT(12), .SATA_MIN_WAKE(4), .SHOW_REALIGN_COMMA("TRUE"), .SIM_MODE("FAST"), .SIM_RECEIVER_DETECT_PASS("TRUE"), .SIM_RESET_SPEEDUP("TRUE"), .SIM_TX_EIDLE_DRIVE_LEVEL(1'b0), .SIM_VERSION(2), .TAPDLY_SET_TX(2'h0), .TEMPERATUR_PAR(4'b0010), .TERM_RCAL_CFG(15'b100001000010000), .TERM_RCAL_OVRD(3'b000), .TRANS_TIME_RATE(8'h0E), .TST_RSV0(8'h00), .TST_RSV1(8'h00), .TXBUF_EN("TRUE"), .TXBUF_RESET_ON_RATE_CHANGE("TRUE"), .TXDLY_CFG(16'h0009), .TXDLY_LCFG(16'h0050), .TXDRVBIAS_N(4'b1010), .TXDRVBIAS_P(4'b1010), .TXFIFO_ADDR_CFG("LOW"), .TXGBOX_FIFO_INIT_RD_ADDR(4), .TXGEARBOX_EN("FALSE"), .TXOUT_DIV(4), .TXPCSRESET_TIME(5'b00011), .TXPHDLY_CFG0(16'h2020), .TXPHDLY_CFG1(16'h0075), .TXPH_CFG(16'h0980), .TXPH_MONITOR_SEL(5'b00000), .TXPI_CFG0(2'b01), .TXPI_CFG1(2'b01), .TXPI_CFG2(2'b01), .TXPI_CFG3(1'b1), .TXPI_CFG4(1'b1), .TXPI_CFG5(3'b011), .TXPI_GRAY_SEL(1'b0), .TXPI_INVSTROBE_SEL(1'b1), .TXPI_LPM(1'b0), .TXPI_PPMCLK_SEL("TXUSRCLK2"), .TXPI_PPM_CFG(8'b00000000), .TXPI_SYNFREQ_PPM(3'b001), .TXPI_VREFSEL(1'b0), .TXPMARESET_TIME(5'b00011), .TXSYNC_MULTILANE(1'b0), .TXSYNC_OVRD(1'b0), .TXSYNC_SKIP_DA(1'b0), .TX_CLK25_DIV(5), .TX_CLKMUX_EN(1'b1), .TX_DATA_WIDTH(20), .TX_DCD_CFG(6'b000010), .TX_DCD_EN(1'b0), .TX_DEEMPH0(6'b000000), .TX_DEEMPH1(6'b000000), .TX_DIVRESET_TIME(5'b00001), .TX_DRIVE_MODE("DIRECT"), .TX_EIDLE_ASSERT_DELAY(3'b100), .TX_EIDLE_DEASSERT_DELAY(3'b011), .TX_EML_PHI_TUNE(1'b0), .TX_FABINT_USRCLK_FLOP(1'b0), .TX_IDLE_DATA_ZERO(1'b0), .TX_INT_DATAWIDTH(0), .TX_LOOPBACK_DRIVE_HIZ("FALSE"), .TX_MAINCURSOR_SEL(1'b0), .TX_MARGIN_FULL_0(7'b1001111), .TX_MARGIN_FULL_1(7'b1001110), .TX_MARGIN_FULL_2(7'b1001100), .TX_MARGIN_FULL_3(7'b1001010), .TX_MARGIN_FULL_4(7'b1001000), .TX_MARGIN_LOW_0(7'b1000110), .TX_MARGIN_LOW_1(7'b1000101), .TX_MARGIN_LOW_2(7'b1000011), .TX_MARGIN_LOW_3(7'b1000010), .TX_MARGIN_LOW_4(7'b1000000), .TX_MODE_SEL(3'b000), .TX_PMADATA_OPT(1'b0), .TX_PMA_POWER_SAVE(1'b0), .TX_PROGCLK_SEL("CPLL"), .TX_PROGDIV_CFG(20.000000), .TX_QPI_STATUS_EN(1'b0), .TX_RXDETECT_CFG(14'h0032), .TX_RXDETECT_REF(3'b100), .TX_SAMPLE_PERIOD(3'b111), .TX_SARC_LPBK_ENB(1'b0), .TX_XCLK_SEL("TXOUT"), .USE_PCS_CLK_PHASE_SEL(1'b0), .WB_MODE(2'b00)) \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST (.BUFGTCE({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_289 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_290 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_291 }), .BUFGTCEMASK({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_292 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_293 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_294 }), .BUFGTDIV({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_357 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_358 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_359 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_360 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_361 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_362 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_363 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_364 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_365 }), .BUFGTRESET({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_295 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_296 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_297 }), .BUFGTRSTMASK({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_298 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_299 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_300 }), .CFGRESET(1'b0), .CLKRSVD0(1'b0), .CLKRSVD1(1'b0), .CPLLFBCLKLOST(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_0 ), .CPLLLOCK(cplllock_out), .CPLLLOCKDETCLK(1'b0), .CPLLLOCKEN(1'b1), .CPLLPD(\gen_gtwizard_gthe3.cpllpd_ch_int ), .CPLLREFCLKLOST(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_2 ), .CPLLREFCLKSEL({1'b0,1'b0,1'b1}), .CPLLRESET(1'b0), .DMONFIFORESET(1'b0), .DMONITORCLK(1'b0), .DMONITOROUT({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_258 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_259 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_260 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_261 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_262 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_263 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_264 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_265 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_266 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_267 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_268 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_269 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_270 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_271 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_272 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_273 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_274 }), .DRPADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DRPCLK(drpclk_in), .DRPDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DRPDO({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_210 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_211 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_212 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_213 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_214 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_215 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_216 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_217 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_218 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_219 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_220 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_221 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_222 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_223 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_224 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_225 }), .DRPEN(1'b0), .DRPRDY(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_3 ), .DRPWE(1'b0), .EVODDPHICALDONE(1'b0), .EVODDPHICALSTART(1'b0), .EVODDPHIDRDEN(1'b0), .EVODDPHIDWREN(1'b0), .EVODDPHIXRDEN(1'b0), .EVODDPHIXWREN(1'b0), .EYESCANDATAERROR(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_4 ), .EYESCANMODE(1'b0), .EYESCANRESET(1'b0), .EYESCANTRIGGER(1'b0), .GTGREFCLK(1'b0), .GTHRXN(gthrxn_in), .GTHRXP(gthrxp_in), .GTHTXN(gthtxn_out), .GTHTXP(gthtxp_out), .GTNORTHREFCLK0(1'b0), .GTNORTHREFCLK1(1'b0), .GTPOWERGOOD(gtpowergood_out), .GTREFCLK0(gtrefclk0_in), .GTREFCLK1(1'b0), .GTREFCLKMONITOR(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_8 ), .GTRESETSEL(1'b0), .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .GTRXRESET(\gen_gtwizard_gthe3.gtrxreset_int ), .GTSOUTHREFCLK0(1'b0), .GTSOUTHREFCLK1(1'b0), .GTTXRESET(\gen_gtwizard_gthe3.gttxreset_int ), .LOOPBACK({1'b0,1'b0,1'b0}), .LPBKRXTXSEREN(1'b0), .LPBKTXRXSEREN(1'b0), .PCIEEQRXEQADAPTDONE(1'b0), .PCIERATEGEN3(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_9 ), .PCIERATEIDLE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_10 ), .PCIERATEQPLLPD({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_275 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_276 }), .PCIERATEQPLLRESET({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_277 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_278 }), .PCIERSTIDLE(1'b0), .PCIERSTTXSYNCSTART(1'b0), .PCIESYNCTXSYNCDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_11 ), .PCIEUSERGEN3RDY(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_12 ), .PCIEUSERPHYSTATUSRST(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_13 ), .PCIEUSERRATEDONE(1'b0), .PCIEUSERRATESTART(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_14 ), .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}), .PCSRSVDOUT({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_70 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_71 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_72 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_73 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_74 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_75 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_76 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_77 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_78 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_79 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_80 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_81 }), .PHYSTATUS(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_15 ), .PINRSRVDAS({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_325 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_326 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_327 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_328 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_329 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_330 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_331 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_332 }), .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .QPLL0CLK(1'b0), .QPLL0REFCLK(1'b0), .QPLL1CLK(1'b0), .QPLL1REFCLK(1'b0), .RESETEXCEPTION(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_16 ), .RESETOVRD(1'b0), .RSTCLKENTX(1'b0), .RX8B10BEN(1'b1), .RXBUFRESET(1'b0), .RXBUFSTATUS({rxbufstatus_out,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_302 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_303 }), .RXBYTEISALIGNED(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_17 ), .RXBYTEREALIGN(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_18 ), .RXCDRFREQRESET(1'b0), .RXCDRHOLD(1'b0), .RXCDRLOCK(rxcdrlock_out), .RXCDROVRDEN(1'b0), .RXCDRPHDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_20 ), .RXCDRRESET(1'b0), .RXCDRRESETRSV(1'b0), .RXCHANBONDSEQ(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_21 ), .RXCHANISALIGNED(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_22 ), .RXCHANREALIGN(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_23 ), .RXCHBONDEN(1'b0), .RXCHBONDI({1'b0,1'b0,1'b0,1'b0,1'b0}), .RXCHBONDLEVEL({1'b0,1'b0,1'b0}), .RXCHBONDMASTER(1'b0), .RXCHBONDO({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_307 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_308 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_309 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_310 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_311 }), .RXCHBONDSLAVE(1'b0), .RXCLKCORCNT(rxclkcorcnt_out), .RXCOMINITDET(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_24 ), .RXCOMMADET(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_25 ), .RXCOMMADETEN(1'b1), .RXCOMSASDET(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_26 ), .RXCOMWAKEDET(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_27 ), .RXCTRL0({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_226 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_227 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_228 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_229 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_230 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_231 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_232 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_233 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_234 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_235 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_236 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_237 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_238 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_239 ,rxctrl0_out}), .RXCTRL1({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_242 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_243 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_244 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_245 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_246 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_247 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_248 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_249 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_250 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_251 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_252 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_253 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_254 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_255 ,rxctrl1_out}), .RXCTRL2({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_333 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_334 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_335 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_336 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_337 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_338 ,rxctrl2_out}), .RXCTRL3({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_341 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_342 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_343 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_344 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_345 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_346 ,rxctrl3_out}), .RXDATA({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_82 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_83 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_84 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_85 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_86 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_87 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_88 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_89 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_90 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_91 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_92 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_93 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_94 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_95 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_96 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_97 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_98 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_99 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_100 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_101 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_102 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_103 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_104 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_105 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_106 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_107 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_108 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_109 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_110 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_111 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_112 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_113 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_114 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_115 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_116 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_117 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_118 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_119 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_120 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_121 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_122 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_123 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_124 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_125 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_126 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_127 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_128 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_129 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_130 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_131 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_132 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_133 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_134 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_135 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_136 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_137 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_138 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_139 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_140 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_141 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_142 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_143 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_144 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_145 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_146 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_147 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_148 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_149 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_150 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_151 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_152 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_153 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_154 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_155 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_156 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_157 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_158 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_159 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_160 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_161 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_162 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_163 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_164 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_165 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_166 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_167 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_168 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_169 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_170 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_171 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_172 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_173 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_174 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_175 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_176 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_177 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_178 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_179 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_180 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_181 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_182 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_183 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_184 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_185 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_186 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_187 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_188 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_189 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_190 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_191 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_192 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_193 ,gtwiz_userdata_rx_out}), .RXDATAEXTENDRSVD({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_349 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_350 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_351 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_352 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_353 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_354 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_355 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_356 }), .RXDATAVALID({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_281 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_282 }), .RXDFEAGCCTRL({1'b0,1'b1}), .RXDFEAGCHOLD(1'b0), .RXDFEAGCOVRDEN(1'b0), .RXDFELFHOLD(1'b0), .RXDFELFOVRDEN(1'b0), .RXDFELPMRESET(1'b0), .RXDFETAP10HOLD(1'b0), .RXDFETAP10OVRDEN(1'b0), .RXDFETAP11HOLD(1'b0), .RXDFETAP11OVRDEN(1'b0), .RXDFETAP12HOLD(1'b0), .RXDFETAP12OVRDEN(1'b0), .RXDFETAP13HOLD(1'b0), .RXDFETAP13OVRDEN(1'b0), .RXDFETAP14HOLD(1'b0), .RXDFETAP14OVRDEN(1'b0), .RXDFETAP15HOLD(1'b0), .RXDFETAP15OVRDEN(1'b0), .RXDFETAP2HOLD(1'b0), .RXDFETAP2OVRDEN(1'b0), .RXDFETAP3HOLD(1'b0), .RXDFETAP3OVRDEN(1'b0), .RXDFETAP4HOLD(1'b0), .RXDFETAP4OVRDEN(1'b0), .RXDFETAP5HOLD(1'b0), .RXDFETAP5OVRDEN(1'b0), .RXDFETAP6HOLD(1'b0), .RXDFETAP6OVRDEN(1'b0), .RXDFETAP7HOLD(1'b0), .RXDFETAP7OVRDEN(1'b0), .RXDFETAP8HOLD(1'b0), .RXDFETAP8OVRDEN(1'b0), .RXDFETAP9HOLD(1'b0), .RXDFETAP9OVRDEN(1'b0), .RXDFEUTHOLD(1'b0), .RXDFEUTOVRDEN(1'b0), .RXDFEVPHOLD(1'b0), .RXDFEVPOVRDEN(1'b0), .RXDFEVSEN(1'b0), .RXDFEXYDEN(1'b1), .RXDLYBYPASS(1'b1), .RXDLYEN(1'b0), .RXDLYOVRDEN(1'b0), .RXDLYSRESET(1'b0), .RXDLYSRESETDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_28 ), .RXELECIDLE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_29 ), .RXELECIDLEMODE({1'b1,1'b1}), .RXGEARBOXSLIP(1'b0), .RXHEADER({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_312 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_313 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_314 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_315 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_316 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_317 }), .RXHEADERVALID({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_283 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_284 }), .RXLATCLK(1'b0), .RXLPMEN(1'b1), .RXLPMGCHOLD(1'b0), .RXLPMGCOVRDEN(1'b0), .RXLPMHFHOLD(1'b0), .RXLPMHFOVRDEN(1'b0), .RXLPMLFHOLD(1'b0), .RXLPMLFKLOVRDEN(1'b0), .RXLPMOSHOLD(1'b0), .RXLPMOSOVRDEN(1'b0), .RXMCOMMAALIGNEN(rxmcommaalignen_in), .RXMONITOROUT({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_318 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_319 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_320 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_321 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_322 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_323 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_324 }), .RXMONITORSEL({1'b0,1'b0}), .RXOOBRESET(1'b0), .RXOSCALRESET(1'b0), .RXOSHOLD(1'b0), .RXOSINTCFG({1'b1,1'b1,1'b0,1'b1}), .RXOSINTDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_30 ), .RXOSINTEN(1'b1), .RXOSINTHOLD(1'b0), .RXOSINTOVRDEN(1'b0), .RXOSINTSTARTED(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_31 ), .RXOSINTSTROBE(1'b0), .RXOSINTSTROBEDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_32 ), .RXOSINTSTROBESTARTED(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_33 ), .RXOSINTTESTOVRDEN(1'b0), .RXOSOVRDEN(1'b0), .RXOUTCLK(rxoutclk_out), .RXOUTCLKFABRIC(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_35 ), .RXOUTCLKPCS(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_36 ), .RXOUTCLKSEL({1'b0,1'b1,1'b0}), .RXPCOMMAALIGNEN(rxmcommaalignen_in), .RXPCSRESET(1'b0), .RXPD({rxpd_in,rxpd_in}), .RXPHALIGN(1'b0), .RXPHALIGNDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_37 ), .RXPHALIGNEN(1'b0), .RXPHALIGNERR(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_38 ), .RXPHDLYPD(1'b1), .RXPHDLYRESET(1'b0), .RXPHOVRDEN(1'b0), .RXPLLCLKSEL({1'b0,1'b0}), .RXPMARESET(1'b0), .RXPMARESETDONE(rxpmaresetdone_out), .RXPOLARITY(1'b0), .RXPRBSCNTRESET(1'b0), .RXPRBSERR(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_40 ), .RXPRBSLOCKED(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_41 ), .RXPRBSSEL({1'b0,1'b0,1'b0,1'b0}), .RXPRGDIVRESETDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_42 ), .RXPROGDIVRESET(\gen_gtwizard_gthe3.rxprogdivreset_int ), .RXQPIEN(1'b0), .RXQPISENN(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_43 ), .RXQPISENP(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_44 ), .RXRATE({1'b0,1'b0,1'b0}), .RXRATEDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_45 ), .RXRATEMODE(1'b0), .RXRECCLKOUT(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_46 ), .RXRESETDONE(rxresetdone_out), .RXSLIDE(1'b0), .RXSLIDERDY(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_48 ), .RXSLIPDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_49 ), .RXSLIPOUTCLK(1'b0), .RXSLIPOUTCLKRDY(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_50 ), .RXSLIPPMA(1'b0), .RXSLIPPMARDY(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_51 ), .RXSTARTOFSEQ({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_285 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_286 }), .RXSTATUS({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_304 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_305 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_306 }), .RXSYNCALLIN(1'b0), .RXSYNCDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_52 ), .RXSYNCIN(1'b0), .RXSYNCMODE(1'b0), .RXSYNCOUT(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_53 ), .RXSYSCLKSEL({1'b0,1'b0}), .RXUSERRDY(\gen_gtwizard_gthe3.rxuserrdy_int ), .RXUSRCLK(rxusrclk_in), .RXUSRCLK2(rxusrclk_in), .RXVALID(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_54 ), .SIGVALIDCLK(1'b0), .TSTIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TX8B10BEN(1'b1), .TXBUFDIFFCTRL({1'b0,1'b0,1'b0}), .TXBUFSTATUS({txbufstatus_out,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_288 }), .TXCOMFINISH(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_55 ), .TXCOMINIT(1'b0), .TXCOMSAS(1'b0), .TXCOMWAKE(1'b0), .TXCTRL0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txctrl0_in}), .TXCTRL1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txctrl1_in}), .TXCTRL2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,txctrl2_in}), .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gtwiz_userdata_tx_in}), .TXDATAEXTENDRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXDEEMPH(1'b0), .TXDETECTRX(1'b0), .TXDIFFCTRL({1'b1,1'b0,1'b0,1'b0}), .TXDIFFPD(1'b0), .TXDLYBYPASS(1'b1), .TXDLYEN(1'b0), .TXDLYHOLD(1'b0), .TXDLYOVRDEN(1'b0), .TXDLYSRESET(1'b0), .TXDLYSRESETDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_56 ), .TXDLYUPDOWN(1'b0), .TXELECIDLE(txelecidle_in), .TXHEADER({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXINHIBIT(1'b0), .TXLATCLK(1'b0), .TXMAINCURSOR({1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXMARGIN({1'b0,1'b0,1'b0}), .TXOUTCLK(txoutclk_out), .TXOUTCLKFABRIC(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_58 ), .TXOUTCLKPCS(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_59 ), .TXOUTCLKSEL({1'b1,1'b0,1'b1}), .TXPCSRESET(1'b0), .TXPD({txelecidle_in,txelecidle_in}), .TXPDELECIDLEMODE(1'b0), .TXPHALIGN(1'b0), .TXPHALIGNDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_60 ), .TXPHALIGNEN(1'b0), .TXPHDLYPD(1'b1), .TXPHDLYRESET(1'b0), .TXPHDLYTSTCLK(1'b0), .TXPHINIT(1'b0), .TXPHINITDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_61 ), .TXPHOVRDEN(1'b0), .TXPIPPMEN(1'b0), .TXPIPPMOVRDEN(1'b0), .TXPIPPMPD(1'b0), .TXPIPPMSEL(1'b0), .TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}), .TXPISOPD(1'b0), .TXPLLCLKSEL({1'b0,1'b0}), .TXPMARESET(1'b0), .TXPMARESETDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_62 ), .TXPOLARITY(1'b0), .TXPOSTCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}), .TXPOSTCURSORINV(1'b0), .TXPRBSFORCEERR(1'b0), .TXPRBSSEL({1'b0,1'b0,1'b0,1'b0}), .TXPRECURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}), .TXPRECURSORINV(1'b0), .TXPRGDIVRESETDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_63 ), .TXPROGDIVRESET(\gen_gtwizard_gthe3.txprogdivreset_int ), .TXQPIBIASEN(1'b0), .TXQPISENN(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_64 ), .TXQPISENP(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_65 ), .TXQPISTRONGPDOWN(1'b0), .TXQPIWEAKPUP(1'b0), .TXRATE({1'b0,1'b0,1'b0}), .TXRATEDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_66 ), .TXRATEMODE(1'b0), .TXRESETDONE(txresetdone_out), .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXSWING(1'b0), .TXSYNCALLIN(1'b0), .TXSYNCDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_68 ), .TXSYNCIN(1'b0), .TXSYNCMODE(1'b0), .TXSYNCOUT(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69 ), .TXSYSCLKSEL({1'b0,1'b0}), .TXUSERRDY(\gen_gtwizard_gthe3.txuserrdy_int ), .TXUSRCLK(rxusrclk_in), .TXUSRCLK2(rxusrclk_in)); LUT1 #( .INIT(2'h1)) rst_in_meta_i_1__2 (.I0(cplllock_out), .O(rst_in0)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_gtwiz_reset (\gen_gtwizard_gthe3.txprogdivreset_int , gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out, \gen_gtwizard_gthe3.gttxreset_int , \gen_gtwizard_gthe3.txuserrdy_int , \gen_gtwizard_gthe3.rxprogdivreset_int , \gen_gtwizard_gthe3.gtrxreset_int , \gen_gtwizard_gthe3.rxuserrdy_int , \gen_gtwizard_gthe3.cpllpd_ch_int , gtpowergood_out, gtwiz_userclk_tx_active_in, cplllock_out, rxpmaresetdone_out, rxcdrlock_out, drpclk_in, gtwiz_reset_all_in, gtwiz_reset_tx_datapath_in, rst_in0, rxusrclk_in, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync , gtwiz_reset_rx_datapath_in, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ); output \gen_gtwizard_gthe3.txprogdivreset_int ; output [0:0]gtwiz_reset_tx_done_out; output [0:0]gtwiz_reset_rx_done_out; output \gen_gtwizard_gthe3.gttxreset_int ; output \gen_gtwizard_gthe3.txuserrdy_int ; output \gen_gtwizard_gthe3.rxprogdivreset_int ; output \gen_gtwizard_gthe3.gtrxreset_int ; output \gen_gtwizard_gthe3.rxuserrdy_int ; output \gen_gtwizard_gthe3.cpllpd_ch_int ; input [0:0]gtpowergood_out; input [0:0]gtwiz_userclk_tx_active_in; input [0:0]cplllock_out; input [0:0]rxpmaresetdone_out; input [0:0]rxcdrlock_out; input [0:0]drpclk_in; input [0:0]gtwiz_reset_all_in; input [0:0]gtwiz_reset_tx_datapath_in; input rst_in0; input [0:0]rxusrclk_in; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; input [0:0]gtwiz_reset_rx_datapath_in; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; wire \FSM_sequential_sm_reset_all[2]_i_3_n_0 ; wire \FSM_sequential_sm_reset_all[2]_i_4_n_0 ; wire \FSM_sequential_sm_reset_rx[1]_i_2_n_0 ; wire \FSM_sequential_sm_reset_rx[2]_i_6_n_0 ; wire \FSM_sequential_sm_reset_tx[2]_i_3_n_0 ; wire bit_synchronizer_gtpowergood_inst_n_0; wire bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst_n_2; wire bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0; wire bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0; wire bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1; wire bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2; wire bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1; wire bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2; wire bit_synchronizer_plllock_rx_inst_n_1; wire bit_synchronizer_plllock_rx_inst_n_2; wire bit_synchronizer_plllock_tx_inst_n_1; wire bit_synchronizer_plllock_tx_inst_n_2; wire bit_synchronizer_rxcdrlock_inst_n_0; wire bit_synchronizer_rxcdrlock_inst_n_1; wire bit_synchronizer_rxcdrlock_inst_n_2; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.cpllpd_ch_int ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; wire \gen_gtwizard_gthe3.gtrxreset_int ; wire \gen_gtwizard_gthe3.gttxreset_int ; wire \gen_gtwizard_gthe3.rxprogdivreset_int ; wire \gen_gtwizard_gthe3.rxuserrdy_int ; wire \gen_gtwizard_gthe3.txprogdivreset_int ; wire \gen_gtwizard_gthe3.txuserrdy_int ; wire [0:0]gtpowergood_out; wire gttxreset_out_i_3_n_0; wire [0:0]gtwiz_reset_all_in; wire gtwiz_reset_all_sync; wire gtwiz_reset_rx_any_sync; wire gtwiz_reset_rx_datapath_dly; wire [0:0]gtwiz_reset_rx_datapath_in; wire gtwiz_reset_rx_datapath_int_i_1_n_0; wire gtwiz_reset_rx_datapath_int_reg_n_0; wire gtwiz_reset_rx_datapath_sync; wire gtwiz_reset_rx_done_int_reg_n_0; wire [0:0]gtwiz_reset_rx_done_out; wire gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0; wire gtwiz_reset_rx_pll_and_datapath_int_reg_n_0; wire gtwiz_reset_rx_pll_and_datapath_sync; wire gtwiz_reset_tx_any_sync; wire [0:0]gtwiz_reset_tx_datapath_in; wire gtwiz_reset_tx_datapath_sync; wire gtwiz_reset_tx_done_int_reg_n_0; wire [0:0]gtwiz_reset_tx_done_out; wire gtwiz_reset_tx_pll_and_datapath_dly; wire gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0; wire gtwiz_reset_tx_pll_and_datapath_int_reg_n_0; wire gtwiz_reset_tx_pll_and_datapath_sync; wire gtwiz_reset_userclk_tx_active_sync; wire [0:0]gtwiz_userclk_tx_active_in; wire p_0_in; wire [9:0]p_0_in__0; wire [9:0]p_0_in__1; wire [2:0]p_1_in; wire plllock_rx_sync; wire plllock_tx_sync; wire reset_synchronizer_gtwiz_reset_rx_any_inst_n_1; wire reset_synchronizer_gtwiz_reset_rx_any_inst_n_2; wire reset_synchronizer_gtwiz_reset_rx_any_inst_n_3; wire reset_synchronizer_gtwiz_reset_tx_any_inst_n_1; wire reset_synchronizer_gtwiz_reset_tx_any_inst_n_2; wire reset_synchronizer_gtwiz_reset_tx_any_inst_n_3; wire rst_in0; wire [0:0]rxcdrlock_out; wire [0:0]rxpmaresetdone_out; wire [0:0]rxusrclk_in; wire sel; wire [2:0]sm_reset_all; wire [2:0]sm_reset_all__0; wire sm_reset_all_timer_clr_i_1_n_0; wire sm_reset_all_timer_clr_i_2_n_0; wire sm_reset_all_timer_clr_reg_n_0; wire [2:0]sm_reset_all_timer_ctr; wire sm_reset_all_timer_ctr0_n_0; wire \sm_reset_all_timer_ctr[0]_i_1_n_0 ; wire \sm_reset_all_timer_ctr[1]_i_1_n_0 ; wire \sm_reset_all_timer_ctr[2]_i_1_n_0 ; wire sm_reset_all_timer_sat; wire sm_reset_all_timer_sat_i_1_n_0; wire [2:0]sm_reset_rx; wire [2:0]sm_reset_rx__0; wire sm_reset_rx_cdr_to_clr; wire sm_reset_rx_cdr_to_clr_i_3_n_0; wire \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ; wire \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0 ; wire \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0 ; wire \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0 ; wire \sm_reset_rx_cdr_to_ctr[0]_i_6_n_0 ; wire \sm_reset_rx_cdr_to_ctr[0]_i_7_n_0 ; wire [25:0]sm_reset_rx_cdr_to_ctr_reg; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_1 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_2 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_3 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_4 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_5 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_6 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_7 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_1 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_2 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_3 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_4 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_5 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_6 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_7 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9 ; wire \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14 ; wire \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15 ; wire \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_7 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_1 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_2 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_3 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_4 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_5 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_6 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_7 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9 ; wire sm_reset_rx_cdr_to_sat; wire sm_reset_rx_cdr_to_sat_i_1_n_0; wire sm_reset_rx_cdr_to_sat_i_2_n_0; wire sm_reset_rx_cdr_to_sat_i_3_n_0; wire sm_reset_rx_cdr_to_sat_i_4_n_0; wire sm_reset_rx_cdr_to_sat_i_5_n_0; wire sm_reset_rx_cdr_to_sat_i_6_n_0; wire sm_reset_rx_pll_timer_clr_i_1_n_0; wire sm_reset_rx_pll_timer_clr_reg_n_0; wire \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ; wire \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0 ; wire \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 ; wire [9:0]sm_reset_rx_pll_timer_ctr_reg; wire sm_reset_rx_pll_timer_sat; wire sm_reset_rx_pll_timer_sat_i_1_n_0; wire sm_reset_rx_pll_timer_sat_i_2_n_0; wire sm_reset_rx_pll_timer_sat_i_3_n_0; wire sm_reset_rx_timer_clr_reg_n_0; wire [2:0]sm_reset_rx_timer_ctr; wire sm_reset_rx_timer_ctr0_n_0; wire \sm_reset_rx_timer_ctr[0]_i_1_n_0 ; wire \sm_reset_rx_timer_ctr[1]_i_1_n_0 ; wire \sm_reset_rx_timer_ctr[2]_i_1_n_0 ; wire sm_reset_rx_timer_sat; wire sm_reset_rx_timer_sat_i_1_n_0; wire [2:0]sm_reset_tx; wire [2:0]sm_reset_tx__0; wire sm_reset_tx_pll_timer_clr_i_1_n_0; wire sm_reset_tx_pll_timer_clr_reg_n_0; wire \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0 ; wire \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 ; wire [9:0]sm_reset_tx_pll_timer_ctr_reg; wire sm_reset_tx_pll_timer_sat; wire sm_reset_tx_pll_timer_sat_i_1_n_0; wire sm_reset_tx_pll_timer_sat_i_2_n_0; wire sm_reset_tx_pll_timer_sat_i_3_n_0; wire sm_reset_tx_timer_clr_reg_n_0; wire [2:0]sm_reset_tx_timer_ctr; wire sm_reset_tx_timer_sat; wire sm_reset_tx_timer_sat_i_1_n_0; wire txuserrdy_out_i_3_n_0; wire [7:1]\NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_CO_UNCONNECTED ; wire [7:2]\NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_O_UNCONNECTED ; LUT6 #( .INIT(64'h00FFF70000FFFFFF)) \FSM_sequential_sm_reset_all[0]_i_1 (.I0(gtwiz_reset_rx_done_int_reg_n_0), .I1(sm_reset_all_timer_sat), .I2(sm_reset_all_timer_clr_reg_n_0), .I3(sm_reset_all[2]), .I4(sm_reset_all[1]), .I5(sm_reset_all[0]), .O(sm_reset_all__0[0])); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT3 #( .INIT(8'h34)) \FSM_sequential_sm_reset_all[1]_i_1 (.I0(sm_reset_all[2]), .I1(sm_reset_all[1]), .I2(sm_reset_all[0]), .O(sm_reset_all__0[1])); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT3 #( .INIT(8'h4A)) \FSM_sequential_sm_reset_all[2]_i_2 (.I0(sm_reset_all[2]), .I1(sm_reset_all[0]), .I2(sm_reset_all[1]), .O(sm_reset_all__0[2])); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT3 #( .INIT(8'h08)) \FSM_sequential_sm_reset_all[2]_i_3 (.I0(sm_reset_all_timer_sat), .I1(gtwiz_reset_rx_done_int_reg_n_0), .I2(sm_reset_all_timer_clr_reg_n_0), .O(\FSM_sequential_sm_reset_all[2]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT3 #( .INIT(8'h40)) \FSM_sequential_sm_reset_all[2]_i_4 (.I0(sm_reset_all_timer_clr_reg_n_0), .I1(sm_reset_all_timer_sat), .I2(gtwiz_reset_tx_done_int_reg_n_0), .O(\FSM_sequential_sm_reset_all[2]_i_4_n_0 )); (* FSM_ENCODED_STATES = "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110" *) FDRE #( .INIT(1'b1)) \FSM_sequential_sm_reset_all_reg[0] (.C(drpclk_in), .CE(bit_synchronizer_gtpowergood_inst_n_0), .D(sm_reset_all__0[0]), .Q(sm_reset_all[0]), .R(gtwiz_reset_all_sync)); (* FSM_ENCODED_STATES = "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110" *) FDRE #( .INIT(1'b1)) \FSM_sequential_sm_reset_all_reg[1] (.C(drpclk_in), .CE(bit_synchronizer_gtpowergood_inst_n_0), .D(sm_reset_all__0[1]), .Q(sm_reset_all[1]), .R(gtwiz_reset_all_sync)); (* FSM_ENCODED_STATES = "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110" *) FDRE #( .INIT(1'b1)) \FSM_sequential_sm_reset_all_reg[2] (.C(drpclk_in), .CE(bit_synchronizer_gtpowergood_inst_n_0), .D(sm_reset_all__0[2]), .Q(sm_reset_all[2]), .R(gtwiz_reset_all_sync)); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT2 #( .INIT(4'h2)) \FSM_sequential_sm_reset_rx[1]_i_2 (.I0(sm_reset_rx_timer_sat), .I1(sm_reset_rx_timer_clr_reg_n_0), .O(\FSM_sequential_sm_reset_rx[1]_i_2_n_0 )); LUT6 #( .INIT(64'hDDFD8888DDDD8888)) \FSM_sequential_sm_reset_rx[2]_i_2 (.I0(sm_reset_rx[1]), .I1(sm_reset_rx[0]), .I2(sm_reset_rx_timer_sat), .I3(sm_reset_rx_timer_clr_reg_n_0), .I4(sm_reset_rx[2]), .I5(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .O(sm_reset_rx__0[2])); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT5 #( .INIT(32'h00004000)) \FSM_sequential_sm_reset_rx[2]_i_6 (.I0(sm_reset_rx[0]), .I1(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I2(sm_reset_rx[1]), .I3(sm_reset_rx_timer_sat), .I4(sm_reset_rx_timer_clr_reg_n_0), .O(\FSM_sequential_sm_reset_rx[2]_i_6_n_0 )); (* FSM_ENCODED_STATES = "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_rx_reg[0] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2), .D(sm_reset_rx__0[0]), .Q(sm_reset_rx[0]), .R(gtwiz_reset_rx_any_sync)); (* FSM_ENCODED_STATES = "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_rx_reg[1] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2), .D(sm_reset_rx__0[1]), .Q(sm_reset_rx[1]), .R(gtwiz_reset_rx_any_sync)); (* FSM_ENCODED_STATES = "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_rx_reg[2] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2), .D(sm_reset_rx__0[2]), .Q(sm_reset_rx[2]), .R(gtwiz_reset_rx_any_sync)); (* SOFT_HLUTNM = "soft_lutpair50" *) LUT3 #( .INIT(8'h38)) \FSM_sequential_sm_reset_tx[2]_i_2 (.I0(sm_reset_tx[0]), .I1(sm_reset_tx[1]), .I2(sm_reset_tx[2]), .O(sm_reset_tx__0[2])); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT2 #( .INIT(4'hE)) \FSM_sequential_sm_reset_tx[2]_i_3 (.I0(sm_reset_tx[1]), .I1(sm_reset_tx[2]), .O(\FSM_sequential_sm_reset_tx[2]_i_3_n_0 )); (* FSM_ENCODED_STATES = "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_tx_reg[0] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0), .D(sm_reset_tx__0[0]), .Q(sm_reset_tx[0]), .R(gtwiz_reset_tx_any_sync)); (* FSM_ENCODED_STATES = "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_tx_reg[1] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0), .D(sm_reset_tx__0[1]), .Q(sm_reset_tx[1]), .R(gtwiz_reset_tx_any_sync)); (* FSM_ENCODED_STATES = "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_tx_reg[2] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0), .D(sm_reset_tx__0[2]), .Q(sm_reset_tx[2]), .R(gtwiz_reset_tx_any_sync)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_4 bit_synchronizer_gtpowergood_inst (.E(bit_synchronizer_gtpowergood_inst_n_0), .\FSM_sequential_sm_reset_all_reg[0] (\FSM_sequential_sm_reset_all[2]_i_3_n_0 ), .\FSM_sequential_sm_reset_all_reg[0]_0 (\FSM_sequential_sm_reset_all[2]_i_4_n_0 ), .Q(sm_reset_all), .drpclk_in(drpclk_in), .gtpowergood_out(gtpowergood_out)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_5 bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst (.drpclk_in(drpclk_in), .gtwiz_reset_rx_datapath_dly(gtwiz_reset_rx_datapath_dly), .in0(gtwiz_reset_rx_datapath_sync)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_6 bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst (.D(sm_reset_rx__0[1:0]), .\FSM_sequential_sm_reset_rx_reg[0] (\FSM_sequential_sm_reset_rx[1]_i_2_n_0 ), .\FSM_sequential_sm_reset_rx_reg[0]_0 (\FSM_sequential_sm_reset_rx[2]_i_6_n_0 ), .Q(sm_reset_rx), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .gtwiz_reset_rx_datapath_dly(gtwiz_reset_rx_datapath_dly), .i_in_out_reg_0(bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst_n_2), .in0(gtwiz_reset_rx_pll_and_datapath_sync)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_7 bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst (.E(bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0), .\FSM_sequential_sm_reset_tx_reg[0] (\FSM_sequential_sm_reset_tx[2]_i_3_n_0 ), .\FSM_sequential_sm_reset_tx_reg[0]_0 (bit_synchronizer_plllock_tx_inst_n_2), .\FSM_sequential_sm_reset_tx_reg[0]_1 (bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2), .Q(sm_reset_tx[0]), .drpclk_in(drpclk_in), .gtwiz_reset_tx_pll_and_datapath_dly(gtwiz_reset_tx_pll_and_datapath_dly), .in0(gtwiz_reset_tx_datapath_sync)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_8 bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst (.D(sm_reset_tx__0[1:0]), .Q(sm_reset_tx), .drpclk_in(drpclk_in), .gtwiz_reset_tx_pll_and_datapath_dly(gtwiz_reset_tx_pll_and_datapath_dly), .in0(gtwiz_reset_tx_pll_and_datapath_sync)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_9 bit_synchronizer_gtwiz_reset_userclk_rx_active_inst (.E(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2), .\FSM_sequential_sm_reset_rx_reg[0] (bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0), .\FSM_sequential_sm_reset_rx_reg[0]_0 (bit_synchronizer_rxcdrlock_inst_n_1), .\FSM_sequential_sm_reset_rx_reg[0]_1 (bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst_n_2), .\FSM_sequential_sm_reset_rx_reg[0]_2 (sm_reset_rx_pll_timer_clr_reg_n_0), .\FSM_sequential_sm_reset_rx_reg[2] (bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1), .Q(sm_reset_rx), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.rxuserrdy_int (\gen_gtwizard_gthe3.rxuserrdy_int ), .gtwiz_reset_rx_any_sync(gtwiz_reset_rx_any_sync), .rxpmaresetdone_out(rxpmaresetdone_out), .sm_reset_rx_pll_timer_sat(sm_reset_rx_pll_timer_sat), .sm_reset_rx_timer_clr_reg(bit_synchronizer_plllock_rx_inst_n_2), .sm_reset_rx_timer_clr_reg_0(sm_reset_rx_timer_clr_reg_n_0), .sm_reset_rx_timer_sat(sm_reset_rx_timer_sat)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_10 bit_synchronizer_gtwiz_reset_userclk_tx_active_inst (.\FSM_sequential_sm_reset_tx_reg[0] (txuserrdy_out_i_3_n_0), .\FSM_sequential_sm_reset_tx_reg[0]_0 (\FSM_sequential_sm_reset_tx[2]_i_3_n_0 ), .\FSM_sequential_sm_reset_tx_reg[0]_1 (sm_reset_tx_pll_timer_clr_reg_n_0), .\FSM_sequential_sm_reset_tx_reg[2] (bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1), .Q(sm_reset_tx), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .gtwiz_reset_userclk_tx_active_sync(gtwiz_reset_userclk_tx_active_sync), .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in), .i_in_out_reg_0(bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2), .plllock_tx_sync(plllock_tx_sync), .sm_reset_tx_pll_timer_sat(sm_reset_tx_pll_timer_sat), .sm_reset_tx_timer_clr_reg(sm_reset_tx_timer_clr_reg_n_0), .sm_reset_tx_timer_clr_reg_0(gttxreset_out_i_3_n_0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_11 bit_synchronizer_plllock_rx_inst (.\FSM_sequential_sm_reset_rx_reg[1] (bit_synchronizer_plllock_rx_inst_n_2), .Q(sm_reset_rx), .cplllock_out(cplllock_out), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .gtwiz_reset_rx_done_int_reg(\FSM_sequential_sm_reset_rx[1]_i_2_n_0 ), .gtwiz_reset_rx_done_int_reg_0(gtwiz_reset_rx_done_int_reg_n_0), .i_in_out_reg_0(bit_synchronizer_plllock_rx_inst_n_1), .plllock_rx_sync(plllock_rx_sync)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_12 bit_synchronizer_plllock_tx_inst (.\FSM_sequential_sm_reset_tx_reg[0] (gttxreset_out_i_3_n_0), .Q(sm_reset_tx), .cplllock_out(cplllock_out), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .gtwiz_reset_tx_done_int_reg(bit_synchronizer_plllock_tx_inst_n_1), .gtwiz_reset_tx_done_int_reg_0(gtwiz_reset_tx_done_int_reg_n_0), .gtwiz_reset_tx_done_int_reg_1(sm_reset_tx_timer_clr_reg_n_0), .i_in_out_reg_0(bit_synchronizer_plllock_tx_inst_n_2), .plllock_tx_sync(plllock_tx_sync), .sm_reset_tx_timer_sat(sm_reset_tx_timer_sat)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_bit_synchronizer_13 bit_synchronizer_rxcdrlock_inst (.\FSM_sequential_sm_reset_rx_reg[0] (\FSM_sequential_sm_reset_rx[1]_i_2_n_0 ), .\FSM_sequential_sm_reset_rx_reg[1] (bit_synchronizer_rxcdrlock_inst_n_1), .\FSM_sequential_sm_reset_rx_reg[2] (bit_synchronizer_rxcdrlock_inst_n_0), .Q(sm_reset_rx), .drpclk_in(drpclk_in), .plllock_rx_sync(plllock_rx_sync), .rxcdrlock_out(rxcdrlock_out), .sm_reset_rx_cdr_to_clr(sm_reset_rx_cdr_to_clr), .sm_reset_rx_cdr_to_clr_reg(sm_reset_rx_cdr_to_clr_i_3_n_0), .sm_reset_rx_cdr_to_sat(sm_reset_rx_cdr_to_sat), .sm_reset_rx_cdr_to_sat_reg(bit_synchronizer_rxcdrlock_inst_n_2)); LUT2 #( .INIT(4'hE)) \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_i_1 (.I0(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ), .I1(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ), .O(\gen_gtwizard_gthe3.cpllpd_ch_int )); FDRE #( .INIT(1'b1)) gtrxreset_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_rx_any_inst_n_3), .Q(\gen_gtwizard_gthe3.gtrxreset_int ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT2 #( .INIT(4'h2)) gttxreset_out_i_3 (.I0(sm_reset_tx_timer_sat), .I1(sm_reset_tx_timer_clr_reg_n_0), .O(gttxreset_out_i_3_n_0)); FDRE #( .INIT(1'b1)) gttxreset_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_tx_any_inst_n_2), .Q(\gen_gtwizard_gthe3.gttxreset_int ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair51" *) LUT4 #( .INIT(16'hF740)) gtwiz_reset_rx_datapath_int_i_1 (.I0(sm_reset_all[2]), .I1(sm_reset_all[0]), .I2(sm_reset_all[1]), .I3(gtwiz_reset_rx_datapath_int_reg_n_0), .O(gtwiz_reset_rx_datapath_int_i_1_n_0)); FDRE #( .INIT(1'b0)) gtwiz_reset_rx_datapath_int_reg (.C(drpclk_in), .CE(1'b1), .D(gtwiz_reset_rx_datapath_int_i_1_n_0), .Q(gtwiz_reset_rx_datapath_int_reg_n_0), .R(gtwiz_reset_all_sync)); FDRE #( .INIT(1'b0)) gtwiz_reset_rx_done_int_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_plllock_rx_inst_n_1), .Q(gtwiz_reset_rx_done_int_reg_n_0), .R(gtwiz_reset_rx_any_sync)); LUT4 #( .INIT(16'hF704)) gtwiz_reset_rx_pll_and_datapath_int_i_1 (.I0(sm_reset_all[0]), .I1(sm_reset_all[2]), .I2(sm_reset_all[1]), .I3(gtwiz_reset_rx_pll_and_datapath_int_reg_n_0), .O(gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0)); FDRE #( .INIT(1'b0)) gtwiz_reset_rx_pll_and_datapath_int_reg (.C(drpclk_in), .CE(1'b1), .D(gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0), .Q(gtwiz_reset_rx_pll_and_datapath_int_reg_n_0), .R(gtwiz_reset_all_sync)); FDRE #( .INIT(1'b0)) gtwiz_reset_tx_done_int_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_plllock_tx_inst_n_1), .Q(gtwiz_reset_tx_done_int_reg_n_0), .R(gtwiz_reset_tx_any_sync)); (* SOFT_HLUTNM = "soft_lutpair51" *) LUT4 #( .INIT(16'hFB02)) gtwiz_reset_tx_pll_and_datapath_int_i_1 (.I0(sm_reset_all[0]), .I1(sm_reset_all[1]), .I2(sm_reset_all[2]), .I3(gtwiz_reset_tx_pll_and_datapath_int_reg_n_0), .O(gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0)); FDRE #( .INIT(1'b0)) gtwiz_reset_tx_pll_and_datapath_int_reg (.C(drpclk_in), .CE(1'b1), .D(gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0), .Q(gtwiz_reset_tx_pll_and_datapath_int_reg_n_0), .R(gtwiz_reset_all_sync)); FDRE #( .INIT(1'b0)) pllreset_rx_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_rx_any_inst_n_1), .Q(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ), .R(1'b0)); FDRE #( .INIT(1'b1)) pllreset_tx_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_tx_any_inst_n_1), .Q(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ), .R(1'b0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_gtwiz_reset_all_inst (.drpclk_in(drpclk_in), .gtwiz_reset_all_in(gtwiz_reset_all_in), .gtwiz_reset_all_sync(gtwiz_reset_all_sync)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_14 reset_synchronizer_gtwiz_reset_rx_any_inst (.\FSM_sequential_sm_reset_rx_reg[1] (reset_synchronizer_gtwiz_reset_rx_any_inst_n_1), .\FSM_sequential_sm_reset_rx_reg[1]_0 (reset_synchronizer_gtwiz_reset_rx_any_inst_n_2), .\FSM_sequential_sm_reset_rx_reg[1]_1 (reset_synchronizer_gtwiz_reset_rx_any_inst_n_3), .Q(sm_reset_rx), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ), .\gen_gtwizard_gthe3.gtrxreset_int (\gen_gtwizard_gthe3.gtrxreset_int ), .\gen_gtwizard_gthe3.rxprogdivreset_int (\gen_gtwizard_gthe3.rxprogdivreset_int ), .gtrxreset_out_reg(\FSM_sequential_sm_reset_rx[1]_i_2_n_0 ), .gtwiz_reset_rx_any_sync(gtwiz_reset_rx_any_sync), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), .plllock_rx_sync(plllock_rx_sync), .rst_in_out_reg_0(gtwiz_reset_rx_datapath_int_reg_n_0), .rst_in_out_reg_1(gtwiz_reset_rx_pll_and_datapath_int_reg_n_0), .rxprogdivreset_out_reg(bit_synchronizer_rxcdrlock_inst_n_2)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_15 reset_synchronizer_gtwiz_reset_rx_datapath_inst (.drpclk_in(drpclk_in), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), .in0(gtwiz_reset_rx_datapath_sync), .rst_in_out_reg_0(gtwiz_reset_rx_datapath_int_reg_n_0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_16 reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst (.drpclk_in(drpclk_in), .in0(gtwiz_reset_rx_pll_and_datapath_sync), .rst_in_meta_reg_0(gtwiz_reset_rx_pll_and_datapath_int_reg_n_0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_17 reset_synchronizer_gtwiz_reset_tx_any_inst (.\FSM_sequential_sm_reset_tx_reg[0] (reset_synchronizer_gtwiz_reset_tx_any_inst_n_3), .\FSM_sequential_sm_reset_tx_reg[1] (reset_synchronizer_gtwiz_reset_tx_any_inst_n_1), .\FSM_sequential_sm_reset_tx_reg[1]_0 (reset_synchronizer_gtwiz_reset_tx_any_inst_n_2), .Q(sm_reset_tx), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ), .\gen_gtwizard_gthe3.gttxreset_int (\gen_gtwizard_gthe3.gttxreset_int ), .\gen_gtwizard_gthe3.txuserrdy_int (\gen_gtwizard_gthe3.txuserrdy_int ), .gttxreset_out_reg(gttxreset_out_i_3_n_0), .gtwiz_reset_tx_any_sync(gtwiz_reset_tx_any_sync), .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in), .gtwiz_reset_userclk_tx_active_sync(gtwiz_reset_userclk_tx_active_sync), .plllock_tx_sync(plllock_tx_sync), .rst_in_out_reg_0(gtwiz_reset_tx_pll_and_datapath_int_reg_n_0), .txuserrdy_out_reg(txuserrdy_out_i_3_n_0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_18 reset_synchronizer_gtwiz_reset_tx_datapath_inst (.drpclk_in(drpclk_in), .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in), .in0(gtwiz_reset_tx_datapath_sync)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_19 reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst (.drpclk_in(drpclk_in), .in0(gtwiz_reset_tx_pll_and_datapath_sync), .rst_in_meta_reg_0(gtwiz_reset_tx_pll_and_datapath_int_reg_n_0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer reset_synchronizer_rx_done_inst (.gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out), .rst_in_sync2_reg_0(gtwiz_reset_rx_done_int_reg_n_0), .rxusrclk_in(rxusrclk_in)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer_20 reset_synchronizer_tx_done_inst (.gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out), .rst_in_sync2_reg_0(gtwiz_reset_tx_done_int_reg_n_0), .rxusrclk_in(rxusrclk_in)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_21 reset_synchronizer_txprogdivreset_inst (.drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.txprogdivreset_int (\gen_gtwizard_gthe3.txprogdivreset_int ), .rst_in0(rst_in0)); FDRE #( .INIT(1'b1)) rxprogdivreset_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_rx_any_inst_n_2), .Q(\gen_gtwizard_gthe3.rxprogdivreset_int ), .R(1'b0)); FDRE #( .INIT(1'b0)) rxuserrdy_out_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1), .Q(\gen_gtwizard_gthe3.rxuserrdy_int ), .R(1'b0)); LUT5 #( .INIT(32'hEFFA200A)) sm_reset_all_timer_clr_i_1 (.I0(sm_reset_all_timer_clr_i_2_n_0), .I1(sm_reset_all[1]), .I2(sm_reset_all[2]), .I3(sm_reset_all[0]), .I4(sm_reset_all_timer_clr_reg_n_0), .O(sm_reset_all_timer_clr_i_1_n_0)); LUT6 #( .INIT(64'h0000B0003333BB33)) sm_reset_all_timer_clr_i_2 (.I0(gtwiz_reset_rx_done_int_reg_n_0), .I1(sm_reset_all[2]), .I2(gtwiz_reset_tx_done_int_reg_n_0), .I3(sm_reset_all_timer_sat), .I4(sm_reset_all_timer_clr_reg_n_0), .I5(sm_reset_all[1]), .O(sm_reset_all_timer_clr_i_2_n_0)); FDSE #( .INIT(1'b1)) sm_reset_all_timer_clr_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_all_timer_clr_i_1_n_0), .Q(sm_reset_all_timer_clr_reg_n_0), .S(gtwiz_reset_all_sync)); LUT3 #( .INIT(8'h7F)) sm_reset_all_timer_ctr0 (.I0(sm_reset_all_timer_ctr[2]), .I1(sm_reset_all_timer_ctr[0]), .I2(sm_reset_all_timer_ctr[1]), .O(sm_reset_all_timer_ctr0_n_0)); LUT1 #( .INIT(2'h1)) \sm_reset_all_timer_ctr[0]_i_1 (.I0(sm_reset_all_timer_ctr[0]), .O(\sm_reset_all_timer_ctr[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT2 #( .INIT(4'h6)) \sm_reset_all_timer_ctr[1]_i_1 (.I0(sm_reset_all_timer_ctr[0]), .I1(sm_reset_all_timer_ctr[1]), .O(\sm_reset_all_timer_ctr[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT3 #( .INIT(8'h78)) \sm_reset_all_timer_ctr[2]_i_1 (.I0(sm_reset_all_timer_ctr[0]), .I1(sm_reset_all_timer_ctr[1]), .I2(sm_reset_all_timer_ctr[2]), .O(\sm_reset_all_timer_ctr[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \sm_reset_all_timer_ctr_reg[0] (.C(drpclk_in), .CE(sm_reset_all_timer_ctr0_n_0), .D(\sm_reset_all_timer_ctr[0]_i_1_n_0 ), .Q(sm_reset_all_timer_ctr[0]), .R(sm_reset_all_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_all_timer_ctr_reg[1] (.C(drpclk_in), .CE(sm_reset_all_timer_ctr0_n_0), .D(\sm_reset_all_timer_ctr[1]_i_1_n_0 ), .Q(sm_reset_all_timer_ctr[1]), .R(sm_reset_all_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_all_timer_ctr_reg[2] (.C(drpclk_in), .CE(sm_reset_all_timer_ctr0_n_0), .D(\sm_reset_all_timer_ctr[2]_i_1_n_0 ), .Q(sm_reset_all_timer_ctr[2]), .R(sm_reset_all_timer_clr_reg_n_0)); LUT5 #( .INIT(32'h0000FF80)) sm_reset_all_timer_sat_i_1 (.I0(sm_reset_all_timer_ctr[2]), .I1(sm_reset_all_timer_ctr[0]), .I2(sm_reset_all_timer_ctr[1]), .I3(sm_reset_all_timer_sat), .I4(sm_reset_all_timer_clr_reg_n_0), .O(sm_reset_all_timer_sat_i_1_n_0)); FDRE #( .INIT(1'b0)) sm_reset_all_timer_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_all_timer_sat_i_1_n_0), .Q(sm_reset_all_timer_sat), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT3 #( .INIT(8'h40)) sm_reset_rx_cdr_to_clr_i_3 (.I0(sm_reset_rx_timer_clr_reg_n_0), .I1(sm_reset_rx_timer_sat), .I2(sm_reset_rx[1]), .O(sm_reset_rx_cdr_to_clr_i_3_n_0)); FDSE #( .INIT(1'b1)) sm_reset_rx_cdr_to_clr_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_rxcdrlock_inst_n_0), .Q(sm_reset_rx_cdr_to_clr), .S(gtwiz_reset_rx_any_sync)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \sm_reset_rx_cdr_to_ctr[0]_i_1 (.I0(sm_reset_rx_cdr_to_ctr_reg[0]), .I1(sm_reset_rx_cdr_to_ctr_reg[1]), .I2(\sm_reset_rx_cdr_to_ctr[0]_i_3_n_0 ), .I3(\sm_reset_rx_cdr_to_ctr[0]_i_4_n_0 ), .I4(\sm_reset_rx_cdr_to_ctr[0]_i_5_n_0 ), .I5(\sm_reset_rx_cdr_to_ctr[0]_i_6_n_0 ), .O(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFDFFFFFFFFF)) \sm_reset_rx_cdr_to_ctr[0]_i_3 (.I0(sm_reset_rx_cdr_to_ctr_reg[18]), .I1(sm_reset_rx_cdr_to_ctr_reg[19]), .I2(sm_reset_rx_cdr_to_ctr_reg[17]), .I3(sm_reset_rx_cdr_to_ctr_reg[16]), .I4(sm_reset_rx_cdr_to_ctr_reg[14]), .I5(sm_reset_rx_cdr_to_ctr_reg[15]), .O(\sm_reset_rx_cdr_to_ctr[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFEFFFFFFFF)) \sm_reset_rx_cdr_to_ctr[0]_i_4 (.I0(sm_reset_rx_cdr_to_ctr_reg[24]), .I1(sm_reset_rx_cdr_to_ctr_reg[25]), .I2(sm_reset_rx_cdr_to_ctr_reg[22]), .I3(sm_reset_rx_cdr_to_ctr_reg[23]), .I4(sm_reset_rx_cdr_to_ctr_reg[21]), .I5(sm_reset_rx_cdr_to_ctr_reg[20]), .O(\sm_reset_rx_cdr_to_ctr[0]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFDFFFFFFFFF)) \sm_reset_rx_cdr_to_ctr[0]_i_5 (.I0(sm_reset_rx_cdr_to_ctr_reg[12]), .I1(sm_reset_rx_cdr_to_ctr_reg[13]), .I2(sm_reset_rx_cdr_to_ctr_reg[10]), .I3(sm_reset_rx_cdr_to_ctr_reg[11]), .I4(sm_reset_rx_cdr_to_ctr_reg[9]), .I5(sm_reset_rx_cdr_to_ctr_reg[8]), .O(\sm_reset_rx_cdr_to_ctr[0]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFD)) \sm_reset_rx_cdr_to_ctr[0]_i_6 (.I0(sm_reset_rx_cdr_to_ctr_reg[6]), .I1(sm_reset_rx_cdr_to_ctr_reg[7]), .I2(sm_reset_rx_cdr_to_ctr_reg[4]), .I3(sm_reset_rx_cdr_to_ctr_reg[5]), .I4(sm_reset_rx_cdr_to_ctr_reg[3]), .I5(sm_reset_rx_cdr_to_ctr_reg[2]), .O(\sm_reset_rx_cdr_to_ctr[0]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \sm_reset_rx_cdr_to_ctr[0]_i_7 (.I0(sm_reset_rx_cdr_to_ctr_reg[0]), .O(\sm_reset_rx_cdr_to_ctr[0]_i_7_n_0 )); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[0] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15 ), .Q(sm_reset_rx_cdr_to_ctr_reg[0]), .R(sm_reset_rx_cdr_to_clr)); (* ADDER_THRESHOLD = "16" *) CARRY8 \sm_reset_rx_cdr_to_ctr_reg[0]_i_2 (.CI(1'b0), .CI_TOP(1'b0), .CO({\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_1 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_2 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_3 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_4 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_5 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_6 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}), .O({\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15 }), .S({sm_reset_rx_cdr_to_ctr_reg[7:1],\sm_reset_rx_cdr_to_ctr[0]_i_7_n_0 })); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[10] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13 ), .Q(sm_reset_rx_cdr_to_ctr_reg[10]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[11] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12 ), .Q(sm_reset_rx_cdr_to_ctr_reg[11]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[12] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11 ), .Q(sm_reset_rx_cdr_to_ctr_reg[12]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[13] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10 ), .Q(sm_reset_rx_cdr_to_ctr_reg[13]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[14] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9 ), .Q(sm_reset_rx_cdr_to_ctr_reg[14]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[15] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8 ), .Q(sm_reset_rx_cdr_to_ctr_reg[15]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[16] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15 ), .Q(sm_reset_rx_cdr_to_ctr_reg[16]), .R(sm_reset_rx_cdr_to_clr)); (* ADDER_THRESHOLD = "16" *) CARRY8 \sm_reset_rx_cdr_to_ctr_reg[16]_i_1 (.CI(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0 ), .CI_TOP(1'b0), .CO({\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_1 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_2 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_3 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_4 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_5 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_6 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15 }), .S(sm_reset_rx_cdr_to_ctr_reg[23:16])); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[17] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14 ), .Q(sm_reset_rx_cdr_to_ctr_reg[17]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[18] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13 ), .Q(sm_reset_rx_cdr_to_ctr_reg[18]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[19] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12 ), .Q(sm_reset_rx_cdr_to_ctr_reg[19]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[1] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14 ), .Q(sm_reset_rx_cdr_to_ctr_reg[1]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[20] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11 ), .Q(sm_reset_rx_cdr_to_ctr_reg[20]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[21] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10 ), .Q(sm_reset_rx_cdr_to_ctr_reg[21]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[22] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9 ), .Q(sm_reset_rx_cdr_to_ctr_reg[22]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[23] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8 ), .Q(sm_reset_rx_cdr_to_ctr_reg[23]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[24] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15 ), .Q(sm_reset_rx_cdr_to_ctr_reg[24]), .R(sm_reset_rx_cdr_to_clr)); (* ADDER_THRESHOLD = "16" *) CARRY8 \sm_reset_rx_cdr_to_ctr_reg[24]_i_1 (.CI(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0 ), .CI_TOP(1'b0), .CO({\NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_CO_UNCONNECTED [7:1],\sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_O_UNCONNECTED [7:2],\sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14 ,\sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15 }), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,sm_reset_rx_cdr_to_ctr_reg[25:24]})); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[25] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14 ), .Q(sm_reset_rx_cdr_to_ctr_reg[25]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[2] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13 ), .Q(sm_reset_rx_cdr_to_ctr_reg[2]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[3] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12 ), .Q(sm_reset_rx_cdr_to_ctr_reg[3]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[4] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11 ), .Q(sm_reset_rx_cdr_to_ctr_reg[4]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[5] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10 ), .Q(sm_reset_rx_cdr_to_ctr_reg[5]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[6] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9 ), .Q(sm_reset_rx_cdr_to_ctr_reg[6]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[7] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8 ), .Q(sm_reset_rx_cdr_to_ctr_reg[7]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[8] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15 ), .Q(sm_reset_rx_cdr_to_ctr_reg[8]), .R(sm_reset_rx_cdr_to_clr)); (* ADDER_THRESHOLD = "16" *) CARRY8 \sm_reset_rx_cdr_to_ctr_reg[8]_i_1 (.CI(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0 ), .CI_TOP(1'b0), .CO({\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_1 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_2 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_3 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_4 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_5 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_6 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15 }), .S(sm_reset_rx_cdr_to_ctr_reg[15:8])); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[9] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14 ), .Q(sm_reset_rx_cdr_to_ctr_reg[9]), .R(sm_reset_rx_cdr_to_clr)); LUT3 #( .INIT(8'h0E)) sm_reset_rx_cdr_to_sat_i_1 (.I0(sm_reset_rx_cdr_to_sat), .I1(sm_reset_rx_cdr_to_sat_i_2_n_0), .I2(sm_reset_rx_cdr_to_clr), .O(sm_reset_rx_cdr_to_sat_i_1_n_0)); LUT6 #( .INIT(64'h0000000000008000)) sm_reset_rx_cdr_to_sat_i_2 (.I0(sm_reset_rx_cdr_to_sat_i_3_n_0), .I1(sm_reset_rx_cdr_to_sat_i_4_n_0), .I2(sm_reset_rx_cdr_to_sat_i_5_n_0), .I3(sm_reset_rx_cdr_to_sat_i_6_n_0), .I4(sm_reset_rx_cdr_to_ctr_reg[0]), .I5(sm_reset_rx_cdr_to_ctr_reg[1]), .O(sm_reset_rx_cdr_to_sat_i_2_n_0)); LUT6 #( .INIT(64'h0000000100000000)) sm_reset_rx_cdr_to_sat_i_3 (.I0(sm_reset_rx_cdr_to_ctr_reg[4]), .I1(sm_reset_rx_cdr_to_ctr_reg[5]), .I2(sm_reset_rx_cdr_to_ctr_reg[2]), .I3(sm_reset_rx_cdr_to_ctr_reg[3]), .I4(sm_reset_rx_cdr_to_ctr_reg[7]), .I5(sm_reset_rx_cdr_to_ctr_reg[6]), .O(sm_reset_rx_cdr_to_sat_i_3_n_0)); LUT6 #( .INIT(64'h0000000000000010)) sm_reset_rx_cdr_to_sat_i_4 (.I0(sm_reset_rx_cdr_to_ctr_reg[22]), .I1(sm_reset_rx_cdr_to_ctr_reg[23]), .I2(sm_reset_rx_cdr_to_ctr_reg[20]), .I3(sm_reset_rx_cdr_to_ctr_reg[21]), .I4(sm_reset_rx_cdr_to_ctr_reg[25]), .I5(sm_reset_rx_cdr_to_ctr_reg[24]), .O(sm_reset_rx_cdr_to_sat_i_4_n_0)); LUT6 #( .INIT(64'h0000002000000000)) sm_reset_rx_cdr_to_sat_i_5 (.I0(sm_reset_rx_cdr_to_ctr_reg[17]), .I1(sm_reset_rx_cdr_to_ctr_reg[16]), .I2(sm_reset_rx_cdr_to_ctr_reg[15]), .I3(sm_reset_rx_cdr_to_ctr_reg[14]), .I4(sm_reset_rx_cdr_to_ctr_reg[19]), .I5(sm_reset_rx_cdr_to_ctr_reg[18]), .O(sm_reset_rx_cdr_to_sat_i_5_n_0)); LUT6 #( .INIT(64'h0000002000000000)) sm_reset_rx_cdr_to_sat_i_6 (.I0(sm_reset_rx_cdr_to_ctr_reg[10]), .I1(sm_reset_rx_cdr_to_ctr_reg[11]), .I2(sm_reset_rx_cdr_to_ctr_reg[8]), .I3(sm_reset_rx_cdr_to_ctr_reg[9]), .I4(sm_reset_rx_cdr_to_ctr_reg[13]), .I5(sm_reset_rx_cdr_to_ctr_reg[12]), .O(sm_reset_rx_cdr_to_sat_i_6_n_0)); FDRE #( .INIT(1'b0)) sm_reset_rx_cdr_to_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_rx_cdr_to_sat_i_1_n_0), .Q(sm_reset_rx_cdr_to_sat), .R(1'b0)); LUT5 #( .INIT(32'hFFF3000B)) sm_reset_rx_pll_timer_clr_i_1 (.I0(sm_reset_rx_pll_timer_sat), .I1(sm_reset_rx[0]), .I2(sm_reset_rx[1]), .I3(sm_reset_rx[2]), .I4(sm_reset_rx_pll_timer_clr_reg_n_0), .O(sm_reset_rx_pll_timer_clr_i_1_n_0)); FDSE #( .INIT(1'b1)) sm_reset_rx_pll_timer_clr_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_rx_pll_timer_clr_i_1_n_0), .Q(sm_reset_rx_pll_timer_clr_reg_n_0), .S(gtwiz_reset_rx_any_sync)); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT1 #( .INIT(2'h1)) \sm_reset_rx_pll_timer_ctr[0]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[0]), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT2 #( .INIT(4'h6)) \sm_reset_rx_pll_timer_ctr[1]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[1]), .I1(sm_reset_rx_pll_timer_ctr_reg[0]), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT3 #( .INIT(8'h78)) \sm_reset_rx_pll_timer_ctr[2]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[1]), .I1(sm_reset_rx_pll_timer_ctr_reg[0]), .I2(sm_reset_rx_pll_timer_ctr_reg[2]), .O(p_0_in__1[2])); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT4 #( .INIT(16'h7F80)) \sm_reset_rx_pll_timer_ctr[3]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[2]), .I1(sm_reset_rx_pll_timer_ctr_reg[0]), .I2(sm_reset_rx_pll_timer_ctr_reg[1]), .I3(sm_reset_rx_pll_timer_ctr_reg[3]), .O(p_0_in__1[3])); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT5 #( .INIT(32'h7FFF8000)) \sm_reset_rx_pll_timer_ctr[4]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[3]), .I1(sm_reset_rx_pll_timer_ctr_reg[1]), .I2(sm_reset_rx_pll_timer_ctr_reg[0]), .I3(sm_reset_rx_pll_timer_ctr_reg[2]), .I4(sm_reset_rx_pll_timer_ctr_reg[4]), .O(p_0_in__1[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \sm_reset_rx_pll_timer_ctr[5]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[4]), .I1(sm_reset_rx_pll_timer_ctr_reg[2]), .I2(sm_reset_rx_pll_timer_ctr_reg[0]), .I3(sm_reset_rx_pll_timer_ctr_reg[1]), .I4(sm_reset_rx_pll_timer_ctr_reg[3]), .I5(sm_reset_rx_pll_timer_ctr_reg[5]), .O(p_0_in__1[5])); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT2 #( .INIT(4'h9)) \sm_reset_rx_pll_timer_ctr[6]_i_1 (.I0(\sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 ), .I1(sm_reset_rx_pll_timer_ctr_reg[6]), .O(p_0_in__1[6])); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT3 #( .INIT(8'hD2)) \sm_reset_rx_pll_timer_ctr[7]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[6]), .I1(\sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 ), .I2(sm_reset_rx_pll_timer_ctr_reg[7]), .O(p_0_in__1[7])); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT4 #( .INIT(16'hDF20)) \sm_reset_rx_pll_timer_ctr[8]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[7]), .I1(\sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 ), .I2(sm_reset_rx_pll_timer_ctr_reg[6]), .I3(sm_reset_rx_pll_timer_ctr_reg[8]), .O(p_0_in__1[8])); LUT5 #( .INIT(32'hFFFFFFBF)) \sm_reset_rx_pll_timer_ctr[9]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[3]), .I1(sm_reset_rx_pll_timer_ctr_reg[2]), .I2(sm_reset_rx_pll_timer_ctr_reg[1]), .I3(sm_reset_rx_pll_timer_ctr_reg[0]), .I4(\sm_reset_rx_pll_timer_ctr[9]_i_3_n_0 ), .O(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT5 #( .INIT(32'hF7FF0800)) \sm_reset_rx_pll_timer_ctr[9]_i_2 (.I0(sm_reset_rx_pll_timer_ctr_reg[8]), .I1(sm_reset_rx_pll_timer_ctr_reg[6]), .I2(\sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 ), .I3(sm_reset_rx_pll_timer_ctr_reg[7]), .I4(sm_reset_rx_pll_timer_ctr_reg[9]), .O(p_0_in__1[9])); LUT6 #( .INIT(64'hFFFFFFEFFFFFFFFF)) \sm_reset_rx_pll_timer_ctr[9]_i_3 (.I0(sm_reset_rx_pll_timer_ctr_reg[8]), .I1(sm_reset_rx_pll_timer_ctr_reg[9]), .I2(sm_reset_rx_pll_timer_ctr_reg[6]), .I3(sm_reset_rx_pll_timer_ctr_reg[7]), .I4(sm_reset_rx_pll_timer_ctr_reg[4]), .I5(sm_reset_rx_pll_timer_ctr_reg[5]), .O(\sm_reset_rx_pll_timer_ctr[9]_i_3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \sm_reset_rx_pll_timer_ctr[9]_i_4 (.I0(sm_reset_rx_pll_timer_ctr_reg[4]), .I1(sm_reset_rx_pll_timer_ctr_reg[2]), .I2(sm_reset_rx_pll_timer_ctr_reg[0]), .I3(sm_reset_rx_pll_timer_ctr_reg[1]), .I4(sm_reset_rx_pll_timer_ctr_reg[3]), .I5(sm_reset_rx_pll_timer_ctr_reg[5]), .O(\sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[0] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[0]), .Q(sm_reset_rx_pll_timer_ctr_reg[0]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[1] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[1]), .Q(sm_reset_rx_pll_timer_ctr_reg[1]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[2] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[2]), .Q(sm_reset_rx_pll_timer_ctr_reg[2]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[3] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[3]), .Q(sm_reset_rx_pll_timer_ctr_reg[3]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[4] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[4]), .Q(sm_reset_rx_pll_timer_ctr_reg[4]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[5] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[5]), .Q(sm_reset_rx_pll_timer_ctr_reg[5]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[6] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[6]), .Q(sm_reset_rx_pll_timer_ctr_reg[6]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[7] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[7]), .Q(sm_reset_rx_pll_timer_ctr_reg[7]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[8] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[8]), .Q(sm_reset_rx_pll_timer_ctr_reg[8]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[9] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[9]), .Q(sm_reset_rx_pll_timer_ctr_reg[9]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); LUT4 #( .INIT(16'h00EA)) sm_reset_rx_pll_timer_sat_i_1 (.I0(sm_reset_rx_pll_timer_sat), .I1(sm_reset_rx_pll_timer_sat_i_2_n_0), .I2(sm_reset_rx_pll_timer_sat_i_3_n_0), .I3(sm_reset_rx_pll_timer_clr_reg_n_0), .O(sm_reset_rx_pll_timer_sat_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT4 #( .INIT(16'h0040)) sm_reset_rx_pll_timer_sat_i_2 (.I0(sm_reset_rx_pll_timer_ctr_reg[3]), .I1(sm_reset_rx_pll_timer_ctr_reg[2]), .I2(sm_reset_rx_pll_timer_ctr_reg[1]), .I3(sm_reset_rx_pll_timer_ctr_reg[0]), .O(sm_reset_rx_pll_timer_sat_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000020)) sm_reset_rx_pll_timer_sat_i_3 (.I0(sm_reset_rx_pll_timer_ctr_reg[6]), .I1(sm_reset_rx_pll_timer_ctr_reg[7]), .I2(sm_reset_rx_pll_timer_ctr_reg[5]), .I3(sm_reset_rx_pll_timer_ctr_reg[4]), .I4(sm_reset_rx_pll_timer_ctr_reg[9]), .I5(sm_reset_rx_pll_timer_ctr_reg[8]), .O(sm_reset_rx_pll_timer_sat_i_3_n_0)); FDRE #( .INIT(1'b0)) sm_reset_rx_pll_timer_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_rx_pll_timer_sat_i_1_n_0), .Q(sm_reset_rx_pll_timer_sat), .R(1'b0)); FDSE #( .INIT(1'b1)) sm_reset_rx_timer_clr_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0), .Q(sm_reset_rx_timer_clr_reg_n_0), .S(gtwiz_reset_rx_any_sync)); LUT3 #( .INIT(8'h7F)) sm_reset_rx_timer_ctr0 (.I0(sm_reset_rx_timer_ctr[2]), .I1(sm_reset_rx_timer_ctr[0]), .I2(sm_reset_rx_timer_ctr[1]), .O(sm_reset_rx_timer_ctr0_n_0)); LUT1 #( .INIT(2'h1)) \sm_reset_rx_timer_ctr[0]_i_1 (.I0(sm_reset_rx_timer_ctr[0]), .O(\sm_reset_rx_timer_ctr[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT2 #( .INIT(4'h6)) \sm_reset_rx_timer_ctr[1]_i_1 (.I0(sm_reset_rx_timer_ctr[0]), .I1(sm_reset_rx_timer_ctr[1]), .O(\sm_reset_rx_timer_ctr[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT3 #( .INIT(8'h78)) \sm_reset_rx_timer_ctr[2]_i_1 (.I0(sm_reset_rx_timer_ctr[0]), .I1(sm_reset_rx_timer_ctr[1]), .I2(sm_reset_rx_timer_ctr[2]), .O(\sm_reset_rx_timer_ctr[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \sm_reset_rx_timer_ctr_reg[0] (.C(drpclk_in), .CE(sm_reset_rx_timer_ctr0_n_0), .D(\sm_reset_rx_timer_ctr[0]_i_1_n_0 ), .Q(sm_reset_rx_timer_ctr[0]), .R(sm_reset_rx_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_timer_ctr_reg[1] (.C(drpclk_in), .CE(sm_reset_rx_timer_ctr0_n_0), .D(\sm_reset_rx_timer_ctr[1]_i_1_n_0 ), .Q(sm_reset_rx_timer_ctr[1]), .R(sm_reset_rx_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_timer_ctr_reg[2] (.C(drpclk_in), .CE(sm_reset_rx_timer_ctr0_n_0), .D(\sm_reset_rx_timer_ctr[2]_i_1_n_0 ), .Q(sm_reset_rx_timer_ctr[2]), .R(sm_reset_rx_timer_clr_reg_n_0)); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT5 #( .INIT(32'h0000FF80)) sm_reset_rx_timer_sat_i_1 (.I0(sm_reset_rx_timer_ctr[2]), .I1(sm_reset_rx_timer_ctr[0]), .I2(sm_reset_rx_timer_ctr[1]), .I3(sm_reset_rx_timer_sat), .I4(sm_reset_rx_timer_clr_reg_n_0), .O(sm_reset_rx_timer_sat_i_1_n_0)); FDRE #( .INIT(1'b0)) sm_reset_rx_timer_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_rx_timer_sat_i_1_n_0), .Q(sm_reset_rx_timer_sat), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT5 #( .INIT(32'hEFEF1101)) sm_reset_tx_pll_timer_clr_i_1 (.I0(sm_reset_tx[1]), .I1(sm_reset_tx[2]), .I2(sm_reset_tx[0]), .I3(sm_reset_tx_pll_timer_sat), .I4(sm_reset_tx_pll_timer_clr_reg_n_0), .O(sm_reset_tx_pll_timer_clr_i_1_n_0)); FDSE #( .INIT(1'b1)) sm_reset_tx_pll_timer_clr_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_tx_pll_timer_clr_i_1_n_0), .Q(sm_reset_tx_pll_timer_clr_reg_n_0), .S(gtwiz_reset_tx_any_sync)); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT1 #( .INIT(2'h1)) \sm_reset_tx_pll_timer_ctr[0]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT2 #( .INIT(4'h6)) \sm_reset_tx_pll_timer_ctr[1]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[1]), .I1(sm_reset_tx_pll_timer_ctr_reg[0]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair52" *) LUT3 #( .INIT(8'h78)) \sm_reset_tx_pll_timer_ctr[2]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[1]), .I1(sm_reset_tx_pll_timer_ctr_reg[0]), .I2(sm_reset_tx_pll_timer_ctr_reg[2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair52" *) LUT4 #( .INIT(16'h7F80)) \sm_reset_tx_pll_timer_ctr[3]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[2]), .I1(sm_reset_tx_pll_timer_ctr_reg[0]), .I2(sm_reset_tx_pll_timer_ctr_reg[1]), .I3(sm_reset_tx_pll_timer_ctr_reg[3]), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT5 #( .INIT(32'h7FFF8000)) \sm_reset_tx_pll_timer_ctr[4]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[3]), .I1(sm_reset_tx_pll_timer_ctr_reg[1]), .I2(sm_reset_tx_pll_timer_ctr_reg[0]), .I3(sm_reset_tx_pll_timer_ctr_reg[2]), .I4(sm_reset_tx_pll_timer_ctr_reg[4]), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \sm_reset_tx_pll_timer_ctr[5]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[4]), .I1(sm_reset_tx_pll_timer_ctr_reg[2]), .I2(sm_reset_tx_pll_timer_ctr_reg[0]), .I3(sm_reset_tx_pll_timer_ctr_reg[1]), .I4(sm_reset_tx_pll_timer_ctr_reg[3]), .I5(sm_reset_tx_pll_timer_ctr_reg[5]), .O(p_0_in__0[5])); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT2 #( .INIT(4'h9)) \sm_reset_tx_pll_timer_ctr[6]_i_1 (.I0(\sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 ), .I1(sm_reset_tx_pll_timer_ctr_reg[6]), .O(p_0_in__0[6])); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT3 #( .INIT(8'hD2)) \sm_reset_tx_pll_timer_ctr[7]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[6]), .I1(\sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 ), .I2(sm_reset_tx_pll_timer_ctr_reg[7]), .O(p_0_in__0[7])); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT4 #( .INIT(16'hDF20)) \sm_reset_tx_pll_timer_ctr[8]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[7]), .I1(\sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 ), .I2(sm_reset_tx_pll_timer_ctr_reg[6]), .I3(sm_reset_tx_pll_timer_ctr_reg[8]), .O(p_0_in__0[8])); LUT5 #( .INIT(32'hFFFFFFBF)) \sm_reset_tx_pll_timer_ctr[9]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[3]), .I1(sm_reset_tx_pll_timer_ctr_reg[2]), .I2(sm_reset_tx_pll_timer_ctr_reg[1]), .I3(sm_reset_tx_pll_timer_ctr_reg[0]), .I4(\sm_reset_tx_pll_timer_ctr[9]_i_3_n_0 ), .O(sel)); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT5 #( .INIT(32'hF7FF0800)) \sm_reset_tx_pll_timer_ctr[9]_i_2 (.I0(sm_reset_tx_pll_timer_ctr_reg[8]), .I1(sm_reset_tx_pll_timer_ctr_reg[6]), .I2(\sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 ), .I3(sm_reset_tx_pll_timer_ctr_reg[7]), .I4(sm_reset_tx_pll_timer_ctr_reg[9]), .O(p_0_in__0[9])); LUT6 #( .INIT(64'hFFFFFFEFFFFFFFFF)) \sm_reset_tx_pll_timer_ctr[9]_i_3 (.I0(sm_reset_tx_pll_timer_ctr_reg[8]), .I1(sm_reset_tx_pll_timer_ctr_reg[9]), .I2(sm_reset_tx_pll_timer_ctr_reg[6]), .I3(sm_reset_tx_pll_timer_ctr_reg[7]), .I4(sm_reset_tx_pll_timer_ctr_reg[4]), .I5(sm_reset_tx_pll_timer_ctr_reg[5]), .O(\sm_reset_tx_pll_timer_ctr[9]_i_3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \sm_reset_tx_pll_timer_ctr[9]_i_4 (.I0(sm_reset_tx_pll_timer_ctr_reg[4]), .I1(sm_reset_tx_pll_timer_ctr_reg[2]), .I2(sm_reset_tx_pll_timer_ctr_reg[0]), .I3(sm_reset_tx_pll_timer_ctr_reg[1]), .I4(sm_reset_tx_pll_timer_ctr_reg[3]), .I5(sm_reset_tx_pll_timer_ctr_reg[5]), .O(\sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[0] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[0]), .Q(sm_reset_tx_pll_timer_ctr_reg[0]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[1] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[1]), .Q(sm_reset_tx_pll_timer_ctr_reg[1]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[2] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[2]), .Q(sm_reset_tx_pll_timer_ctr_reg[2]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[3] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[3]), .Q(sm_reset_tx_pll_timer_ctr_reg[3]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[4] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[4]), .Q(sm_reset_tx_pll_timer_ctr_reg[4]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[5] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[5]), .Q(sm_reset_tx_pll_timer_ctr_reg[5]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[6] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[6]), .Q(sm_reset_tx_pll_timer_ctr_reg[6]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[7] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[7]), .Q(sm_reset_tx_pll_timer_ctr_reg[7]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[8] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[8]), .Q(sm_reset_tx_pll_timer_ctr_reg[8]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[9] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[9]), .Q(sm_reset_tx_pll_timer_ctr_reg[9]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); LUT4 #( .INIT(16'h00EA)) sm_reset_tx_pll_timer_sat_i_1 (.I0(sm_reset_tx_pll_timer_sat), .I1(sm_reset_tx_pll_timer_sat_i_2_n_0), .I2(sm_reset_tx_pll_timer_sat_i_3_n_0), .I3(sm_reset_tx_pll_timer_clr_reg_n_0), .O(sm_reset_tx_pll_timer_sat_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT4 #( .INIT(16'h0040)) sm_reset_tx_pll_timer_sat_i_2 (.I0(sm_reset_tx_pll_timer_ctr_reg[3]), .I1(sm_reset_tx_pll_timer_ctr_reg[2]), .I2(sm_reset_tx_pll_timer_ctr_reg[1]), .I3(sm_reset_tx_pll_timer_ctr_reg[0]), .O(sm_reset_tx_pll_timer_sat_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000020)) sm_reset_tx_pll_timer_sat_i_3 (.I0(sm_reset_tx_pll_timer_ctr_reg[6]), .I1(sm_reset_tx_pll_timer_ctr_reg[7]), .I2(sm_reset_tx_pll_timer_ctr_reg[5]), .I3(sm_reset_tx_pll_timer_ctr_reg[4]), .I4(sm_reset_tx_pll_timer_ctr_reg[9]), .I5(sm_reset_tx_pll_timer_ctr_reg[8]), .O(sm_reset_tx_pll_timer_sat_i_3_n_0)); FDRE #( .INIT(1'b0)) sm_reset_tx_pll_timer_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_tx_pll_timer_sat_i_1_n_0), .Q(sm_reset_tx_pll_timer_sat), .R(1'b0)); FDSE #( .INIT(1'b1)) sm_reset_tx_timer_clr_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1), .Q(sm_reset_tx_timer_clr_reg_n_0), .S(gtwiz_reset_tx_any_sync)); LUT3 #( .INIT(8'h7F)) sm_reset_tx_timer_ctr0 (.I0(sm_reset_tx_timer_ctr[2]), .I1(sm_reset_tx_timer_ctr[0]), .I2(sm_reset_tx_timer_ctr[1]), .O(p_0_in)); LUT1 #( .INIT(2'h1)) \sm_reset_tx_timer_ctr[0]_i_1 (.I0(sm_reset_tx_timer_ctr[0]), .O(p_1_in[0])); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT2 #( .INIT(4'h6)) \sm_reset_tx_timer_ctr[1]_i_1 (.I0(sm_reset_tx_timer_ctr[0]), .I1(sm_reset_tx_timer_ctr[1]), .O(p_1_in[1])); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT3 #( .INIT(8'h78)) \sm_reset_tx_timer_ctr[2]_i_1 (.I0(sm_reset_tx_timer_ctr[0]), .I1(sm_reset_tx_timer_ctr[1]), .I2(sm_reset_tx_timer_ctr[2]), .O(p_1_in[2])); FDRE #( .INIT(1'b0)) \sm_reset_tx_timer_ctr_reg[0] (.C(drpclk_in), .CE(p_0_in), .D(p_1_in[0]), .Q(sm_reset_tx_timer_ctr[0]), .R(sm_reset_tx_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_timer_ctr_reg[1] (.C(drpclk_in), .CE(p_0_in), .D(p_1_in[1]), .Q(sm_reset_tx_timer_ctr[1]), .R(sm_reset_tx_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_timer_ctr_reg[2] (.C(drpclk_in), .CE(p_0_in), .D(p_1_in[2]), .Q(sm_reset_tx_timer_ctr[2]), .R(sm_reset_tx_timer_clr_reg_n_0)); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT5 #( .INIT(32'h0000FF80)) sm_reset_tx_timer_sat_i_1 (.I0(sm_reset_tx_timer_ctr[2]), .I1(sm_reset_tx_timer_ctr[0]), .I2(sm_reset_tx_timer_ctr[1]), .I3(sm_reset_tx_timer_sat), .I4(sm_reset_tx_timer_clr_reg_n_0), .O(sm_reset_tx_timer_sat_i_1_n_0)); FDRE #( .INIT(1'b0)) sm_reset_tx_timer_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_tx_timer_sat_i_1_n_0), .Q(sm_reset_tx_timer_sat), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair50" *) LUT4 #( .INIT(16'h0400)) txuserrdy_out_i_3 (.I0(sm_reset_tx[1]), .I1(sm_reset_tx[2]), .I2(sm_reset_tx_timer_clr_reg_n_0), .I3(sm_reset_tx_timer_sat), .O(txuserrdy_out_i_3_n_0)); FDRE #( .INIT(1'b0)) txuserrdy_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_tx_any_inst_n_3), .Q(\gen_gtwizard_gthe3.txuserrdy_int ), .R(1'b0)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer (gtwiz_reset_rx_done_out, rxusrclk_in, rst_in_sync2_reg_0); output [0:0]gtwiz_reset_rx_done_out; input [0:0]rxusrclk_in; input rst_in_sync2_reg_0; wire [0:0]gtwiz_reset_rx_done_out; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_i_1__0_n_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; wire rst_in_sync2_reg_0; (* async_reg = "true" *) wire rst_in_sync3; wire [0:0]rxusrclk_in; (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_meta_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1__0_n_0), .D(1'b1), .Q(rst_in_meta)); LUT1 #( .INIT(2'h1)) rst_in_out_i_1__0 (.I0(rst_in_sync2_reg_0), .O(rst_in_out_i_1__0_n_0)); FDCE #( .INIT(1'b0)) rst_in_out_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1__0_n_0), .D(rst_in_sync3), .Q(gtwiz_reset_rx_done_out)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync1_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1__0_n_0), .D(rst_in_meta), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync2_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1__0_n_0), .D(rst_in_sync1), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync3_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1__0_n_0), .D(rst_in_sync2), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer_20 (gtwiz_reset_tx_done_out, rxusrclk_in, rst_in_sync2_reg_0); output [0:0]gtwiz_reset_tx_done_out; input [0:0]rxusrclk_in; input rst_in_sync2_reg_0; wire [0:0]gtwiz_reset_tx_done_out; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_i_1_n_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; wire rst_in_sync2_reg_0; (* async_reg = "true" *) wire rst_in_sync3; wire [0:0]rxusrclk_in; (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_meta_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1_n_0), .D(1'b1), .Q(rst_in_meta)); LUT1 #( .INIT(2'h1)) rst_in_out_i_1 (.I0(rst_in_sync2_reg_0), .O(rst_in_out_i_1_n_0)); FDCE #( .INIT(1'b0)) rst_in_out_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1_n_0), .D(rst_in_sync3), .Q(gtwiz_reset_tx_done_out)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync1_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1_n_0), .D(rst_in_meta), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync2_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1_n_0), .D(rst_in_sync1), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync3_reg (.C(rxusrclk_in), .CE(1'b1), .CLR(rst_in_out_i_1_n_0), .D(rst_in_sync2), .Q(rst_in_sync3)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer (gtwiz_reset_all_sync, drpclk_in, gtwiz_reset_all_in); output gtwiz_reset_all_sync; input [0:0]drpclk_in; input [0:0]gtwiz_reset_all_in; wire [0:0]drpclk_in; wire [0:0]gtwiz_reset_all_in; wire gtwiz_reset_all_sync; (* async_reg = "true" *) wire rst_in_meta; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(gtwiz_reset_all_in), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(gtwiz_reset_all_in), .Q(gtwiz_reset_all_sync)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(gtwiz_reset_all_in), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(gtwiz_reset_all_in), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(gtwiz_reset_all_in), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_14 (gtwiz_reset_rx_any_sync, \FSM_sequential_sm_reset_rx_reg[1] , \FSM_sequential_sm_reset_rx_reg[1]_0 , \FSM_sequential_sm_reset_rx_reg[1]_1 , drpclk_in, Q, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int , rxprogdivreset_out_reg, \gen_gtwizard_gthe3.rxprogdivreset_int , plllock_rx_sync, gtrxreset_out_reg, \gen_gtwizard_gthe3.gtrxreset_int , rst_in_out_reg_0, gtwiz_reset_rx_datapath_in, rst_in_out_reg_1); output gtwiz_reset_rx_any_sync; output \FSM_sequential_sm_reset_rx_reg[1] ; output \FSM_sequential_sm_reset_rx_reg[1]_0 ; output \FSM_sequential_sm_reset_rx_reg[1]_1 ; input [0:0]drpclk_in; input [2:0]Q; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ; input rxprogdivreset_out_reg; input \gen_gtwizard_gthe3.rxprogdivreset_int ; input plllock_rx_sync; input gtrxreset_out_reg; input \gen_gtwizard_gthe3.gtrxreset_int ; input rst_in_out_reg_0; input [0:0]gtwiz_reset_rx_datapath_in; input rst_in_out_reg_1; wire \FSM_sequential_sm_reset_rx_reg[1] ; wire \FSM_sequential_sm_reset_rx_reg[1]_0 ; wire \FSM_sequential_sm_reset_rx_reg[1]_1 ; wire [2:0]Q; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ; wire \gen_gtwizard_gthe3.gtrxreset_int ; wire \gen_gtwizard_gthe3.rxprogdivreset_int ; wire gtrxreset_out_i_2_n_0; wire gtrxreset_out_reg; wire gtwiz_reset_rx_any; wire gtwiz_reset_rx_any_sync; wire [0:0]gtwiz_reset_rx_datapath_in; wire plllock_rx_sync; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_reg_0; wire rst_in_out_reg_1; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; wire rxprogdivreset_out_reg; LUT6 #( .INIT(64'h7FFFFFFF44884488)) gtrxreset_out_i_1 (.I0(Q[1]), .I1(gtrxreset_out_i_2_n_0), .I2(plllock_rx_sync), .I3(Q[0]), .I4(gtrxreset_out_reg), .I5(\gen_gtwizard_gthe3.gtrxreset_int ), .O(\FSM_sequential_sm_reset_rx_reg[1]_1 )); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT2 #( .INIT(4'h1)) gtrxreset_out_i_2 (.I0(gtwiz_reset_rx_any_sync), .I1(Q[2]), .O(gtrxreset_out_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT5 #( .INIT(32'hFDFF0100)) pllreset_rx_out_i_1 (.I0(Q[1]), .I1(Q[2]), .I2(gtwiz_reset_rx_any_sync), .I3(Q[0]), .I4(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ), .O(\FSM_sequential_sm_reset_rx_reg[1] )); LUT3 #( .INIT(8'hFE)) rst_in_meta_i_1 (.I0(rst_in_out_reg_0), .I1(gtwiz_reset_rx_datapath_in), .I2(rst_in_out_reg_1), .O(gtwiz_reset_rx_any)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(gtwiz_reset_rx_any), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(gtwiz_reset_rx_any), .Q(gtwiz_reset_rx_any_sync)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(gtwiz_reset_rx_any), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(gtwiz_reset_rx_any), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(gtwiz_reset_rx_any), .Q(rst_in_sync3)); LUT6 #( .INIT(64'hFFFBFFFF00120012)) rxprogdivreset_out_i_1 (.I0(Q[1]), .I1(Q[2]), .I2(Q[0]), .I3(gtwiz_reset_rx_any_sync), .I4(rxprogdivreset_out_reg), .I5(\gen_gtwizard_gthe3.rxprogdivreset_int ), .O(\FSM_sequential_sm_reset_rx_reg[1]_0 )); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_15 (in0, drpclk_in, gtwiz_reset_rx_datapath_in, rst_in_out_reg_0); output in0; input [0:0]drpclk_in; input [0:0]gtwiz_reset_rx_datapath_in; input rst_in_out_reg_0; wire [0:0]drpclk_in; wire [0:0]gtwiz_reset_rx_datapath_in; wire in0; wire rst_in0_0; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_reg_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; LUT2 #( .INIT(4'hE)) rst_in_meta_i_1__0 (.I0(gtwiz_reset_rx_datapath_in), .I1(rst_in_out_reg_0), .O(rst_in0_0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(rst_in0_0), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(rst_in0_0), .Q(in0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(rst_in0_0), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(rst_in0_0), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(rst_in0_0), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_16 (in0, drpclk_in, rst_in_meta_reg_0); output in0; input [0:0]drpclk_in; input rst_in_meta_reg_0; wire [0:0]drpclk_in; wire in0; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_meta_reg_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(rst_in_meta_reg_0), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(rst_in_meta_reg_0), .Q(in0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(rst_in_meta_reg_0), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(rst_in_meta_reg_0), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(rst_in_meta_reg_0), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_17 (gtwiz_reset_tx_any_sync, \FSM_sequential_sm_reset_tx_reg[1] , \FSM_sequential_sm_reset_tx_reg[1]_0 , \FSM_sequential_sm_reset_tx_reg[0] , drpclk_in, gtwiz_reset_tx_datapath_in, rst_in_out_reg_0, Q, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int , plllock_tx_sync, gttxreset_out_reg, \gen_gtwizard_gthe3.gttxreset_int , txuserrdy_out_reg, gtwiz_reset_userclk_tx_active_sync, \gen_gtwizard_gthe3.txuserrdy_int ); output gtwiz_reset_tx_any_sync; output \FSM_sequential_sm_reset_tx_reg[1] ; output \FSM_sequential_sm_reset_tx_reg[1]_0 ; output \FSM_sequential_sm_reset_tx_reg[0] ; input [0:0]drpclk_in; input [0:0]gtwiz_reset_tx_datapath_in; input rst_in_out_reg_0; input [2:0]Q; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ; input plllock_tx_sync; input gttxreset_out_reg; input \gen_gtwizard_gthe3.gttxreset_int ; input txuserrdy_out_reg; input gtwiz_reset_userclk_tx_active_sync; input \gen_gtwizard_gthe3.txuserrdy_int ; wire \FSM_sequential_sm_reset_tx_reg[0] ; wire \FSM_sequential_sm_reset_tx_reg[1] ; wire \FSM_sequential_sm_reset_tx_reg[1]_0 ; wire [2:0]Q; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ; wire \gen_gtwizard_gthe3.gttxreset_int ; wire \gen_gtwizard_gthe3.txuserrdy_int ; wire gttxreset_out_i_2_n_0; wire gttxreset_out_reg; wire gtwiz_reset_tx_any; wire gtwiz_reset_tx_any_sync; wire [0:0]gtwiz_reset_tx_datapath_in; wire gtwiz_reset_userclk_tx_active_sync; wire plllock_tx_sync; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_reg_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; wire txuserrdy_out_i_2_n_0; wire txuserrdy_out_reg; LUT6 #( .INIT(64'h7FFFFFFF44884488)) gttxreset_out_i_1 (.I0(Q[1]), .I1(gttxreset_out_i_2_n_0), .I2(plllock_tx_sync), .I3(Q[0]), .I4(gttxreset_out_reg), .I5(\gen_gtwizard_gthe3.gttxreset_int ), .O(\FSM_sequential_sm_reset_tx_reg[1]_0 )); LUT2 #( .INIT(4'h1)) gttxreset_out_i_2 (.I0(gtwiz_reset_tx_any_sync), .I1(Q[2]), .O(gttxreset_out_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT5 #( .INIT(32'hFDFF0100)) pllreset_tx_out_i_1 (.I0(Q[1]), .I1(Q[2]), .I2(gtwiz_reset_tx_any_sync), .I3(Q[0]), .I4(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ), .O(\FSM_sequential_sm_reset_tx_reg[1] )); LUT2 #( .INIT(4'hE)) rst_in_meta_i_1__1 (.I0(gtwiz_reset_tx_datapath_in), .I1(rst_in_out_reg_0), .O(gtwiz_reset_tx_any)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(gtwiz_reset_tx_any), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(gtwiz_reset_tx_any), .Q(gtwiz_reset_tx_any_sync)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(gtwiz_reset_tx_any), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(gtwiz_reset_tx_any), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(gtwiz_reset_tx_any), .Q(rst_in_sync3)); LUT6 #( .INIT(64'hDD55DD5588008C00)) txuserrdy_out_i_1 (.I0(txuserrdy_out_i_2_n_0), .I1(txuserrdy_out_reg), .I2(Q[0]), .I3(gtwiz_reset_userclk_tx_active_sync), .I4(gtwiz_reset_tx_any_sync), .I5(\gen_gtwizard_gthe3.txuserrdy_int ), .O(\FSM_sequential_sm_reset_tx_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT4 #( .INIT(16'h0110)) txuserrdy_out_i_2 (.I0(Q[2]), .I1(gtwiz_reset_tx_any_sync), .I2(Q[1]), .I3(Q[0]), .O(txuserrdy_out_i_2_n_0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_18 (in0, drpclk_in, gtwiz_reset_tx_datapath_in); output in0; input [0:0]drpclk_in; input [0:0]gtwiz_reset_tx_datapath_in; wire [0:0]drpclk_in; wire [0:0]gtwiz_reset_tx_datapath_in; wire in0; (* async_reg = "true" *) wire rst_in_meta; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(gtwiz_reset_tx_datapath_in), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(gtwiz_reset_tx_datapath_in), .Q(in0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(gtwiz_reset_tx_datapath_in), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(gtwiz_reset_tx_datapath_in), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(gtwiz_reset_tx_datapath_in), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_19 (in0, drpclk_in, rst_in_meta_reg_0); output in0; input [0:0]drpclk_in; input rst_in_meta_reg_0; wire [0:0]drpclk_in; wire in0; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_meta_reg_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(rst_in_meta_reg_0), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(rst_in_meta_reg_0), .Q(in0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(rst_in_meta_reg_0), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(rst_in_meta_reg_0), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(rst_in_meta_reg_0), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gtwizard_ultrascale_v1_7_9_reset_synchronizer_21 (\gen_gtwizard_gthe3.txprogdivreset_int , drpclk_in, rst_in0); output \gen_gtwizard_gthe3.txprogdivreset_int ; input [0:0]drpclk_in; input rst_in0; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.txprogdivreset_int ; wire rst_in0; (* async_reg = "true" *) wire rst_in_meta; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(rst_in0), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(rst_in0), .Q(\gen_gtwizard_gthe3.txprogdivreset_int )); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(rst_in0), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(rst_in0), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(rst_in0), .Q(rst_in_sync3)); endmodule `pragma protect begin_protected `pragma protect version = 1 `pragma protect encrypt_agent = "XILINX" `pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2" `pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64) `pragma protect key_block WrLPAmevOeee/HiaIGgPKffTsGjPw79Mvhb1LvIE3IQs20r9+LQOoFGpfUylEN1UW2O2frWdS04S 72SDyqvJ5A== `pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128) `pragma protect key_block C57Uh05FvDEJaXQ4H8lC5UbDO/jg7m+45NOtD4cM+eEYb3jcEPXS/mMv8e0ZOAe/mg7S5VXmkWr7 VEk0dR5AU4kxRj4XjFKlvVLZkhNdXiS3LQk/EziN2GSKJjjDKBkNHEfhYIGF1ZkOpC43O4yuYrxk CIWTpVXywZi8wCaExe8= `pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block lnTbrZfs2R120YpSyobtyskobEgxZSAlXnUQXw1gJpszgY/hqhzTy3v0ru7GipkY6qPoEcZwNnVX iD7GpCBRhqKix8pqMugQ1kvNhkn1r2YRhmA6XHA0ry90LNrf+n9uqlf476IBJTLTd3uu4ZngV06I QvBbiq8tjaP25el1krCHHl5rfNirhuwiDDOMI2E116k0hSU8spCYQ0rZ4zCPJqOKT+fAtz1I+L2I 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30W6/WVZIHVXI4hz2Tj2FJeP6CH8heIsXS7ZBfvz1+iWQVKDBND6gqK57uetJX00xO/GaIU7C7Ei ZWjqfSDMfaTdMr904pAQs5ZgD6WLxqJ0SdR6Yf3b3jFUEVyOpGYiHs9rZpSbSzvEWuzPvUY8qp2g 6uB+B5OsRXrodWSBVexcC2Ew7CACMJHK/VgcemVB7fkUFAAvm1OZQomG3LlfjgcmZEqM8M7T0SDG eQPkn1NZ3fqf40igV86+Qi4vpjBZ1iFnppVxR3bpoQOg9tuOJU8+IviXdR6vDY3S9FrQqK3Rekwc Bt6ktGf99nmbyE087TL+ae35QKvlaepRf/Vpc8wejyMOFYHEIw== `pragma protect end_protected `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; parameter GRES_WIDTH = 10000; parameter GRES_START = 10000; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; wire GRESTORE; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; reg GRESTORE_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (strong1, weak0) GSR = GSR_int; assign (strong1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; assign (strong1, weak0) GRESTORE = GRESTORE_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end initial begin GRESTORE_int = 1'b0; #(GRES_START); GRESTORE_int = 1'b1; #(GRES_WIDTH); GRESTORE_int = 1'b0; end endmodule `endif