There are two versions of firmware: the base version using
Gigbit Ethernet and is based on ipbus as in fc7_ngFEC.
The second version is for use on Commnad module of the Apollo
ATCA project which uses PCIe instead. The PCIe address apace is
32bit but as PCIe is byte address, the two LSB must always be "00"
and bit 31-2 mapped to bit 29-0 of ipbus address space. The two
MSB of ipbus address is prepended by firmware as "01" so that both
versions have the same address map in ipbus address space.
3/10/2021
Stat_reg base address is 0x60000000
0x0	firmware version
0x1	firmware creation date
0x2	bit 0		if 1, TCDS2 GBT in loopback mode
0x3	bit 0		fabric_clk locked
	bit 1		fabric_clk input signal stopped
	bit 2		fabric_clk feedback signal stopped
	bit 3		BC0 missing
	bit 4		if 0, Si5345 loss of lock
	bit 16		if 0, FireFly RX0 present
	bit 17		if 0, FireFly RX1 present
	bit 18		if 0, FireFly RX2 present
	bit 19		if 0, FireFly RX3 present
	bit 20		if 0, FireFly TX0 present
	bit 21		if 0, FireFly TX1 present
	bit 22		if 0, FireFly TX2 present
	bit 23		if 0, FireFly TX3 present
	bit 30-24	board ID
0x30-0x5f	GBT status register for SFP1 to SPF48
	bit 0		rx_data_valid
	bit 1		rx_frame_locked
	bit 2		rx_wordclk_locked
	bit 3		rx_ready
	bit 4		mgt_ready
	bit 5		tx_ready
	bit 6		cpll locked
	bit 7		mgt_reset_tx_done
	bit 8-31	not used
0x60-0x8f	ngccm_bkp_reg	
0x90-0xbf	ngccm_status_reg	
0x90	ngccm_status_reg for SFP1
	bit 24-16	all '1' after ngCCM_status reset, reset to '0' if 
			corresponging status bit is '0' when test_comm is '1'
	bit 24		RX_COMM_HBGOOD
	bit 23		RX_DATA_VALID
	bit 22		RX_READY
	bit 21		RX_IS_DATA
	bit 20		RX_HEADER_LOCKED
	bit 19		RXPLL_LOCKED
	bit 18		EPCS_CDR_LOCKED
	bit 17		SYS_REFCLK
	bit 16		SYS_MASTER
	bit 8-0		current ngCCM_status
	bit 8		RX_COMM_HBGOOD
	bit 7		RX_DATA_VALID
	bit 6		RX_READY
	bit 5		RX_IS_DATA
	bit 4		RX_HEADER_LOCKED
	bit 3		RXPLL_LOCKED
	bit 2		EPCS_CDR_LOCKED
	bit 1		SYS_REFCLK
	bit 0		SYS_MASTER
0x91	ngccm_status_reg for SFP2
...
0xbf	ngccm_status_reg for SFP48
0x200-0x22f	rate_ngccm_status0 bit SYS_MASTER
0x200	SFP1 
	bit 15-0	percentage of bit = '1' when test_comm = '1', 0x8000 equals 100%		
0x201	SFP2
... 
0x22f	SFP48 
0x230-0x25f	rate_ngccm_status1 bit SYS_REFCLK	
0x230	SFP1 
	bit 15-0	percentage of bit = '1' when test_comm = '1', 0x8000 equals 100%		
0x231	SFP2
... 
0x25f	SFP48 
0x260-0x28f	rate_ngccm_status2 bit EPCS_CDR_LOCKED	
0x260	SFP1 
	bit 15-0	percentage of bit = '1' when test_comm = '1', 0x8000 equals 100%		
0x261	SFP2
... 
0x28f	SFP48 
0x290-0x2bf	rate_ngccm_status3 bit RXPLL_LOCKED	
0x290	SFP1 
	bit 15-0	percentage of bit = '1' when test_comm = '1', 0x8000 equals 100%		
0x291	SFP2
... 
0x2bf	SFP48 
0x2c0-0x2ef	rate_ngccm_status4 bit RX_HEADER_LOCKED	
0x2c0	SFP1 
	bit 15-0	percentage of bit = '1' when test_comm = '1', 0x8000 equals 100%		
0x2c1	SFP2
... 
0x2ef	SFP48 
0x2f0-0x31f	rate_ngccm_status6 bit RX_READY	
0x2f0	SFP1 
	bit 15-0	percentage of bit = '1' when test_comm = '1', 0x8000 equals 100%		
0x2f1	SFP2
... 
0x31f	SFP48 
0x320-0x34f	rate_ngccm_status7 bit RX_DATA_VALID	
0x320	SFP1 
	bit 15-0	percentage of bit = '1' when test_comm = '1', 0x8000 equals 100%		
0x321	SFP2
... 
0x34f	SFP48 
0x350-0x37f	rate_ngccm_status8 bit RX_COMM_HBGOOD	
0x350	SFP1 
	bit 15-0	percentage of bit = '1' when test_comm = '1', 0x8000 equals 100%		
0x351	SFP2
... 
0x37f	SFP48 
0x380-0x3af	rate of test_comm
0x380	rate of test_comm for SFP1
	bit 15-0	percentage of test_comm = '1' over time, 0x8000 equals 100%
0x381	rate of test_comm for SFP2
...
0x3af	rate of test_comm for SFP48

0x400-0x42f	rx_rs_err_cnt for channel0-47	
0x430-0x45f	PRBS_err_cnt for channel0-47	
0x460-0x48f	ngccm_rx_down_cnt for channel0-47	
0x490-0x4bf	TimeoutErrorCnt for channel0-47	
0x4c0-0x4ef	TCK_inCnt for channel0-47	
0x4f0-0x51f	TCK_outCnt for channel0-47	
0x520-0x54f	pwr_good_cnt for channel0-47	
0x550-0x57f	rx_frameclk_lock_lost_cnt for channel0-47	
0x580-0x5af	tx_not_ready_cnt for channel0-47	
0x5b0		TTC_counters(0) single bit error count	
0x5b1		TTC_counters(1) double bit error count
0x5b2		TTC_counters(2) QIEreset_cnt	
0x5b3		TTC_counters(3) EvCntRes_cnt	
0x5b4		TTC_counters(4) BC0_cnt	
0x5b5		TTC_counters(5) BC0_late_Cnt	
0x5b6		TTC_counters(6) BC0_onTime_cnt	
0x5b7		TTC_counters(7) BC0_early_cnt	
0x5b8		TTC_counters(8) WTE_cnt	
0x5e0		fabric_clk_LOCK_lost_cnt

0x600		tx_wordclk rate	
0x601		fabric_clk rate	
0x630-0x65f	rx_wordclk rate for channel0-47	
0x660-0x68f	rx_frameclk rate for channel0-47	

ctrl_reg base address 0x60001000
0x0	bit 0		reset GBT_bank_0 all
	bit 1		reset GBT_bank_1 all
	bit 2		reset GBT_bank_2 all
	bit 3		reset GBT_bank_3 all
	bit 4		reset GBT_bank_0 TX
	bit 5		reset GBT_bank_1 TX
	bit 6		reset GBT_bank_2 TX
	bit 7		reset GBT_bank_3 TX
	bit 8		reset GBT_bank_0 RX
	bit 9		reset GBT_bank_1 RX
	bit 10		reset GBT_bank_2 RX
	bit 11		reset GBT_bank_3 RX
	bit 12		reset error
	bit 13		reset PRBS of TCDS2_if 
	bit 14		reset TCDS2_if
	bit 15		reset ngccm_status
0x1	bit 0		if 1, set TCDS2 GBT in loopback mode
	bit 1		if 1, Si5345 select DTH's HQ clock as input
	bit 2		if 1, set TCDS2_if in PRBS test mode
	bit3		if 1, TTS = READY. If 0, TTS = BUSY
	bit 18-16	set SFP_GBT's loopback mode
0x2	bit 15-0	set I2C clock prescale
0x3	bit 31-0	if bit i is 1, corresponding SFP(i) is enabled
0x4	bit 15-0 	if bit i is 1, corresponding SFP(i+32) is enabled	
0x5	bit 31-0	if bit i is 1, reset Rx of corresponding SFP(i)
0x6	bit 15-0 	if bit i is 1, reset Rx of corresponding SFP(i+32)	
0x7	counter reset control
	bit 31 		if bit i is 1, execute counter reset	
	bit 30-29	when "00", reset all counters
			when "01", reset the counter for cntr_din(i), i = integer(bit 8-0)
			when "10", reset all counters for SFP(i), i = integer(bit 5-0)
			when "11", 
				case bit 3-0 is
				  when x"0" => reset counters corresponding to cntr_din(0-47)
				  when x"1" => reset counters corresponding to cntr_din(48-95)
				  when x"2" => reset counters corresponding to cntr_din(96-143)
				  when x"3" => reset counters corresponding to cntr_din(144-191)
				  when x"4" => reset counters corresponding to cntr_din(192-239)
				  when x"5" => reset counters corresponding to cntr_din(240-287)
				  when x"6" => reset counters corresponding to cntr_din(288-335)
				  when x"7" => reset counters corresponding to cntr_din(336-383)
				  when x"8" => reset counters corresponding to cntr_din(384-431)
				  when x"9" => reset counters corresponding to cntr_din(432-479)
				  when x"a" => reset counters corresponding to cntr_din(480-511)
				end case
0x8	bit 3-0		Firefly Rx reset
	bit 7-4		Firefly Tx reset
	bit 19-16	reset Firefly Rx I2C control
	bit 23-20	reset Firefly Tx I2C control
	bit 24		reset Si534x I2C control	
0x9	bit 31-0	if bit i is 1, reset HPTD circuit of corresponding SFP(i)
0xa	bit 15-0 	if bit i is 1, reset HPTD circuit of corresponding SFP(i+32)	
0x14	bit 15-0	ngCCM and ngfec_module partition reset for SFP1
	bit 31-16	ngCCM and ngfec_module partition reset for SFP2	
...
0x2b	bit 15-0	ngCCM and ngfec_module partition reset for SFP47	
	bit 31-16	ngCCM and ngfec_module partition reset for SFP48	
0x2c	bit 15-0	QIE_reset delay for SFP1
	bit 31-16	QIE_reset delay for SFP2
...
0x43	bit 15-0	QIE_reset delay for SFP47
	bit 31-16	QIE_reset delay for SFP48

ipb_miso, ipb_mosi base address
0x60000000	user_ipb_stat_regs
0x60000800	user_ipb_ctrl_regs
0x60100000	user_board_I2C (Firefly, Si_5345 etc)
	partition 8 controls Si534x chips
	partition 7-4 control FireFly Tx
	partition 3-0 control FireFly Rx
for ngFEC_modules, 5 MSB of address are always "01101"
	SFP number is specified as bit 25-20 and 
	partition is specified as bit26 & bit 19-16
0x68000000	SFP1
0x68100000	SFP1
......
0x6af00000	SFP48