Difference from fc7_ngFEC:
from the software point of view, number of channel has increased
to 48, so in the ipb_addr_sel table partion bit4 is moved from
bit 21 to bit 26 and SFP channel is specified by bit 25-20.
stat_reg base address is x"60000000", the same as before,
but its size is now 2048 words.
ctrl_reg space base address is now x"60000800", size remains 128 words.
As optical link becomes FireFly, its I2C control is moved from ngFEC_module
to a separate I2C_if module, which controls 4 each of FireFly TX and Rx
modules plus I2C control for SiLab clock generater Si5340 and Si5345. It
is exactly the same as its counter part in ngFEC_module and ngccm, so the
software should remain the same, except the base address for I2C_if module
is x"60100000".
The system ipbus space does not exist any more.
On the hardware side, the legacy TTC/TTS interface is no longer needed. 
It is now replaced by TCDS2 which uses backplane 10Gbit link for TTC and
TTS information exchange. As of now, TTC infomation in TCDS2 only BcntRes
is defined. Other TTC commands are only dummy in the firmware module TCDS2_if
and need be updated once they are defined.
Besides the TCDS2 stream, DTH is supposed to provide a high quality TTC clock
(320.54MHz)which can be used in place of the Rx recovered TTC clock to be used 
as a source for TTC clock distribution. If it is available, Si5435 should use
it as input, otherwise the Rx recovered clock should be selected for data run.
For test purposes, TCDS2_if can also be set to loopback mode and generate BcntRes
itself.
The transmitters to ngccm now uses HPTD to keep the latency the same every time
it startws. This also solved the problem of phase alignment between tx_wordclk
and the tx_refclk the fc7_ngFEC and the new firmware removed all the phase
monitoring circuits used before. 
Besides above mentioned address changes, the firmware modules remain the same
as in fc7_ngFEC so no new problem is not expected.
To save resources, counters and multiplexers are now built with the abundent
but little used DSP components of the Xilinx chip. The result is that there
are still 35% LUT, 70%FF and 18%BRAM availble for future expansions.
Test benches stat_reg_tb and ctrl_reg_tb are availble to verify how these 
DSP constructed modules work which simulates all the related modules.