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Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // DO NOT MODIFY THIS FILE. // IP VLNV: xilinx.com:ip:gtwizard_ultrascale:1.7 // IP Revision: 5 // The following must be inserted into your Verilog file for this // core to be instantiated. Change the instance name and port connections // (in parentheses) to your own signal names. //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG mgt_ip your_instance_name ( .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in), // input wire [0 : 0] gtwiz_userclk_tx_active_in .gtwiz_userclk_rx_reset_in(gtwiz_userclk_rx_reset_in), // input wire [0 : 0] gtwiz_userclk_rx_reset_in .gtwiz_userclk_rx_srcclk_out(gtwiz_userclk_rx_srcclk_out), // output wire [0 : 0] gtwiz_userclk_rx_srcclk_out .gtwiz_userclk_rx_usrclk_out(gtwiz_userclk_rx_usrclk_out), // output wire [0 : 0] gtwiz_userclk_rx_usrclk_out .gtwiz_userclk_rx_usrclk2_out(gtwiz_userclk_rx_usrclk2_out), // output wire [0 : 0] gtwiz_userclk_rx_usrclk2_out .gtwiz_userclk_rx_active_out(gtwiz_userclk_rx_active_out), // output wire [0 : 0] gtwiz_userclk_rx_active_out .gtwiz_reset_clk_freerun_in(gtwiz_reset_clk_freerun_in), // input wire [0 : 0] gtwiz_reset_clk_freerun_in .gtwiz_reset_all_in(gtwiz_reset_all_in), // input wire [0 : 0] gtwiz_reset_all_in .gtwiz_reset_tx_pll_and_datapath_in(gtwiz_reset_tx_pll_and_datapath_in), // input wire [0 : 0] gtwiz_reset_tx_pll_and_datapath_in .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in), // input wire [0 : 0] gtwiz_reset_tx_datapath_in .gtwiz_reset_rx_pll_and_datapath_in(gtwiz_reset_rx_pll_and_datapath_in), // input wire [0 : 0] gtwiz_reset_rx_pll_and_datapath_in .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), // input wire [0 : 0] gtwiz_reset_rx_datapath_in .gtwiz_reset_rx_cdr_stable_out(gtwiz_reset_rx_cdr_stable_out), // output wire [0 : 0] gtwiz_reset_rx_cdr_stable_out .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out), // output wire [0 : 0] gtwiz_reset_tx_done_out .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out), // output wire [0 : 0] gtwiz_reset_rx_done_out .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in), // input wire [39 : 0] gtwiz_userdata_tx_in .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out), // output wire [19 : 0] gtwiz_userdata_rx_out .drpclk_in(drpclk_in), // input wire [0 : 0] drpclk_in .gthrxn_in(gthrxn_in), // input wire [0 : 0] gthrxn_in .gthrxp_in(gthrxp_in), // input wire [0 : 0] gthrxp_in .gtrefclk0_in(gtrefclk0_in), // input wire [0 : 0] gtrefclk0_in .loopback_in(loopback_in), // input wire [2 : 0] loopback_in .rxpd_in(rxpd_in), // input wire [1 : 0] rxpd_in .rxpolarity_in(rxpolarity_in), // input wire [0 : 0] rxpolarity_in .rxslide_in(rxslide_in), // input wire [0 : 0] rxslide_in .txdlybypass_in(txdlybypass_in), // input wire [0 : 0] txdlybypass_in .txdlyen_in(txdlyen_in), // input wire [0 : 0] txdlyen_in .txdlyhold_in(txdlyhold_in), // input wire [0 : 0] txdlyhold_in .txdlyovrden_in(txdlyovrden_in), // input wire [0 : 0] txdlyovrden_in .txdlysreset_in(txdlysreset_in), // input wire [0 : 0] txdlysreset_in .txdlyupdown_in(txdlyupdown_in), // input wire [0 : 0] txdlyupdown_in .txpd_in(txpd_in), // input wire [1 : 0] txpd_in .txpdelecidlemode_in(txpdelecidlemode_in), // input wire [0 : 0] txpdelecidlemode_in .txphalign_in(txphalign_in), // input wire [0 : 0] txphalign_in .txphalignen_in(txphalignen_in), // input wire [0 : 0] txphalignen_in .txphdlypd_in(txphdlypd_in), // input wire [0 : 0] txphdlypd_in .txphdlyreset_in(txphdlyreset_in), // input wire [0 : 0] txphdlyreset_in .txphdlytstclk_in(txphdlytstclk_in), // input wire [0 : 0] txphdlytstclk_in .txphinit_in(txphinit_in), // input wire [0 : 0] txphinit_in .txphovrden_in(txphovrden_in), // input wire [0 : 0] txphovrden_in .txpolarity_in(txpolarity_in), // input wire [0 : 0] txpolarity_in .txsyncallin_in(txsyncallin_in), // input wire [0 : 0] txsyncallin_in .txsyncin_in(txsyncin_in), // input wire [0 : 0] txsyncin_in .txsyncmode_in(txsyncmode_in), // input wire [0 : 0] txsyncmode_in .txusrclk_in(txusrclk_in), // input wire [0 : 0] txusrclk_in .txusrclk2_in(txusrclk2_in), // input wire [0 : 0] txusrclk2_in .cplllock_out(cplllock_out), // output wire [0 : 0] cplllock_out .gthtxn_out(gthtxn_out), // output wire [0 : 0] gthtxn_out .gthtxp_out(gthtxp_out), // output wire [0 : 0] gthtxp_out .gtpowergood_out(gtpowergood_out), // output wire [0 : 0] gtpowergood_out .rxpmaresetdone_out(rxpmaresetdone_out), // output wire [0 : 0] rxpmaresetdone_out .txdlysresetdone_out(txdlysresetdone_out), // output wire [0 : 0] txdlysresetdone_out .txoutclk_out(txoutclk_out), // output wire [0 : 0] txoutclk_out .txphaligndone_out(txphaligndone_out), // output wire [0 : 0] txphaligndone_out .txphinitdone_out(txphinitdone_out), // output wire [0 : 0] txphinitdone_out .txpmaresetdone_out(txpmaresetdone_out), // output wire [0 : 0] txpmaresetdone_out .txsyncdone_out(txsyncdone_out), // output wire [0 : 0] txsyncdone_out .txsyncout_out(txsyncout_out) // output wire [0 : 0] txsyncout_out ); // INST_TAG_END ------ End INSTANTIATION Template --------- // You must compile the wrapper file mgt_ip.v when simulating // the core, mgt_ip. When compiling the wrapper file, be sure to // reference the Verilog simulation library.