//------------------------------------------------------------------------------ // (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. //------------------------------------------------------------------------------ `timescale 1ps/1ps // ===================================================================================================================== // This example design wrapper module instantiates the core and any helper blocks which the user chose to exclude from // the core, connects them as appropriate, and maps enabled ports // ===================================================================================================================== module mgt_ip_example_wrapper ( input wire [0:0] gthrxn_in ,input wire [0:0] gthrxp_in ,output wire [0:0] gthtxn_out ,output wire [0:0] gthtxp_out ,input wire [0:0] gtwiz_userclk_tx_reset_in ,output wire [0:0] gtwiz_userclk_tx_srcclk_out ,output wire [0:0] gtwiz_userclk_tx_usrclk_out ,output wire [0:0] gtwiz_userclk_tx_usrclk2_out ,output wire [0:0] gtwiz_userclk_tx_active_out ,input wire [0:0] gtwiz_userclk_rx_reset_in ,output wire [0:0] gtwiz_userclk_rx_srcclk_out ,output wire [0:0] gtwiz_userclk_rx_usrclk_out ,output wire [0:0] gtwiz_userclk_rx_usrclk2_out ,output wire [0:0] gtwiz_userclk_rx_active_out ,input wire [0:0] gtwiz_buffbypass_tx_reset_in ,input wire [0:0] gtwiz_buffbypass_tx_start_user_in ,output wire [0:0] gtwiz_buffbypass_tx_done_out ,output wire [0:0] gtwiz_buffbypass_tx_error_out ,input wire [0:0] gtwiz_reset_clk_freerun_in ,input wire [0:0] gtwiz_reset_all_in ,input wire [0:0] gtwiz_reset_tx_pll_and_datapath_in ,input wire [0:0] gtwiz_reset_tx_datapath_in ,input wire [0:0] gtwiz_reset_rx_pll_and_datapath_in ,input wire [0:0] gtwiz_reset_rx_datapath_in ,output wire [0:0] gtwiz_reset_rx_cdr_stable_out ,output wire [0:0] gtwiz_reset_tx_done_out ,output wire [0:0] gtwiz_reset_rx_done_out ,input wire [39:0] gtwiz_userdata_tx_in ,output wire [19:0] gtwiz_userdata_rx_out ,input wire [0:0] drpclk_in ,input wire [0:0] gtrefclk0_in ,input wire [2:0] loopback_in ,input wire [1:0] rxpd_in ,input wire [0:0] rxpolarity_in ,input wire [0:0] rxslide_in ,input wire [1:0] txpd_in ,input wire [0:0] txpdelecidlemode_in ,input wire [0:0] txpolarity_in ,output wire [0:0] cplllock_out ,output wire [0:0] gtpowergood_out ,output wire [0:0] rxpmaresetdone_out ,output wire [0:0] txpmaresetdone_out ); // =================================================================================================================== // PARAMETERS AND FUNCTIONS // =================================================================================================================== // Declare and initialize local parameters and functions used for HDL generation localparam [191:0] P_CHANNEL_ENABLE = 192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000; `include "mgt_ip_example_wrapper_functions.v" localparam integer P_TX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(8); localparam integer P_RX_MASTER_CH_PACKED_IDX = f_calc_pk_mc_idx(8); // =================================================================================================================== // HELPER BLOCKS // =================================================================================================================== // Any helper blocks which the user chose to exclude from the core will appear below. In addition, some signal // assignments related to optionally-enabled ports may appear below. // ------------------------------------------------------------------------------------------------------------------- // Transmitter user clocking network helper block // ------------------------------------------------------------------------------------------------------------------- wire [0:0] txusrclk_int; wire [0:0] txusrclk2_int; wire [0:0] txoutclk_int; // Generate a single module instance which is driven by a clock source associated with the master transmitter channel, // and which drives TXUSRCLK and TXUSRCLK2 for all channels // The source clock is TXOUTCLK from the master transmitter channel assign gtwiz_userclk_tx_srcclk_out = txoutclk_int[P_TX_MASTER_CH_PACKED_IDX]; // Instantiate a single instance of the transmitter user clocking network helper block mgt_ip_example_gtwiz_userclk_tx gtwiz_userclk_tx_inst ( .gtwiz_userclk_tx_srcclk_in (gtwiz_userclk_tx_srcclk_out), .gtwiz_userclk_tx_reset_in (gtwiz_userclk_tx_reset_in), .gtwiz_userclk_tx_usrclk_out (gtwiz_userclk_tx_usrclk_out), .gtwiz_userclk_tx_usrclk2_out (gtwiz_userclk_tx_usrclk2_out), .gtwiz_userclk_tx_active_out (gtwiz_userclk_tx_active_out) ); // Drive TXUSRCLK and TXUSRCLK2 for all channels with the respective helper block outputs assign txusrclk_int = {1{gtwiz_userclk_tx_usrclk_out}}; assign txusrclk2_int = {1{gtwiz_userclk_tx_usrclk2_out}}; // ------------------------------------------------------------------------------------------------------------------- // Transmitter buffer bypass controller helper block // ------------------------------------------------------------------------------------------------------------------- wire [0:0] txphaligndone_int; wire [0:0] txphinitdone_int; wire [0:0] txdlysresetdone_int; wire [0:0] txsyncout_int; wire [0:0] txsyncdone_int; wire [0:0] txphdlyreset_int; wire [0:0] txphalign_int; wire [0:0] txphalignen_int; wire [0:0] txphdlypd_int; wire [0:0] txphinit_int; wire [0:0] txphovrden_int; wire [0:0] txdlysreset_int; wire [0:0] txdlybypass_int; wire [0:0] txdlyen_int; wire [0:0] txdlyovrden_int; wire [0:0] txphdlytstclk_int; wire [0:0] txdlyhold_int; wire [0:0] txdlyupdown_int; wire [0:0] txsyncmode_int; wire [0:0] txsyncallin_int; wire [0:0] txsyncin_int; // Generate a single module instance which uses the designated transmitter master channel as the transmit buffer // bypass master channel, and all other channels as transmit buffer bypass slave channels // Depending on the number of reset controller helper blocks, either use the single reset done indicator or the // logical combination of per-channel reset done indicators as the reset done indicator for use in this block wire gtwiz_buffbypass_tx_resetdone_int; assign gtwiz_buffbypass_tx_resetdone_int = gtwiz_reset_tx_done_out; (* DONT_TOUCH = "TRUE" *) mgt_ip_example_gtwiz_buffbypass_tx #( .P_TOTAL_NUMBER_OF_CHANNELS (1), .P_MASTER_CHANNEL_POINTER (P_TX_MASTER_CH_PACKED_IDX) ) gtwiz_buffbypass_tx_inst ( .gtwiz_buffbypass_tx_clk_in (gtwiz_userclk_tx_usrclk2_out), .gtwiz_buffbypass_tx_reset_in (gtwiz_buffbypass_tx_reset_in), .gtwiz_buffbypass_tx_start_user_in (gtwiz_buffbypass_tx_start_user_in), .gtwiz_buffbypass_tx_resetdone_in (gtwiz_buffbypass_tx_resetdone_int), .gtwiz_buffbypass_tx_done_out (gtwiz_buffbypass_tx_done_out), .gtwiz_buffbypass_tx_error_out (gtwiz_buffbypass_tx_error_out), .txphaligndone_in (txphaligndone_int), .txphinitdone_in (txphinitdone_int), .txdlysresetdone_in (txdlysresetdone_int), .txsyncout_in (txsyncout_int), .txsyncdone_in (txsyncdone_int), .txphdlyreset_out (txphdlyreset_int), .txphalign_out (txphalign_int), .txphalignen_out (txphalignen_int), .txphdlypd_out (txphdlypd_int), .txphinit_out (txphinit_int), .txphovrden_out (txphovrden_int), .txdlysreset_out (txdlysreset_int), .txdlybypass_out (txdlybypass_int), .txdlyen_out (txdlyen_int), .txdlyovrden_out (txdlyovrden_int), .txphdlytstclk_out (txphdlytstclk_int), .txdlyhold_out (txdlyhold_int), .txdlyupdown_out (txdlyupdown_int), .txsyncmode_out (txsyncmode_int), .txsyncallin_out (txsyncallin_int), .txsyncin_out (txsyncin_int) ); wire [0:0] gtpowergood_int; // Required assignment to expose the GTPOWERGOOD port per user request assign gtpowergood_out = gtpowergood_int; wire [0:0] cplllock_int; // Required assignment to expose the CPLLLOCK port per user request assign cplllock_out = cplllock_int; // =================================================================================================================== // CORE INSTANCE // =================================================================================================================== // Instantiate the core, mapping its enabled ports to example design ports and helper blocks as appropriate mgt_ip mgt_ip_inst ( .gthrxn_in (gthrxn_in) ,.gthrxp_in (gthrxp_in) ,.gthtxn_out (gthtxn_out) ,.gthtxp_out (gthtxp_out) ,.gtwiz_userclk_tx_active_in (gtwiz_userclk_tx_active_out) ,.gtwiz_userclk_rx_reset_in (gtwiz_userclk_rx_reset_in) ,.gtwiz_userclk_rx_srcclk_out (gtwiz_userclk_rx_srcclk_out) ,.gtwiz_userclk_rx_usrclk_out (gtwiz_userclk_rx_usrclk_out) ,.gtwiz_userclk_rx_usrclk2_out (gtwiz_userclk_rx_usrclk2_out) ,.gtwiz_userclk_rx_active_out (gtwiz_userclk_rx_active_out) ,.gtwiz_reset_clk_freerun_in (gtwiz_reset_clk_freerun_in) ,.gtwiz_reset_all_in (gtwiz_reset_all_in) ,.gtwiz_reset_tx_pll_and_datapath_in (gtwiz_reset_tx_pll_and_datapath_in) ,.gtwiz_reset_tx_datapath_in (gtwiz_reset_tx_datapath_in) ,.gtwiz_reset_rx_pll_and_datapath_in (gtwiz_reset_rx_pll_and_datapath_in) ,.gtwiz_reset_rx_datapath_in (gtwiz_reset_rx_datapath_in) ,.gtwiz_reset_rx_cdr_stable_out (gtwiz_reset_rx_cdr_stable_out) ,.gtwiz_reset_tx_done_out (gtwiz_reset_tx_done_out) ,.gtwiz_reset_rx_done_out (gtwiz_reset_rx_done_out) ,.gtwiz_userdata_tx_in (gtwiz_userdata_tx_in) ,.gtwiz_userdata_rx_out (gtwiz_userdata_rx_out) ,.drpclk_in (drpclk_in) ,.gtrefclk0_in (gtrefclk0_in) ,.loopback_in (loopback_in) ,.rxpd_in (rxpd_in) ,.rxpolarity_in (rxpolarity_in) ,.rxslide_in (rxslide_in) ,.txdlybypass_in (txdlybypass_int) ,.txdlyen_in (txdlyen_int) ,.txdlyhold_in (txdlyhold_int) ,.txdlyovrden_in (txdlyovrden_int) ,.txdlysreset_in (txdlysreset_int) ,.txdlyupdown_in (txdlyupdown_int) ,.txpd_in (txpd_in) ,.txpdelecidlemode_in (txpdelecidlemode_in) ,.txphalign_in (txphalign_int) ,.txphalignen_in (txphalignen_int) ,.txphdlypd_in (txphdlypd_int) ,.txphdlyreset_in (txphdlyreset_int) ,.txphdlytstclk_in (txphdlytstclk_int) ,.txphinit_in (txphinit_int) ,.txphovrden_in (txphovrden_int) ,.txpolarity_in (txpolarity_in) ,.txsyncallin_in (txsyncallin_int) ,.txsyncin_in (txsyncin_int) ,.txsyncmode_in (txsyncmode_int) ,.txusrclk_in (txusrclk_int) ,.txusrclk2_in (txusrclk2_int) ,.cplllock_out (cplllock_int) ,.gtpowergood_out (gtpowergood_int) ,.rxpmaresetdone_out (rxpmaresetdone_out) ,.txdlysresetdone_out (txdlysresetdone_int) ,.txoutclk_out (txoutclk_int) ,.txphaligndone_out (txphaligndone_int) ,.txphinitdone_out (txphinitdone_int) ,.txpmaresetdone_out (txpmaresetdone_out) ,.txsyncdone_out (txsyncdone_int) ,.txsyncout_out (txsyncout_int) ); endmodule