--====================================================================== -- Node image for the DTH, to provide a backplane TCDS loopback. --====================================================================== library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; use work.ipbus.all; use work.ipbus_reg_types.all; use work.drp_decl.all; use work.dth_tcds_infra_status.all; use work.ipbus_decode_dth_tcds_user_main.all; --================================================== entity dth_tcds_user_main is port ( clk_ipb : in std_logic; rst_ipb : in std_logic; ipb_in : in ipb_wbus; ipb_out : out ipb_rbus; clk_aux : in std_logic; rst_aux : in std_logic; nuke : in std_logic; soft_rst : in std_logic; -- Status summary from the board infrastructure. infra_status : in dth_tcds_infra_status; -- General purpose clocks from IC51. clk_gp_100mhz_p : in std_logic; clk_gp_100mhz_n : in std_logic; clk_gp_125mhz_p : in std_logic; clk_gp_125mhz_n : in std_logic; clk_gp_156_25mhz_p : in std_logic; clk_gp_156_25mhz_n : in std_logic; -- Bunch clocks coming from the two clock cleaners supplying the -- high-precision clock to the backplane. clk_40_backplane_lo_p : in std_logic; clk_40_backplane_lo_n : in std_logic; clk_40_backplane_hi_p : in std_logic; clk_40_backplane_hi_n : in std_logic; -- GTH reference clocks. mgt_refclk_gth_mgt226_rc0_p : in std_logic; mgt_refclk_gth_mgt226_rc0_n : in std_logic; mgt_refclk_gth_mgt227_rc0_p : in std_logic; mgt_refclk_gth_mgt227_rc0_n : in std_logic; mgt_refclk_gth_mgt231_rc0_p : in std_logic; mgt_refclk_gth_mgt231_rc0_n : in std_logic; mgt_refclk_gth_mgt232_rc0_p : in std_logic; mgt_refclk_gth_mgt232_rc0_n : in std_logic; mgt_refclk_gth_mgt233_rc0_p : in std_logic; mgt_refclk_gth_mgt233_rc0_n : in std_logic; mgt_refclk_gth_mgt234_rc0_p : in std_logic; mgt_refclk_gth_mgt234_rc0_n : in std_logic; -- GTY reference clocks. mgt_refclk_gty_mgt127_rc0_p : in std_logic; mgt_refclk_gty_mgt127_rc0_n : in std_logic; mgt_refclk_gty_mgt128_rc0_p : in std_logic; mgt_refclk_gty_mgt128_rc0_n : in std_logic; mgt_refclk_gty_mgt130_rc0_p : in std_logic; mgt_refclk_gty_mgt130_rc0_n : in std_logic; mgt_refclk_gty_mgt132_rc0_p : in std_logic; mgt_refclk_gty_mgt132_rc0_n : in std_logic; mgt_refclk_gty_mgt132_rc1_p : in std_logic; mgt_refclk_gty_mgt132_rc1_n : in std_logic; mgt_refclk_gty_mgt133_rc0_p : in std_logic; mgt_refclk_gty_mgt133_rc0_n : in std_logic; mgt_refclk_gty_mgt134_rc0_p : in std_logic; mgt_refclk_gty_mgt134_rc0_n : in std_logic; -- Clock selection lines. -- - The select line of IC84, switching between the GTH and GTY -- recovered MGT clocks. sel_recclk_out : out std_logic; -- Status/diagnostic LEDs. user_leds : out std_logic_vector(7 downto 0); -- Front-panel TCDS SFPs. tcds_frontpanel_a_tx_p : out std_logic; tcds_frontpanel_a_tx_n : out std_logic; tcds_frontpanel_a_rx_p : in std_logic; tcds_frontpanel_a_rx_n : in std_logic; -- tcds_frontpanel_b_tx_p : out std_logic; tcds_frontpanel_b_tx_n : out std_logic; tcds_frontpanel_b_rx_p : in std_logic; tcds_frontpanel_b_rx_n : in std_logic; -- Backplane TCDS signals. -- NOTE: Slot 1 (i.e., index 0) is the first hub slot, in which the DTH sits. tcds_backplane_slot2_tx_p : out std_logic; tcds_backplane_slot2_tx_n : out std_logic; tcds_backplane_slot2_rx_p : in std_logic; tcds_backplane_slot2_rx_n : in std_logic; -- tcds_backplane_slot3_tx_p : out std_logic; tcds_backplane_slot3_tx_n : out std_logic; tcds_backplane_slot3_rx_p : in std_logic; tcds_backplane_slot3_rx_n : in std_logic; -- tcds_backplane_slot4_tx_p : out std_logic; tcds_backplane_slot4_tx_n : out std_logic; tcds_backplane_slot4_rx_p : in std_logic; tcds_backplane_slot4_rx_n : in std_logic; -- tcds_backplane_slot5_tx_p : out std_logic; tcds_backplane_slot5_tx_n : out std_logic; tcds_backplane_slot5_rx_p : in std_logic; tcds_backplane_slot5_rx_n : in std_logic; -- tcds_backplane_slot6_tx_p : out std_logic; tcds_backplane_slot6_tx_n : out std_logic; tcds_backplane_slot6_rx_p : in std_logic; tcds_backplane_slot6_rx_n : in std_logic; -- tcds_backplane_slot7_tx_p : out std_logic; tcds_backplane_slot7_tx_n : out std_logic; tcds_backplane_slot7_rx_p : in std_logic; tcds_backplane_slot7_rx_n : in std_logic; -- tcds_backplane_slot8_tx_p : out std_logic; tcds_backplane_slot8_tx_n : out std_logic; tcds_backplane_slot8_rx_p : in std_logic; tcds_backplane_slot8_rx_n : in std_logic; -- tcds_backplane_slot9_tx_p : out std_logic; tcds_backplane_slot9_tx_n : out std_logic; tcds_backplane_slot9_rx_p : in std_logic; tcds_backplane_slot9_rx_n : in std_logic; -- tcds_backplane_slot10_tx_p : out std_logic; tcds_backplane_slot10_tx_n : out std_logic; tcds_backplane_slot10_rx_p : in std_logic; tcds_backplane_slot10_rx_n : in std_logic; -- tcds_backplane_slot11_tx_p : out std_logic; tcds_backplane_slot11_tx_n : out std_logic; tcds_backplane_slot11_rx_p : in std_logic; tcds_backplane_slot11_rx_n : in std_logic; -- tcds_backplane_slot12_tx_p : out std_logic; tcds_backplane_slot12_tx_n : out std_logic; tcds_backplane_slot12_rx_p : in std_logic; tcds_backplane_slot12_rx_n : in std_logic; -- tcds_backplane_slot13_tx_p : out std_logic; tcds_backplane_slot13_tx_n : out std_logic; tcds_backplane_slot13_rx_p : in std_logic; tcds_backplane_slot13_rx_n : in std_logic; -- tcds_backplane_slot14_tx_p : out std_logic; tcds_backplane_slot14_tx_n : out std_logic; tcds_backplane_slot14_rx_p : in std_logic; tcds_backplane_slot14_rx_n : in std_logic ); end dth_tcds_user_main; --================================================== architecture rtl of dth_tcds_user_main is -- IPBus read/write buses. signal ipbw : ipb_wbus_array(N_SLAVES - 1 downto 0); signal ipbr : ipb_rbus_array(N_SLAVES - 1 downto 0); -- DRP bus lines. signal drpw : drp_wbus_array(1 downto 0); signal drpr : drp_rbus_array(1 downto 0); signal ctrl : ipb_reg_v(0 downto 0); signal stat : ipb_reg_v(0 downto 0); -- Clock signals. signal clk_gp_100mhz : std_logic; signal mgt233_refclk0 : std_logic; begin ------------------------------------------ -- IPBus address decoder. ------------------------------------------ fabric : entity work.ipbus_fabric_sel generic map ( NSLV => N_SLAVES, SEL_WIDTH => IPBUS_SEL_WIDTH ) port map ( ipb_in => ipb_in, ipb_out => ipb_out, sel => ipbus_sel_dth_tcds_user_main(ipb_in.ipb_addr), ipb_to_slaves => ipbw, ipb_from_slaves => ipbr ); ------------------------------------------ -- Input buffers for general purpose clocks. ------------------------------------------ ibufds_100mhz : IBUFDS port map ( i => clk_gp_100mhz_p, ib => clk_gp_100mhz_n, o => clk_gp_100mhz ); -- Input buffers for MGT reference clocks. ibufds_mgt233_refclk0 : IBUFDS_GTE4 port map ( i => mgt_refclk_gth_mgt233_rc0_p, ib => mgt_refclk_gth_mgt233_rc0_n, o => mgt233_refclk0, ceb => '0' ); ------------------------------------------ -- Front-panel diagnostic leds. ------------------------------------------ leds : entity work.dth_tcds_user_leds port map ( user_led_top_left => infra_status.pcie_link_locked_and_up, user_led_top_right_of_left => infra_status.pcie_link_activity, user_led_top_left_of_right => '0', user_led_top_right => '0', user_led_bottom_left => '0', user_led_bottom_right_of_left => '0', user_led_bottom_left_of_right => '0', user_led_bottom_right => '0', user_led_connections => user_leds ); ------------------------------------------ -- Two DRP bridges into the GTH down below. ------------------------------------------ -- drp_gth_tcds_backplane_common : entity work.ipbus_drp_bridge -- port map ( -- clk => clk_ipb, -- rst => rst_ipb, -- ipb_in => ipbw(N_SLV_DRP_COMMON), -- ipb_out => ipbr(N_SLV_DRP_COMMON), -- drp_out => drpw(0), -- drp_in => drpr(0) -- ); -- drp_gth_tcds_backplane_channel : entity work.ipbus_drp_bridge -- port map ( -- clk => clk_ipb, -- rst => rst_ipb, -- ipb_in => ipbw(N_SLV_DRP_CHANNEL), -- ipb_out => ipbr(N_SLV_DRP_CHANNEL), -- drp_out => drpw(1), -- drp_in => drpr(1) -- ); ------------------------------------------ -- Loopback on the backplane TCDS signal. (Node functionality.) ------------------------------------------ loopback_tcds2_backplane_node : entity work.loopback_tcds_backplane_node_slot port map ( clk_ipb => clk_ipb, rst_ipb => rst_ipb, ipb_in => ipbw(N_SLV_LOOPBACK_TCDS_BACKPLANE_NODE_SLOT), ipb_out => ipbr(N_SLV_LOOPBACK_TCDS_BACKPLANE_NODE_SLOT), clk_gp_100mhz => clk_gp_100mhz, mgt233_refclk0_320mhz => mgt233_refclk0, tcds_backplane_slot2_tx_p => tcds_backplane_slot2_tx_p, tcds_backplane_slot2_tx_n => tcds_backplane_slot2_tx_n, tcds_backplane_slot2_rx_p => tcds_backplane_slot2_rx_p, tcds_backplane_slot2_rx_n => tcds_backplane_slot2_rx_n ); end rtl; --======================================================================