--====================================================================== -- Node end-point image for the DTH, to provide test point for the -- backplane TCDS link. --====================================================================== library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; use work.ipbus.all; use work.ipbus_reg_types.all; use work.tclink_lpgbt10G_pkg.all; use work.constants_tcds2.all; use work.dth_tcds_infra_status.all; use work.ipbus_decode_dth_tcds_user_main.all; use work.tcds2_choice_speed.all; use work.tcds2_interface_choice_mgt.all; use work.tcds2_interface_choice_speed.all; use work.tcds2_interface_pkg.all; use work.tcds2_link_pkg.all; use work.tcds2_link_speed_pkg.all; use work.tcds2_streams_pkg.all; --================================================== entity dth_tcds_user_main is port ( clk_ipb : in std_logic; rst_ipb : in std_logic; ipb_in : in ipb_wbus; ipb_out : out ipb_rbus; clk_aux : in std_logic; rst_aux : in std_logic; nuke : in std_logic; soft_rst : in std_logic; -- Status summary from the board infrastructure. infra_status : in dth_tcds_infra_status; -- General purpose clocks from IC51. clk_gp_100mhz_p : in std_logic; clk_gp_100mhz_n : in std_logic; clk_gp_125mhz_p : in std_logic; clk_gp_125mhz_n : in std_logic; clk_gp_156_25mhz_p : in std_logic; clk_gp_156_25mhz_n : in std_logic; -- Bunch clocks coming from the two clock cleaners supplying the -- high-precision clock to the backplane. clk_40_backplane_lo_p : in std_logic; clk_40_backplane_lo_n : in std_logic; clk_40_backplane_hi_p : in std_logic; clk_40_backplane_hi_n : in std_logic; -- Bunch clock coming from the 'MGT' clock cleaner (typically -- regenerated from either the 40 MHz or the 320 MHz backplane -- clock). clk_40_backplane_regen_p : in std_logic; clk_40_backplane_regen_n : in std_logic; -- GTH reference clocks. mgt_refclk_gth_mgt226_rc0_p : in std_logic; mgt_refclk_gth_mgt226_rc0_n : in std_logic; mgt_refclk_gth_mgt227_rc0_p : in std_logic; mgt_refclk_gth_mgt227_rc0_n : in std_logic; mgt_refclk_gth_mgt231_rc0_p : in std_logic; mgt_refclk_gth_mgt231_rc0_n : in std_logic; mgt_refclk_gth_mgt232_rc0_p : in std_logic; mgt_refclk_gth_mgt232_rc0_n : in std_logic; mgt_refclk_gth_mgt233_rc0_p : in std_logic; mgt_refclk_gth_mgt233_rc0_n : in std_logic; mgt_refclk_gth_mgt234_rc0_p : in std_logic; mgt_refclk_gth_mgt234_rc0_n : in std_logic; -- GTY reference clocks. mgt_refclk_gty_mgt127_rc0_p : in std_logic; mgt_refclk_gty_mgt127_rc0_n : in std_logic; mgt_refclk_gty_mgt128_rc0_p : in std_logic; mgt_refclk_gty_mgt128_rc0_n : in std_logic; mgt_refclk_gty_mgt130_rc0_p : in std_logic; mgt_refclk_gty_mgt130_rc0_n : in std_logic; mgt_refclk_gty_mgt132_rc0_p : in std_logic; mgt_refclk_gty_mgt132_rc0_n : in std_logic; mgt_refclk_gty_mgt132_rc1_p : in std_logic; mgt_refclk_gty_mgt132_rc1_n : in std_logic; mgt_refclk_gty_mgt133_rc0_p : in std_logic; mgt_refclk_gty_mgt133_rc0_n : in std_logic; mgt_refclk_gty_mgt134_rc0_p : in std_logic; mgt_refclk_gty_mgt134_rc0_n : in std_logic; -- -- Clock selection lines. -- -- - The select line of IC84, switching between the GTH and GTY -- -- recovered MGT clocks. -- sel_recclk_out : out std_logic; -- Recovered bunch clock outputs to the primary and secondary -- clock cleaners. tcds_clk_40_out_pri_p : out std_logic; tcds_clk_40_out_pri_n : out std_logic; tcds_clk_40_out_sec_p : out std_logic; tcds_clk_40_out_sec_n : out std_logic; -- Status/diagnostic LEDs. user_leds : out std_logic_vector(7 downto 0); -- Front-panel TCDS SFPs. tcds_frontpanel_a_tx_p : out std_logic; tcds_frontpanel_a_tx_n : out std_logic; tcds_frontpanel_a_rx_p : in std_logic; tcds_frontpanel_a_rx_n : in std_logic; -- tcds_frontpanel_b_tx_p : out std_logic; tcds_frontpanel_b_tx_n : out std_logic; tcds_frontpanel_b_rx_p : in std_logic; tcds_frontpanel_b_rx_n : in std_logic; -- DAQ FPGA TCDS connection. tcds_daq_fpga_tx_p : out std_logic; tcds_daq_fpga_tx_n : out std_logic; tcds_daq_fpga_rx_p : in std_logic; tcds_daq_fpga_rx_n : in std_logic; -- Backplane TCDS signals. -- NOTE: Slot 1 (i.e., index 0) is the first hub slot, in which the DTH sits. tcds_backplane_slot2_tx_p : out std_logic; tcds_backplane_slot2_tx_n : out std_logic; tcds_backplane_slot2_rx_p : in std_logic; tcds_backplane_slot2_rx_n : in std_logic; -- tcds_backplane_slot3_tx_p : out std_logic; tcds_backplane_slot3_tx_n : out std_logic; tcds_backplane_slot3_rx_p : in std_logic; tcds_backplane_slot3_rx_n : in std_logic; -- tcds_backplane_slot4_tx_p : out std_logic; tcds_backplane_slot4_tx_n : out std_logic; tcds_backplane_slot4_rx_p : in std_logic; tcds_backplane_slot4_rx_n : in std_logic; -- tcds_backplane_slot5_tx_p : out std_logic; tcds_backplane_slot5_tx_n : out std_logic; tcds_backplane_slot5_rx_p : in std_logic; tcds_backplane_slot5_rx_n : in std_logic; -- tcds_backplane_slot6_tx_p : out std_logic; tcds_backplane_slot6_tx_n : out std_logic; tcds_backplane_slot6_rx_p : in std_logic; tcds_backplane_slot6_rx_n : in std_logic; -- tcds_backplane_slot7_tx_p : out std_logic; tcds_backplane_slot7_tx_n : out std_logic; tcds_backplane_slot7_rx_p : in std_logic; tcds_backplane_slot7_rx_n : in std_logic; -- tcds_backplane_slot8_tx_p : out std_logic; tcds_backplane_slot8_tx_n : out std_logic; tcds_backplane_slot8_rx_p : in std_logic; tcds_backplane_slot8_rx_n : in std_logic; -- tcds_backplane_slot9_tx_p : out std_logic; tcds_backplane_slot9_tx_n : out std_logic; tcds_backplane_slot9_rx_p : in std_logic; tcds_backplane_slot9_rx_n : in std_logic; -- tcds_backplane_slot10_tx_p : out std_logic; tcds_backplane_slot10_tx_n : out std_logic; tcds_backplane_slot10_rx_p : in std_logic; tcds_backplane_slot10_rx_n : in std_logic; -- tcds_backplane_slot11_tx_p : out std_logic; tcds_backplane_slot11_tx_n : out std_logic; tcds_backplane_slot11_rx_p : in std_logic; tcds_backplane_slot11_rx_n : in std_logic; -- tcds_backplane_slot12_tx_p : out std_logic; tcds_backplane_slot12_tx_n : out std_logic; tcds_backplane_slot12_rx_p : in std_logic; tcds_backplane_slot12_rx_n : in std_logic; -- tcds_backplane_slot13_tx_p : out std_logic; tcds_backplane_slot13_tx_n : out std_logic; tcds_backplane_slot13_rx_p : in std_logic; tcds_backplane_slot13_rx_n : in std_logic; -- tcds_backplane_slot14_tx_p : out std_logic; tcds_backplane_slot14_tx_n : out std_logic; tcds_backplane_slot14_rx_p : in std_logic; tcds_backplane_slot14_rx_n : in std_logic ); end dth_tcds_user_main; --================================================== architecture rtl of dth_tcds_user_main is -- The transceiver type for the TCDS2 backplane link. constant C_TCDS2_MGT_TYPE : mgt_type_t := C_TCDS2_BACKEND_MGT_TYPE; -- Choice of TCDS2 backplane link line rate constant C_TCDS2_LINK_SPEED : tcds2_link_speed_t := C_TCDS2_BACKEND_LINK_SPEED; -- Include PRBS generator and checker for TCDS2 backplane link -- tests. constant C_TCDS2_INCLUDE_PRBS_LINK_TEST : boolean := true; -- The number of TTS2 channels in each back-end emulator. constant C_BACKEND_NUM_TTS2_CHANNELS : positive := 1; ------------------------------------------ -- IPBus read/write buses. ------------------------------------------ signal ipbw : ipb_wbus_array(N_SLAVES - 1 downto 0); signal ipbr : ipb_rbus_array(N_SLAVES - 1 downto 0); signal ctrl : ipb_reg_v(0 downto 0); signal stat : ipb_reg_v(0 downto 0); ------------------------------------------ -- Clock signals. ------------------------------------------ signal clk_gp_100mhz : std_logic; signal clk_gp_125mhz : std_logic; signal clk_gp_156_25mhz : std_logic; signal clk_40_backplane_lo : std_logic; signal clk_40_backplane_hi : std_logic; signal clk_40_backplane_regen : std_logic; signal clk_320_backplane_regen : std_logic; signal clk40 : std_logic; signal clk_40_tx : std_logic; signal clk_40_rx : std_logic; ------------------------------------------ -- MGT reference clocks from the secondary clock cleaner. ------------------------------------------ signal mgt233_refclk0 : std_logic; signal mgt233_refclk0_aux : std_logic; signal mgt234_refclk0 : std_logic; ------------------------------------------ -- Misc. ------------------------------------------ signal clkdiv : std_logic_vector(5 downto 0); ------------------------------------------ -- Signals related to the TCDS2 backplane link. ------------------------------------------ signal slave_mgt_reset_all : std_logic; signal slave_mgt_reset_tx_pll_and_datapath : std_logic; signal slave_mgt_reset_rx_pll_and_datapath : std_logic; signal slave_mgt_ctrl : tr_core_to_mgt; signal slave_mgt_stat : tr_mgt_to_core; signal slave_core_ctrl : tr_core_control; signal slave_core_stat : tr_core_status; signal slave_tclink_ctrl : tr_tclink_control; signal tcds2_interface_ctrl : tcds2_interface_ctrl_t; signal tcds2_interface_stat : tcds2_interface_stat_t; signal clk_40_oddr_c : std_logic; signal clk_40_oddr_d1 : std_logic; signal clk_40_oddr_d2 : std_logic; signal tcds_clk_40_out_pri : std_logic; signal tcds_clk_40_out_sec : std_logic; -- Control and status registers for the TCDS2 backplane link. signal ctrl_backplane_link : ipb_reg_v(0 downto 0); --signal stat_backplane_link : ipb_reg_v(0 downto 0); -- Temporary TCDS2 TTS2 signals. signal channel0_ttc2 : tcds2_ttc2; signal channel0_tts2 : tcds2_tts2_value_array(C_BACKEND_NUM_TTS2_CHANNELS - 1 downto 0); signal channel1_ttc2 : tcds2_ttc2; signal channel1_tts2 : tcds2_tts2_value_array(C_BACKEND_NUM_TTS2_CHANNELS - 1 downto 0); signal ttc2_frame : tcds2_frame_t; signal tts2_frame : tcds2_frame_t; signal tcds_backplane_data_frame_tx : tcds2_frame_t; signal tcds_backplane_data_frame_rx : tcds2_frame_t; ------------------------------------------ begin ------------------------------------------ -- IPBus address decoder. ------------------------------------------ fabric : entity work.ipbus_fabric_sel generic map ( NSLV => N_SLAVES, SEL_WIDTH => IPBUS_SEL_WIDTH ) port map ( ipb_in => ipb_in, ipb_out => ipb_out, sel => ipbus_sel_dth_tcds_user_main(ipb_in.ipb_addr), ipb_to_slaves => ipbw, ipb_from_slaves => ipbr ); ------------------------------------------ -- Input buffers for general purpose clocks. ------------------------------------------ ibufds_100mhz : ibufds port map ( i => clk_gp_100mhz_p, ib => clk_gp_100mhz_n, o => clk_gp_100mhz ); ibufds_125mhz : ibufds port map ( i => clk_gp_125mhz_p, ib => clk_gp_125mhz_n, o => clk_gp_125mhz ); ibufds_156_25mhz : ibufds port map ( i => clk_gp_156_25mhz_p, ib => clk_gp_156_25mhz_n, o => clk_gp_156_25mhz ); ------------------------------------------ -- Input buffers for the two 40 MHz clocks from the backplane clock -- cleaners. ------------------------------------------ ibufds_40mhz_backplane_lo : ibufds port map ( i => clk_40_backplane_lo_p, ib => clk_40_backplane_lo_n, o => clk_40_backplane_lo ); ibufds_40mhz_backplane_hi : ibufds port map ( i => clk_40_backplane_hi_p, ib => clk_40_backplane_hi_n, o => clk_40_backplane_hi ); ------------------------------------------ -- Input buffer for the 40 MHz clock regenerated from either the 40 -- MHz or the 320 MHz backplane clock. ------------------------------------------ ibufds_40mhz_backplane_regen : ibufds port map ( i => clk_40_backplane_regen_p, ib => clk_40_backplane_regen_n, o => clk_40_backplane_regen ); ------------------------------------------ -- Output buffers for the 40 MHz clocks to the primary and secondary -- clock cleaners. ------------------------------------------ obufds_clk_40mhz_pri : obufds port map ( i => tcds_clk_40_out_pri, o => tcds_clk_40_out_pri_p, ob => tcds_clk_40_out_pri_n ); obufds_clk_40mhz_sec : obufds port map ( i => tcds_clk_40_out_sec, o => tcds_clk_40_out_sec_p, ob => tcds_clk_40_out_sec_n ); ------------------------------------------ -- Input buffers for MGT reference clocks. ------------------------------------------ ibufds_mgt233_refclk0 : ibufds_gte4 generic map ( REFCLK_HROW_CK_SEL => "00" ) port map ( i => mgt_refclk_gth_mgt233_rc0_p, ib => mgt_refclk_gth_mgt233_rc0_n, o => mgt233_refclk0, odiv2 => mgt233_refclk0_aux, ceb => '0' ); ibufds_mgt234_refclk0 : ibufds_gte4 port map ( i => mgt_refclk_gth_mgt234_rc0_p, ib => mgt_refclk_gth_mgt234_rc0_n, o => mgt234_refclk0, ceb => '0' ); ------------------------------------------ -- Transition buffer to get the MGT233-rc0 into the fabric. ------------------------------------------ bufg_gt_320mhz_backplane_regen : bufg_gt port map ( i => mgt233_refclk0_aux, o => clk_320_backplane_regen, ce => '1', cemask => '0', clr => '0', clrmask => '0', div => "000" ); ------------------------------------------ -- Front-panel diagnostic leds. ------------------------------------------ leds : entity work.dth_tcds_user_leds port map ( user_led_top_left => infra_status.pcie_link_locked_and_up, user_led_top_right_of_left => infra_status.pcie_link_activity, user_led_top_left_of_right => '0', user_led_top_right => '0', user_led_bottom_left => '0', user_led_bottom_right_of_left => '0', user_led_bottom_left_of_right => '0', user_led_bottom_right => '0', user_led_connections => user_leds ); ------------------------------------------ -- Frequency counters to keep an eye on some of the clock signals. ------------------------------------------ freq_divs : entity work.freq_ctr_div generic map ( N_CLK => clkdiv'length ) port map ( -- General purpose clocks (from the auxiliary clock generator). clk(0) => clk_gp_100mhz, clk(1) => clk_gp_125mhz, clk(2) => clk_gp_156_25mhz, -- The 40 MHz and 320 MHz clocks from the MGT clock cleaner. NOTE: These -- are both regenerated from the selected (i.e., 40 MHz or 320 MHz) -- backplane clock. clk(3) => clk_40_backplane_regen, clk(4) => clk_320_backplane_regen, -- The 40 MHz recovered RX clock from the TCDS2 backplane link. clk(5) => clk_40_rx, clkdiv => clkdiv ); freq_cntrs : entity work.ipbus_freq_ctr generic map ( N_CLK => clkdiv'length ) port map ( clk => clk_ipb, rst => rst_ipb, ipb_in => ipbw(N_SLV_FREQUENCY_COUNTERS), ipb_out => ipbr(N_SLV_FREQUENCY_COUNTERS), clkdiv => clkdiv ); ------------------------------------------ -- Main TCDS2 (backplane link) interface. ------------------------------------------ tcds2_interface : entity work.tcds2_interface_with_mgt generic map ( G_MGT_TYPE => C_TCDS2_MGT_TYPE, G_LINK_SPEED => C_TCDS2_LINK_SPEED, G_INCLUDE_PRBS_LINK_TEST => C_TCDS2_INCLUDE_PRBS_LINK_TEST ) port map ( ctrl_i => tcds2_interface_ctrl, stat_o => tcds2_interface_stat, clk_sys_125mhz => clk_gp_125mhz, mgt_tx_p_o => tcds_backplane_slot2_tx_p, mgt_tx_n_o => tcds_backplane_slot2_tx_n, mgt_rx_p_i => tcds_backplane_slot2_rx_p, mgt_rx_n_i => tcds_backplane_slot2_rx_n, clk_320_mgt_ref_i => mgt233_refclk0, clk_40_o => clk40, clk_40_oddr_c_o => clk_40_oddr_c, clk_40_oddr_d1_o => clk_40_oddr_d1, clk_40_oddr_d2_o => clk_40_oddr_d2, orbit_o => open, --tcds2_orbit, channel0_ttc2_o => channel0_ttc2, channel0_tts2_i => channel0_tts2, channel1_ttc2_o => channel1_ttc2, channel1_tts2_i => channel1_tts2 ); -- The TCDS2 interface has its own (optional) IPBus accessor. tcds2_interface_accessor : entity work.ipbus_tcds2_interface_accessor port map ( clk_ipb => clk_ipb, rst_ipb => rst_ipb, ipb_in => ipbw(N_SLV_TCDS2_INTERFACE), ipb_out => ipbr(N_SLV_TCDS2_INTERFACE), ctrl_o => tcds2_interface_ctrl, stat_i => tcds2_interface_stat ); ------------------------------------------ -- Recovered LHC bunch clock for use outside the FPGA. ------------------------------------------ -- NOTE: These ones are the clocks for external use. oddr1_clk_40_out_pri : oddre1 generic map ( is_c_inverted => '0', is_d1_inverted => '0', is_d2_inverted => '0', srval => '0' ) port map ( sr => '0', c => clk_40_oddr_c, d1 => clk_40_oddr_d1, d2 => clk_40_oddr_d2, q => tcds_clk_40_out_pri ); oddr1_clk_40_out_sec : oddre1 generic map ( is_c_inverted => '0', is_d1_inverted => '0', is_d2_inverted => '0', srval => '0' ) port map ( sr => '0', c => clk_40_oddr_c, d1 => clk_40_oddr_d1, d2 => clk_40_oddr_d2, q => tcds_clk_40_out_sec ); clk_40_tx <= clk40; clk_40_rx <= clk40; ------------------------------------------ -- Back-end emulator connected to TCDS2 channel 0. ------------------------------------------ backend0 : entity work.backend_emulator generic map ( G_NUM_TTS2_CHANNELS => C_BACKEND_NUM_TTS2_CHANNELS ) port map ( clk_ipb => clk_ipb, rst_ipb => rst_ipb, ipb_in => ipbw(N_SLV_BACKEND_EMULATOR0), ipb_out => ipbr(N_SLV_BACKEND_EMULATOR0), clk_40 => clk_40_tx, ttc2_i => channel0_ttc2, tts2_o => channel0_tts2 ); ------------------------------------------ -- Back-end emulator connected to TCDS2 channel 1. ------------------------------------------ backend1 : entity work.backend_emulator generic map ( G_NUM_TTS2_CHANNELS => C_BACKEND_NUM_TTS2_CHANNELS ) port map ( clk_ipb => clk_ipb, rst_ipb => rst_ipb, ipb_in => ipbw(N_SLV_BACKEND_EMULATOR1), ipb_out => ipbr(N_SLV_BACKEND_EMULATOR1), clk_40 => clk_40_tx, ttc2_i => channel1_ttc2, tts2_o => channel1_tts2 ); end rtl; --======================================================================