--======================================================================
-- Test/helper firmware that runs a 10.2601216 Gbps IBERT on all TCDS
-- backplane lines.
--======================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

use work.ipbus.all;

use work.options_define.all;
use work.options_choose.all;
use work.dth_tcds_infra_status.all;

--==================================================

entity dth_tcds_user_main is
  port (
    clk_ipb : in std_logic;
    rst_ipb : in std_logic;
    ipb_in : in ipb_wbus;
    ipb_out : out ipb_rbus;
    clk_aux : in std_logic;
    rst_aux : in std_logic;
    nuke : in std_logic;
    soft_rst : in std_logic;

    -- Status summary from the board infrastructure.
    infra_status : in dth_tcds_infra_status;

    -- General purpose clocks from IC51.
    clk_gp_100mhz_p : in std_logic;
    clk_gp_100mhz_n : in std_logic;
    clk_gp_125mhz_p : in std_logic;
    clk_gp_125mhz_n : in std_logic;
    clk_gp_156_25mhz_p : in std_logic;
    clk_gp_156_25mhz_n : in std_logic;

    -- Bunch clocks coming from the two clock cleaners supplying the
    -- high-precision clock to the backplane.
    clk_40_backplane_lo_p : in std_logic;
    clk_40_backplane_lo_n : in std_logic;
    clk_40_backplane_hi_p : in std_logic;
    clk_40_backplane_hi_n : in std_logic;

    -- Bunch clock coming from the 'MGT' clock cleaner (typically
    -- regenerated from either the 40 MHz or the 320 MHz backplane
    -- clock).
    clk_40_backplane_regen_p : in std_logic;
    clk_40_backplane_regen_n : in std_logic;

    -- GTH reference clocks.
    mgt_refclk_gth_mgt226_rc0_p : in std_logic;
    mgt_refclk_gth_mgt226_rc0_n : in std_logic;
    mgt_refclk_gth_mgt227_rc0_p : in std_logic;
    mgt_refclk_gth_mgt227_rc0_n : in std_logic;
    mgt_refclk_gth_mgt231_rc0_p : in std_logic;
    mgt_refclk_gth_mgt231_rc0_n : in std_logic;
    mgt_refclk_gth_mgt232_rc0_p : in std_logic;
    mgt_refclk_gth_mgt232_rc0_n : in std_logic;
    mgt_refclk_gth_mgt233_rc0_p : in std_logic;
    mgt_refclk_gth_mgt233_rc0_n : in std_logic;
    mgt_refclk_gth_mgt234_rc0_p : in std_logic;
    mgt_refclk_gth_mgt234_rc0_n : in std_logic;

    -- GTY reference clocks.
    mgt_refclk_gty_mgt127_rc0_p : in std_logic;
    mgt_refclk_gty_mgt127_rc0_n : in std_logic;
    mgt_refclk_gty_mgt128_rc0_p : in std_logic;
    mgt_refclk_gty_mgt128_rc0_n : in std_logic;
    mgt_refclk_gty_mgt130_rc0_p : in std_logic;
    mgt_refclk_gty_mgt130_rc0_n : in std_logic;
    mgt_refclk_gty_mgt132_rc0_p : in std_logic;
    mgt_refclk_gty_mgt132_rc0_n : in std_logic;
    mgt_refclk_gty_mgt132_rc1_p : in std_logic;
    mgt_refclk_gty_mgt132_rc1_n : in std_logic;
    mgt_refclk_gty_mgt133_rc0_p : in std_logic;
    mgt_refclk_gty_mgt133_rc0_n : in std_logic;
    mgt_refclk_gty_mgt134_rc0_p : in std_logic;
    mgt_refclk_gty_mgt134_rc0_n : in std_logic;

    -- -- Clock selection lines.
    -- -- - The select line of IC84, switching between the GTH and GTY
    -- --   recovered MGT clocks.
    -- sel_recclk_out : out std_logic;

    -- Recovered bunch clock outputs to the primary and secondary
    -- clock cleaners.
    tcds_clk_40_out_pri_p : out std_logic;
    tcds_clk_40_out_pri_n : out std_logic;
    tcds_clk_40_out_sec_p : out std_logic;
    tcds_clk_40_out_sec_n : out std_logic;

    -- Status/diagnostic LEDs.
    user_leds : out std_logic_vector(7 downto 0);

    -- Front-panel TCDS SFPs.
    tcds_frontpanel_a_tx_p : out std_logic;
    tcds_frontpanel_a_tx_n : out std_logic;
    tcds_frontpanel_a_rx_p : in std_logic;
    tcds_frontpanel_a_rx_n : in std_logic;
    --
    tcds_frontpanel_b_tx_p : out std_logic;
    tcds_frontpanel_b_tx_n : out std_logic;
    tcds_frontpanel_b_rx_p : in std_logic;
    tcds_frontpanel_b_rx_n : in std_logic;

    -- DAQ FPGA TCDS connection.
    tcds_daq_fpga_tx_p : out std_logic;
    tcds_daq_fpga_tx_n : out std_logic;
    tcds_daq_fpga_rx_p : in std_logic;
    tcds_daq_fpga_rx_n : in std_logic;

    -- Backplane TCDS signals.
    -- NOTE: Slot 1 (i.e., index 0) is the first hub slot, in which the DTH sits.
    --
    tcds_backplane_slot2_tx_p : out std_logic;
    tcds_backplane_slot2_tx_n : out std_logic;
    tcds_backplane_slot2_rx_p : in std_logic;
    tcds_backplane_slot2_rx_n : in std_logic;
    --
    tcds_backplane_slot3_tx_p : out std_logic;
    tcds_backplane_slot3_tx_n : out std_logic;
    tcds_backplane_slot3_rx_p : in std_logic;
    tcds_backplane_slot3_rx_n : in std_logic;
    --
    tcds_backplane_slot4_tx_p : out std_logic;
    tcds_backplane_slot4_tx_n : out std_logic;
    tcds_backplane_slot4_rx_p : in std_logic;
    tcds_backplane_slot4_rx_n : in std_logic;
    --
    tcds_backplane_slot5_tx_p : out std_logic;
    tcds_backplane_slot5_tx_n : out std_logic;
    tcds_backplane_slot5_rx_p : in std_logic;
    tcds_backplane_slot5_rx_n : in std_logic;
    --
    tcds_backplane_slot6_tx_p : out std_logic;
    tcds_backplane_slot6_tx_n : out std_logic;
    tcds_backplane_slot6_rx_p : in std_logic;
    tcds_backplane_slot6_rx_n : in std_logic;
    --
    tcds_backplane_slot7_tx_p : out std_logic;
    tcds_backplane_slot7_tx_n : out std_logic;
    tcds_backplane_slot7_rx_p : in std_logic;
    tcds_backplane_slot7_rx_n : in std_logic;
    --
    tcds_backplane_slot8_tx_p : out std_logic;
    tcds_backplane_slot8_tx_n : out std_logic;
    tcds_backplane_slot8_rx_p : in std_logic;
    tcds_backplane_slot8_rx_n : in std_logic;
    --
    tcds_backplane_slot9_tx_p : out std_logic;
    tcds_backplane_slot9_tx_n : out std_logic;
    tcds_backplane_slot9_rx_p : in std_logic;
    tcds_backplane_slot9_rx_n : in std_logic;
    --
    tcds_backplane_slot10_tx_p : out std_logic;
    tcds_backplane_slot10_tx_n : out std_logic;
    tcds_backplane_slot10_rx_p : in std_logic;
    tcds_backplane_slot10_rx_n : in std_logic;
    --
    tcds_backplane_slot11_tx_p : out std_logic;
    tcds_backplane_slot11_tx_n : out std_logic;
    tcds_backplane_slot11_rx_p : in std_logic;
    tcds_backplane_slot11_rx_n : in std_logic;
    --
    tcds_backplane_slot12_tx_p : out std_logic;
    tcds_backplane_slot12_tx_n : out std_logic;
    tcds_backplane_slot12_rx_p : in std_logic;
    tcds_backplane_slot12_rx_n : in std_logic;
    --
    tcds_backplane_slot13_tx_p : out std_logic;
    tcds_backplane_slot13_tx_n : out std_logic;
    tcds_backplane_slot13_rx_p : in std_logic;
    tcds_backplane_slot13_rx_n : in std_logic;
    --
    tcds_backplane_slot14_tx_p : out std_logic;
    tcds_backplane_slot14_tx_n : out std_logic;
    tcds_backplane_slot14_rx_p : in std_logic;
    tcds_backplane_slot14_rx_n : in std_logic
  );

end dth_tcds_user_main;

--==================================================

architecture rtl of dth_tcds_user_main is

  -- Clock signals.
  signal clk_gp_100mhz : std_logic;
  signal mgt227_refclk0 : std_logic;
  signal mgt231_refclk0 : std_logic;
  signal mgt128_refclk0 : std_logic;
  signal mgt132_refclk0 : std_logic;

  -- TCDS to DAQ FPGA.
  signal tcds_daq_fpga_gth_tx_p : std_logic_vector(3 downto 0);
  signal tcds_daq_fpga_gth_tx_n : std_logic_vector(3 downto 0);
  signal tcds_daq_fpga_gth_rx_p : std_logic_vector(3 downto 0);
  signal tcds_daq_fpga_gth_rx_n : std_logic_vector(3 downto 0);

  -- TCDS to DAQ FPGA MGT reference clocks.
  signal tcds_daq_fpga_gth_refclk0 : std_logic_vector(0 downto 0);
  signal tcds_daq_fpga_gth_refclk1 : std_logic_vector(0 downto 0);

  signal tcds_daq_fpga_gth_northrefclk0 : std_logic_vector(0 downto 0);
  signal tcds_daq_fpga_gth_northrefclk1 : std_logic_vector(0 downto 0);
  signal tcds_daq_fpga_gth_southrefclk0 : std_logic_vector(0 downto 0);
  signal tcds_daq_fpga_gth_southrefclk1 : std_logic_vector(0 downto 0);

  signal tcds_daq_fpga_gth_refclk00 : std_logic_vector(0 downto 0);
  signal tcds_daq_fpga_gth_refclk10 : std_logic_vector(0 downto 0);
  signal tcds_daq_fpga_gth_refclk01 : std_logic_vector(0 downto 0);
  signal tcds_daq_fpga_gth_refclk11 : std_logic_vector(0 downto 0);

  signal tcds_daq_fpga_gth_northrefclk00 : std_logic_vector(0 downto 0);
  signal tcds_daq_fpga_gth_northrefclk10 : std_logic_vector(0 downto 0);
  signal tcds_daq_fpga_gth_northrefclk01 : std_logic_vector(0 downto 0);
  signal tcds_daq_fpga_gth_northrefclk11 : std_logic_vector(0 downto 0);
  signal tcds_daq_fpga_gth_southrefclk00 : std_logic_vector(0 downto 0);
  signal tcds_daq_fpga_gth_southrefclk10 : std_logic_vector(0 downto 0);
  signal tcds_daq_fpga_gth_southrefclk01 : std_logic_vector(0 downto 0);
  signal tcds_daq_fpga_gth_southrefclk11 : std_logic_vector(0 downto 0);

  -- TCDS backplane signals.
  signal tcds_backplane_gth_tx_p : std_logic_vector(15 downto 0);
  signal tcds_backplane_gth_tx_n : std_logic_vector(15 downto 0);
  signal tcds_backplane_gth_rx_p : std_logic_vector(15 downto 0);
  signal tcds_backplane_gth_rx_n : std_logic_vector(15 downto 0);

  signal tcds_backplane_gty_tx_p : std_logic_vector(15 downto 0);
  signal tcds_backplane_gty_tx_n : std_logic_vector(15 downto 0);
  signal tcds_backplane_gty_rx_p : std_logic_vector(15 downto 0);
  signal tcds_backplane_gty_rx_n : std_logic_vector(15 downto 0);

  -- TCDS backplane MGT reference clocks.
  signal tcds_backplane_gth_refclk0 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_refclk1 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_northrefclk0 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_northrefclk1 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_southrefclk0 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_southrefclk1 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_refclk00 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_refclk10 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_refclk01 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_refclk11 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_northrefclk00 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_northrefclk10 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_northrefclk01 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_northrefclk11 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_southrefclk00 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_southrefclk10 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_southrefclk01 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gth_southrefclk11 : std_logic_vector(3 downto 0);

  signal tcds_backplane_gty_refclk0 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_refclk1 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_northrefclk0 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_northrefclk1 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_southrefclk0 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_southrefclk1 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_refclk00 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_refclk10 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_refclk01 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_refclk11 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_northrefclk00 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_northrefclk10 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_northrefclk01 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_northrefclk11 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_southrefclk00 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_southrefclk10 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_southrefclk01 : std_logic_vector(3 downto 0);
  signal tcds_backplane_gty_southrefclk11 : std_logic_vector(3 downto 0);

begin

  ------------------------------------------
  -- Input buffers for general purpose clocks.
  ------------------------------------------
  ibufds_100mhz : IBUFDS
    port map (
      i => clk_gp_100mhz_p,
      ib => clk_gp_100mhz_n,
      o => clk_gp_100mhz
    );

  ------------------------------------------
  -- Input buffers for MGT reference clocks.
  ------------------------------------------
  ibufds_mgt227_refclk0 : IBUFDS_GTE4
    port map (
      i => mgt_refclk_gth_mgt227_rc0_p,
      ib => mgt_refclk_gth_mgt227_rc0_n,
      o => mgt227_refclk0,
      ceb => '0'
    );

  ibufds_mgt231_refclk0 : IBUFDS_GTE4
    port map (
      i => mgt_refclk_gth_mgt231_rc0_p,
      ib => mgt_refclk_gth_mgt231_rc0_n,
      o => mgt231_refclk0,
      ceb => '0'
    );

  ibufds_mgt128_refclk0 : IBUFDS_GTE4
    port map (
      i => mgt_refclk_gty_mgt128_rc0_p,
      ib => mgt_refclk_gty_mgt128_rc0_n,
      o => mgt128_refclk0,
      ceb => '0'
    );

  ibufds_mgt132_refclk0 : IBUFDS_GTE4
    port map (
      i => mgt_refclk_gty_mgt132_rc0_p,
      ib => mgt_refclk_gty_mgt132_rc0_n,
      o => mgt132_refclk0,
      ceb => '0'
    );

  ------------------------------------------
  -- Front-panel diagnostic leds.
  ------------------------------------------
  leds : entity work.dth_tcds_user_leds
    port map (
      user_led_top_left             => infra_status.pcie_link_locked_and_up,
      user_led_top_right_of_left    => infra_status.pcie_link_activity,
      user_led_top_left_of_right    => '0',
      user_led_top_right            => '0',
      user_led_bottom_left          => '0',
      user_led_bottom_right_of_left => '0',
      user_led_bottom_left_of_right => '0',
      user_led_bottom_right         => '0',
      user_led_connections          => user_leds
    );

  ------------------------------------------
  -- The GTH IBERT for the DAQ FPGA connects to MGT 232.
  ------------------------------------------
  ibert_tcds_daq_fpga_gth : entity work.ibert_tcds_daq_fpga_gth_10g
    port map (
      txp_o => tcds_daq_fpga_gth_tx_p,
      txn_o => tcds_daq_fpga_gth_tx_n,

      rxp_i => tcds_daq_fpga_gth_rx_p,
      rxn_i => tcds_daq_fpga_gth_rx_n,

      gtrefclk0_i => tcds_daq_fpga_gth_refclk0,
      gtrefclk1_i => tcds_daq_fpga_gth_refclk1,

      gtnorthrefclk0_i => tcds_daq_fpga_gth_northrefclk0,
      gtnorthrefclk1_i => tcds_daq_fpga_gth_northrefclk1,
      gtsouthrefclk0_i => tcds_daq_fpga_gth_southrefclk0,
      gtsouthrefclk1_i => tcds_daq_fpga_gth_southrefclk1,

      gtrefclk00_i => tcds_daq_fpga_gth_refclk00,
      gtrefclk10_i => tcds_daq_fpga_gth_refclk10,
      gtrefclk01_i => tcds_daq_fpga_gth_refclk01,
      gtrefclk11_i => tcds_daq_fpga_gth_refclk11,

      gtnorthrefclk00_i => tcds_daq_fpga_gth_northrefclk00,
      gtnorthrefclk10_i => tcds_daq_fpga_gth_northrefclk10,
      gtnorthrefclk01_i => tcds_daq_fpga_gth_northrefclk01,
      gtnorthrefclk11_i => tcds_daq_fpga_gth_northrefclk11,
      gtsouthrefclk00_i => tcds_daq_fpga_gth_southrefclk00,
      gtsouthrefclk10_i => tcds_daq_fpga_gth_southrefclk10,
      gtsouthrefclk01_i => tcds_daq_fpga_gth_southrefclk01,
      gtsouthrefclk11_i => tcds_daq_fpga_gth_southrefclk11,

      rxoutclk_o => open,
      clk => clk_gp_100mhz
    );

  ------------------------------------------
  -- The backplane GTH IBERT spans MGTs 226, 228, 230, and 233.
  ------------------------------------------
  option_ibert_gth_5g : if OPTION_IBERT_SPEED = IBERT_SPEED_5G generate
    ibert_tcds_backplane_gth : entity work.ibert_tcds_backplane_gth_5g
    port map (
      txp_o => tcds_backplane_gth_tx_p,
      txn_o => tcds_backplane_gth_tx_n,

      rxp_i => tcds_backplane_gth_rx_p,
      rxn_i => tcds_backplane_gth_rx_n,

      gtrefclk0_i => tcds_backplane_gth_refclk0,
      gtrefclk1_i => tcds_backplane_gth_refclk1,

      gtnorthrefclk0_i => tcds_backplane_gth_northrefclk0,
      gtnorthrefclk1_i => tcds_backplane_gth_northrefclk1,
      gtsouthrefclk0_i => tcds_backplane_gth_southrefclk0,
      gtsouthrefclk1_i => tcds_backplane_gth_southrefclk1,

      gtrefclk00_i => tcds_backplane_gth_refclk00,
      gtrefclk10_i => tcds_backplane_gth_refclk10,
      gtrefclk01_i => tcds_backplane_gth_refclk01,
      gtrefclk11_i => tcds_backplane_gth_refclk11,

      gtnorthrefclk00_i => tcds_backplane_gth_northrefclk00,
      gtnorthrefclk10_i => tcds_backplane_gth_northrefclk10,
      gtnorthrefclk01_i => tcds_backplane_gth_northrefclk01,
      gtnorthrefclk11_i => tcds_backplane_gth_northrefclk11,
      gtsouthrefclk00_i => tcds_backplane_gth_southrefclk00,
      gtsouthrefclk10_i => tcds_backplane_gth_southrefclk10,
      gtsouthrefclk01_i => tcds_backplane_gth_southrefclk01,
      gtsouthrefclk11_i => tcds_backplane_gth_southrefclk11,

      rxoutclk_o => open,
      clk => clk_gp_100mhz
    );
    end generate;

  option_ibert_gth_10g : if OPTION_IBERT_SPEED = IBERT_SPEED_10G generate
    ibert_tcds_backplane_gth : entity work.ibert_tcds_backplane_gth_10g
    port map (
      txp_o => tcds_backplane_gth_tx_p,
      txn_o => tcds_backplane_gth_tx_n,

      rxp_i => tcds_backplane_gth_rx_p,
      rxn_i => tcds_backplane_gth_rx_n,

      gtrefclk0_i => tcds_backplane_gth_refclk0,
      gtrefclk1_i => tcds_backplane_gth_refclk1,

      gtnorthrefclk0_i => tcds_backplane_gth_northrefclk0,
      gtnorthrefclk1_i => tcds_backplane_gth_northrefclk1,
      gtsouthrefclk0_i => tcds_backplane_gth_southrefclk0,
      gtsouthrefclk1_i => tcds_backplane_gth_southrefclk1,

      gtrefclk00_i => tcds_backplane_gth_refclk00,
      gtrefclk10_i => tcds_backplane_gth_refclk10,
      gtrefclk01_i => tcds_backplane_gth_refclk01,
      gtrefclk11_i => tcds_backplane_gth_refclk11,

      gtnorthrefclk00_i => tcds_backplane_gth_northrefclk00,
      gtnorthrefclk10_i => tcds_backplane_gth_northrefclk10,
      gtnorthrefclk01_i => tcds_backplane_gth_northrefclk01,
      gtnorthrefclk11_i => tcds_backplane_gth_northrefclk11,
      gtsouthrefclk00_i => tcds_backplane_gth_southrefclk00,
      gtsouthrefclk10_i => tcds_backplane_gth_southrefclk10,
      gtsouthrefclk01_i => tcds_backplane_gth_southrefclk01,
      gtsouthrefclk11_i => tcds_backplane_gth_southrefclk11,

      rxoutclk_o => open,
      clk => clk_gp_100mhz
    );
  end generate;

  -- MGT232-0, not connected.
--  tcds_daq_fpga_gth_tx_p(0) <= '0';
--  tcds_daq_fpga_gth_tx_n(0) <= '0';
  tcds_daq_fpga_gth_rx_p(0) <= '0';
  tcds_daq_fpga_gth_rx_n(0) <= '0';
  -- MGT232-1, DAQ FPGA.
  tcds_daq_fpga_tx_p <= tcds_daq_fpga_gth_tx_p(1);
  tcds_daq_fpga_tx_n <= tcds_daq_fpga_gth_tx_n(1);
  tcds_daq_fpga_gth_rx_p(1) <= tcds_daq_fpga_rx_p;
  tcds_daq_fpga_gth_rx_n(1) <= tcds_daq_fpga_rx_n;
  -- MGT232-2, not connected.
--  tcds_daq_fpga_gth_tx_p(2) <= '0';
--  tcds_daq_fpga_gth_tx_n(2) <= '0';
  tcds_daq_fpga_gth_rx_p(2) <= '0';
  tcds_daq_fpga_gth_rx_n(2) <= '0';
  -- MGT232-3, not connected.
--  tcds_daq_fpga_gth_tx_p(3) <= '0';
--  tcds_daq_fpga_gth_tx_n(3) <= '0';
  tcds_daq_fpga_gth_rx_p(3) <= '0';
  tcds_daq_fpga_gth_rx_n(3) <= '0';

  -- MGT226-0, not connected.
--  tcds_backplane_gth_tx_p(0) <= '0';
--  tcds_backplane_gth_tx_n(0) <= '0';
  tcds_backplane_gth_rx_p(0) <= '0';
  tcds_backplane_gth_rx_n(0) <= '0';
  -- MGT226-1, not connected.
--  tcds_backplane_gth_tx_p(1) <= '0';
--  tcds_backplane_gth_tx_n(1) <= '0';
  tcds_backplane_gth_rx_p(1) <= '0';
  tcds_backplane_gth_rx_n(1) <= '0';
  -- MGT226-2, not connected.
--  tcds_backplane_gth_tx_p(2) <= '0';
--  tcds_backplane_gth_tx_n(2) <= '0';
  tcds_backplane_gth_rx_p(2) <= '0';
  tcds_backplane_gth_rx_n(2) <= '0';
  -- MGT226-3, backplane slot 5.
  tcds_backplane_slot5_tx_p <= tcds_backplane_gth_tx_p(3);
  tcds_backplane_slot5_tx_n <= tcds_backplane_gth_tx_n(3);
  tcds_backplane_gth_rx_p(3) <= tcds_backplane_slot5_rx_p;
  tcds_backplane_gth_rx_n(3) <= tcds_backplane_slot5_rx_n;

  -- MGT228-0, not connected.
--  tcds_backplane_gth_tx_p(4) <= '0';
--  tcds_backplane_gth_tx_n(4) <= '0';
  tcds_backplane_gth_rx_p(4) <= '0';
  tcds_backplane_gth_rx_n(4) <= '0';
  -- MGT228-1, backplane slot 3.
  tcds_backplane_slot3_tx_p <= tcds_backplane_gth_tx_p(5);
  tcds_backplane_slot3_tx_n <= tcds_backplane_gth_tx_n(5);
  tcds_backplane_gth_rx_p(5) <= tcds_backplane_slot3_rx_p;
  tcds_backplane_gth_rx_n(5) <= tcds_backplane_slot3_rx_n;
  -- MGT228-2, not connected.
--  tcds_backplane_gth_tx_p(6) <= '0';
--  tcds_backplane_gth_tx_n(6) <= '0';
  tcds_backplane_gth_rx_p(6) <= '0';
  tcds_backplane_gth_rx_n(6) <= '0';
  -- MGT228-3, backplane slot 7.
  tcds_backplane_slot7_tx_p <= tcds_backplane_gth_tx_p(7);
  tcds_backplane_slot7_tx_n <= tcds_backplane_gth_tx_n(7);
  tcds_backplane_gth_rx_p(7) <= tcds_backplane_slot7_rx_p;
  tcds_backplane_gth_rx_n(7) <= tcds_backplane_slot7_rx_n;

  -- MGT230-0, not connected.
--  tcds_backplane_gth_tx_p(8) <= '0';
--  tcds_backplane_gth_tx_n(8) <= '0';
  tcds_backplane_gth_rx_p(8) <= '0';
  tcds_backplane_gth_rx_n(8) <= '0';
  -- MGT230-1, backplane slot 6.
  tcds_backplane_slot6_tx_p <= tcds_backplane_gth_tx_p(9);
  tcds_backplane_slot6_tx_n <= tcds_backplane_gth_tx_n(9);
  tcds_backplane_gth_rx_p(9) <= tcds_backplane_slot6_rx_p;
  tcds_backplane_gth_rx_n(9) <= tcds_backplane_slot6_rx_n;
  -- MGT230-2, not connected.
--  tcds_backplane_gth_tx_p(10) <= '0';
--  tcds_backplane_gth_tx_n(10) <= '0';
  tcds_backplane_gth_rx_p(10) <= '0';
  tcds_backplane_gth_rx_n(10) <= '0';
  -- MGT230-3, backplane slot 4.
  tcds_backplane_slot4_tx_p <= tcds_backplane_gth_tx_p(11);
  tcds_backplane_slot4_tx_n <= tcds_backplane_gth_tx_n(11);
  tcds_backplane_gth_rx_p(11) <= tcds_backplane_slot4_rx_p;
  tcds_backplane_gth_rx_n(11) <= tcds_backplane_slot4_rx_n;

  -- MGT233-0, not connected.
--  tcds_backplane_gth_tx_p(12) <= '0';
--  tcds_backplane_gth_tx_n(12) <= '0';
  tcds_backplane_gth_rx_p(12) <= '0';
  tcds_backplane_gth_rx_n(12) <= '0';
  -- MGT233-1, backplane slot 2.
  tcds_backplane_slot2_tx_p <= tcds_backplane_gth_tx_p(13);
  tcds_backplane_slot2_tx_n <= tcds_backplane_gth_tx_n(13);
  tcds_backplane_gth_rx_p(13) <= tcds_backplane_slot2_rx_p;
  tcds_backplane_gth_rx_n(13) <= tcds_backplane_slot2_rx_n;
  -- MGT233-2, not connected.
--  tcds_backplane_gth_tx_p(14) <= '0';
--  tcds_backplane_gth_tx_n(14) <= '0';
  tcds_backplane_gth_rx_p(14) <= '0';
  tcds_backplane_gth_rx_n(14) <= '0';
  -- MGT233-3, not connected.
--  tcds_backplane_gth_tx_p(15) <= '0';
--  tcds_backplane_gth_tx_n(15) <= '0';
  tcds_backplane_gth_rx_p(15) <= '0';
  tcds_backplane_gth_rx_n(15) <= '0';

  -- MGT232, using MGT231-refclk0.
  tcds_daq_fpga_gth_refclk0(0) <= '0';
  tcds_daq_fpga_gth_refclk1(0) <= '0';
  tcds_daq_fpga_gth_northrefclk0(0) <= mgt231_refclk0;
  tcds_daq_fpga_gth_northrefclk1(0) <= '0';
  tcds_daq_fpga_gth_southrefclk0(0) <= '0';
  tcds_daq_fpga_gth_southrefclk1(0) <= '0';
  tcds_daq_fpga_gth_refclk00(0) <= '0';
  tcds_daq_fpga_gth_refclk10(0) <= '0';
  tcds_daq_fpga_gth_refclk01(0) <= '0';
  tcds_daq_fpga_gth_refclk11(0) <= '0';
  tcds_daq_fpga_gth_northrefclk00(0) <= mgt231_refclk0;
  tcds_daq_fpga_gth_northrefclk10(0) <= '0';
  tcds_daq_fpga_gth_northrefclk01(0) <= '0';
  tcds_daq_fpga_gth_northrefclk11(0) <= '0';
  tcds_daq_fpga_gth_southrefclk00(0) <= '0';
  tcds_daq_fpga_gth_southrefclk10(0) <= '0';
  tcds_daq_fpga_gth_southrefclk01(0) <= '0';
  tcds_daq_fpga_gth_southrefclk11(0) <= '0';

  -- MGT226, using MGT227-refclk0.
  tcds_backplane_gth_refclk0(0) <= '0';
  tcds_backplane_gth_refclk1(0) <= '0';
  tcds_backplane_gth_northrefclk0(0) <= '0';
  tcds_backplane_gth_northrefclk1(0) <= '0';
  tcds_backplane_gth_southrefclk0(0) <= mgt227_refclk0;
  tcds_backplane_gth_southrefclk1(0) <= '0';
  tcds_backplane_gth_refclk00(0) <= '0';
  tcds_backplane_gth_refclk10(0) <= '0';
  tcds_backplane_gth_refclk01(0) <= '0';
  tcds_backplane_gth_refclk11(0) <= '0';
  tcds_backplane_gth_northrefclk00(0) <= '0';
  tcds_backplane_gth_northrefclk10(0) <= '0';
  tcds_backplane_gth_northrefclk01(0) <= '0';
  tcds_backplane_gth_northrefclk11(0) <= '0';
  tcds_backplane_gth_southrefclk00(0) <= mgt227_refclk0;
  tcds_backplane_gth_southrefclk10(0) <= '0';
  tcds_backplane_gth_southrefclk01(0) <= '0';
  tcds_backplane_gth_southrefclk11(0) <= '0';

  -- MGT228, using MGT227-refclk0.
  tcds_backplane_gth_refclk0(1) <= '0';
  tcds_backplane_gth_refclk1(1) <= '0';
  tcds_backplane_gth_northrefclk0(1) <= mgt227_refclk0;
  tcds_backplane_gth_northrefclk1(1) <= '0';
  tcds_backplane_gth_southrefclk0(1) <= '0';
  tcds_backplane_gth_southrefclk1(1) <= '0';
  tcds_backplane_gth_refclk00(1) <= '0';
  tcds_backplane_gth_refclk10(1) <= '0';
  tcds_backplane_gth_refclk01(1) <= '0';
  tcds_backplane_gth_refclk11(1) <= '0';
  tcds_backplane_gth_northrefclk00(1) <= mgt227_refclk0;
  tcds_backplane_gth_northrefclk10(1) <= '0';
  tcds_backplane_gth_northrefclk01(1) <= '0';
  tcds_backplane_gth_northrefclk11(1) <= '0';
  tcds_backplane_gth_southrefclk00(1) <= '0';
  tcds_backplane_gth_southrefclk10(1) <= '0';
  tcds_backplane_gth_southrefclk01(1) <= '0';
  tcds_backplane_gth_southrefclk11(1) <= '0';

  -- MGT230, using MGT231-refclk0.
  tcds_backplane_gth_refclk0(2) <= '0';
  tcds_backplane_gth_refclk1(2) <= '0';
  tcds_backplane_gth_northrefclk0(2) <= '0';
  tcds_backplane_gth_northrefclk1(2) <= '0';
  tcds_backplane_gth_southrefclk0(2) <= mgt231_refclk0;
  tcds_backplane_gth_southrefclk1(2) <= '0';
  tcds_backplane_gth_refclk00(2) <= '0';
  tcds_backplane_gth_refclk10(2) <= '0';
  tcds_backplane_gth_refclk01(2) <= '0';
  tcds_backplane_gth_refclk11(2) <= '0';
  tcds_backplane_gth_northrefclk00(2) <= '0';
  tcds_backplane_gth_northrefclk10(2) <= '0';
  tcds_backplane_gth_northrefclk01(2) <= '0';
  tcds_backplane_gth_northrefclk11(2) <= '0';
  tcds_backplane_gth_southrefclk00(2) <= mgt231_refclk0;
  tcds_backplane_gth_southrefclk10(2) <= '0';
  tcds_backplane_gth_southrefclk01(2) <= '0';
  tcds_backplane_gth_southrefclk11(2) <= '0';

  -- MGT233, using MGT231-refclk0.
  tcds_backplane_gth_refclk0(3) <= '0';
  tcds_backplane_gth_refclk1(3) <= '0';
  tcds_backplane_gth_northrefclk0(3) <= mgt231_refclk0;
  tcds_backplane_gth_northrefclk1(3) <= '0';
  tcds_backplane_gth_southrefclk0(3) <= '0';
  tcds_backplane_gth_southrefclk1(3) <= '0';
  tcds_backplane_gth_refclk00(3) <= '0';
  tcds_backplane_gth_refclk10(3) <= '0';
  tcds_backplane_gth_refclk01(3) <= '0';
  tcds_backplane_gth_refclk11(3) <= '0';
  tcds_backplane_gth_northrefclk00(3) <= mgt231_refclk0;
  tcds_backplane_gth_northrefclk10(3) <= '0';
  tcds_backplane_gth_northrefclk01(3) <= '0';
  tcds_backplane_gth_northrefclk11(3) <= '0';
  tcds_backplane_gth_southrefclk00(3) <= '0';
  tcds_backplane_gth_southrefclk10(3) <= '0';
  tcds_backplane_gth_southrefclk01(3) <= '0';
  tcds_backplane_gth_southrefclk11(3) <= '0';

  ------------------------------------------
  -- The backplane GTY IBERT spans MGTs 127, 129, 131, and 132.
  ------------------------------------------
  option_ibert_gty_5g : if OPTION_IBERT_SPEED = IBERT_SPEED_5G generate
  ibert_tcds_backplane_gty : entity work.ibert_tcds_backplane_gty_5g
    port map (
      txp_o => tcds_backplane_gty_tx_p,
      txn_o => tcds_backplane_gty_tx_n,

      rxp_i => tcds_backplane_gty_rx_p,
      rxn_i => tcds_backplane_gty_rx_n,

      gtrefclk0_i => tcds_backplane_gty_refclk0,
      gtrefclk1_i => tcds_backplane_gty_refclk1,

      gtnorthrefclk0_i => tcds_backplane_gty_northrefclk0,
      gtnorthrefclk1_i => tcds_backplane_gty_northrefclk1,
      gtsouthrefclk0_i => tcds_backplane_gty_southrefclk0,
      gtsouthrefclk1_i => tcds_backplane_gty_southrefclk1,

      gtrefclk00_i => tcds_backplane_gty_refclk00,
      gtrefclk10_i => tcds_backplane_gty_refclk10,
      gtrefclk01_i => tcds_backplane_gty_refclk01,
      gtrefclk11_i => tcds_backplane_gty_refclk11,

      gtnorthrefclk00_i => tcds_backplane_gty_northrefclk00,
      gtnorthrefclk10_i => tcds_backplane_gty_northrefclk10,
      gtnorthrefclk01_i => tcds_backplane_gty_northrefclk01,
      gtnorthrefclk11_i => tcds_backplane_gty_northrefclk11,
      gtsouthrefclk00_i => tcds_backplane_gty_southrefclk00,
      gtsouthrefclk10_i => tcds_backplane_gty_southrefclk10,
      gtsouthrefclk01_i => tcds_backplane_gty_southrefclk01,
      gtsouthrefclk11_i => tcds_backplane_gty_southrefclk11,

      clk => clk_gp_100mhz
  );
  end generate;

  option_ibert_gty_10g : if OPTION_IBERT_SPEED = IBERT_SPEED_10G generate
 ibert_tcds_backplane_gty : entity work.ibert_tcds_backplane_gty_10g
    port map (
      txp_o => tcds_backplane_gty_tx_p,
      txn_o => tcds_backplane_gty_tx_n,

      rxp_i => tcds_backplane_gty_rx_p,
      rxn_i => tcds_backplane_gty_rx_n,

      gtrefclk0_i => tcds_backplane_gty_refclk0,
      gtrefclk1_i => tcds_backplane_gty_refclk1,

      gtnorthrefclk0_i => tcds_backplane_gty_northrefclk0,
      gtnorthrefclk1_i => tcds_backplane_gty_northrefclk1,
      gtsouthrefclk0_i => tcds_backplane_gty_southrefclk0,
      gtsouthrefclk1_i => tcds_backplane_gty_southrefclk1,

      gtrefclk00_i => tcds_backplane_gty_refclk00,
      gtrefclk10_i => tcds_backplane_gty_refclk10,
      gtrefclk01_i => tcds_backplane_gty_refclk01,
      gtrefclk11_i => tcds_backplane_gty_refclk11,

      gtnorthrefclk00_i => tcds_backplane_gty_northrefclk00,
      gtnorthrefclk10_i => tcds_backplane_gty_northrefclk10,
      gtnorthrefclk01_i => tcds_backplane_gty_northrefclk01,
      gtnorthrefclk11_i => tcds_backplane_gty_northrefclk11,
      gtsouthrefclk00_i => tcds_backplane_gty_southrefclk00,
      gtsouthrefclk10_i => tcds_backplane_gty_southrefclk10,
      gtsouthrefclk01_i => tcds_backplane_gty_southrefclk01,
      gtsouthrefclk11_i => tcds_backplane_gty_southrefclk11,

      clk => clk_gp_100mhz
  );
  end generate;

  -- MGT127-0, backplane slot 9.
  tcds_backplane_slot9_tx_p <= tcds_backplane_gty_tx_p(0);
  tcds_backplane_slot9_tx_n <= tcds_backplane_gty_tx_n(0);
  tcds_backplane_gty_rx_p(0) <= tcds_backplane_slot9_rx_p;
  tcds_backplane_gty_rx_n(0) <= tcds_backplane_slot9_rx_n;
  -- MGT127-1, not connected.
--  tcds_backplane_gty_tx_p(1) <= '0';
--  tcds_backplane_gty_tx_n(1) <= '0';
  tcds_backplane_gty_rx_p(1) <= '0';
  tcds_backplane_gty_rx_n(1) <= '0';
  -- MGT127-2, backplane slot 11.
  tcds_backplane_slot11_tx_p <= tcds_backplane_gty_tx_p(2);
  tcds_backplane_slot11_tx_n <= tcds_backplane_gty_tx_n(2);
  tcds_backplane_gty_rx_p(2) <= tcds_backplane_slot11_rx_p;
  tcds_backplane_gty_rx_n(2) <= tcds_backplane_slot11_rx_n;
  -- MGT127-3, not connected.
--  tcds_backplane_gty_tx_p(3) <= '0';
--  tcds_backplane_gty_tx_n(3) <= '0';
  tcds_backplane_gty_rx_p(3) <= '0';
  tcds_backplane_gty_rx_n(3) <= '0';

  -- MGT129-0, backplane slot 8.
  tcds_backplane_slot8_tx_p <= tcds_backplane_gty_tx_p(4);
  tcds_backplane_slot8_tx_n <= tcds_backplane_gty_tx_n(4);
  tcds_backplane_gty_rx_p(4) <= tcds_backplane_slot8_rx_p;
  tcds_backplane_gty_rx_n(4) <= tcds_backplane_slot8_rx_n;
  -- MGT129-1, not connected.
--  tcds_backplane_gty_tx_p(5) <= '0';
--  tcds_backplane_gty_tx_n(5) <= '0';
  tcds_backplane_gty_rx_p(5) <= '0';
  tcds_backplane_gty_rx_n(5) <= '0';
  -- MGT129-2, backplane slot 10.
  tcds_backplane_slot10_tx_p <= tcds_backplane_gty_tx_p(6);
  tcds_backplane_slot10_tx_n <= tcds_backplane_gty_tx_n(6);
  tcds_backplane_gty_rx_p(6) <= tcds_backplane_slot10_rx_p;
  tcds_backplane_gty_rx_n(6) <= tcds_backplane_slot10_rx_n;
  -- MGT129-3, not connected.
--  tcds_backplane_gty_tx_p(7) <= '0';
--  tcds_backplane_gty_tx_n(7) <= '0';
  tcds_backplane_gty_rx_p(7) <= '0';
  tcds_backplane_gty_rx_n(7) <= '0';

  -- MGT131-0, backplane slot 12.
  tcds_backplane_slot12_tx_p <= tcds_backplane_gty_tx_p(8);
  tcds_backplane_slot12_tx_n <= tcds_backplane_gty_tx_n(8);
  tcds_backplane_gty_rx_p(8) <= tcds_backplane_slot12_rx_p;
  tcds_backplane_gty_rx_n(8) <= tcds_backplane_slot12_rx_n;
  -- MGT131-1, not connected.
--  tcds_backplane_gty_tx_p(9) <= '0';
--  tcds_backplane_gty_tx_n(9) <= '0';
  tcds_backplane_gty_rx_p(9) <= '0';
  tcds_backplane_gty_rx_n(9) <= '0';
  -- MGT131-2, not connected.
--  tcds_backplane_gty_tx_p(10) <= '0';
--  tcds_backplane_gty_tx_n(10) <= '0';
  tcds_backplane_gty_rx_p(10) <= '0';
  tcds_backplane_gty_rx_n(10) <= '0';
  -- MGT131-3, backplane slot 13.
  tcds_backplane_slot13_tx_p <= tcds_backplane_gty_tx_p(11);
  tcds_backplane_slot13_tx_n <= tcds_backplane_gty_tx_n(11);
  tcds_backplane_gty_rx_p(11) <= tcds_backplane_slot13_rx_p;
  tcds_backplane_gty_rx_n(11) <= tcds_backplane_slot13_rx_n;

  -- MGT132-0, backplane slot 14.
  tcds_backplane_slot14_tx_p <= tcds_backplane_gty_tx_p(12);
  tcds_backplane_slot14_tx_n <= tcds_backplane_gty_tx_n(12);
  tcds_backplane_gty_rx_p(12) <= tcds_backplane_slot14_rx_p;
  tcds_backplane_gty_rx_n(12) <= tcds_backplane_slot14_rx_n;
  -- MGT132-1, not connected.
--  tcds_backplane_gty_tx_p(13) <= '0';
--  tcds_backplane_gty_tx_n(13) <= '0';
  tcds_backplane_gty_rx_p(13) <= '0';
  tcds_backplane_gty_rx_n(13) <= '0';
  -- MGT132-2, not connected.
--  tcds_backplane_gty_tx_p(14) <= '0';
--  tcds_backplane_gty_tx_n(14) <= '0';
  tcds_backplane_gty_rx_p(14) <= '0';
  tcds_backplane_gty_rx_n(14) <= '0';
  -- MGT132-3, not connected.
--  tcds_backplane_gty_tx_p(15) <= '0';
--  tcds_backplane_gty_tx_n(15) <= '0';
  tcds_backplane_gty_rx_p(15) <= '0';
  tcds_backplane_gty_rx_n(15) <= '0';

  -- MGT127, using MGT128-refclk0.
  tcds_backplane_gty_refclk0(0) <= '0';
  tcds_backplane_gty_refclk1(0) <= '0';
  tcds_backplane_gty_northrefclk0(0) <= '0';
  tcds_backplane_gty_northrefclk1(0) <= '0';
  tcds_backplane_gty_southrefclk0(0) <= mgt128_refclk0;
  tcds_backplane_gty_southrefclk1(0) <= '0';
  tcds_backplane_gty_refclk00(0) <= '0';
  tcds_backplane_gty_refclk10(0) <= '0';
  tcds_backplane_gty_refclk01(0) <= '0';
  tcds_backplane_gty_refclk11(0) <= '0';
  tcds_backplane_gty_northrefclk00(0) <= '0';
  tcds_backplane_gty_northrefclk10(0) <= '0';
  tcds_backplane_gty_northrefclk01(0) <= '0';
  tcds_backplane_gty_northrefclk11(0) <= '0';
  tcds_backplane_gty_southrefclk00(0) <= mgt128_refclk0;
  tcds_backplane_gty_southrefclk10(0) <= '0';
  tcds_backplane_gty_southrefclk01(0) <= '0';
  tcds_backplane_gty_southrefclk11(0) <= '0';

  -- MGT129, using MGT128-refclk0.
  tcds_backplane_gty_refclk0(1) <= '0';
  tcds_backplane_gty_refclk1(1) <= '0';
  tcds_backplane_gty_northrefclk0(1) <= mgt128_refclk0;
  tcds_backplane_gty_northrefclk1(1) <= '0';
  tcds_backplane_gty_southrefclk0(1) <= '0';
  tcds_backplane_gty_southrefclk1(1) <= '0';
  tcds_backplane_gty_refclk00(1) <= '0';
  tcds_backplane_gty_refclk10(1) <= '0';
  tcds_backplane_gty_refclk01(1) <= '0';
  tcds_backplane_gty_refclk11(1) <= '0';
  tcds_backplane_gty_northrefclk00(1) <= mgt128_refclk0;
  tcds_backplane_gty_northrefclk10(1) <= '0';
  tcds_backplane_gty_northrefclk01(1) <= '0';
  tcds_backplane_gty_northrefclk11(1) <= '0';
  tcds_backplane_gty_southrefclk00(1) <= '0';
  tcds_backplane_gty_southrefclk10(1) <= '0';
  tcds_backplane_gty_southrefclk01(1) <= '0';
  tcds_backplane_gty_southrefclk11(1) <= '0';

  -- MGT131, using MGT132-refclk0.
  tcds_backplane_gty_refclk0(2) <= '0';
  tcds_backplane_gty_refclk1(2) <= '0';
  tcds_backplane_gty_northrefclk0(2) <= '0';
  tcds_backplane_gty_northrefclk1(2) <= '0';
  tcds_backplane_gty_southrefclk0(2) <= mgt132_refclk0;
  tcds_backplane_gty_southrefclk1(2) <= '0';
  tcds_backplane_gty_refclk00(2) <= '0';
  tcds_backplane_gty_refclk10(2) <= '0';
  tcds_backplane_gty_refclk01(2) <= '0';
  tcds_backplane_gty_refclk11(2) <= '0';
  tcds_backplane_gty_northrefclk00(2) <= '0';
  tcds_backplane_gty_northrefclk10(2) <= '0';
  tcds_backplane_gty_northrefclk01(2) <= '0';
  tcds_backplane_gty_northrefclk11(2) <= '0';
  tcds_backplane_gty_southrefclk00(2) <= mgt132_refclk0;
  tcds_backplane_gty_southrefclk10(2) <= '0';
  tcds_backplane_gty_southrefclk01(2) <= '0';
  tcds_backplane_gty_southrefclk11(2) <= '0';

  -- MGT132, using MGT132-refclk0.
  tcds_backplane_gty_refclk0(3) <= mgt132_refclk0;
  tcds_backplane_gty_refclk1(3) <= '0';
  tcds_backplane_gty_northrefclk0(3) <= '0';
  tcds_backplane_gty_northrefclk1(3) <= '0';
  tcds_backplane_gty_southrefclk0(3) <= '0';
  tcds_backplane_gty_southrefclk1(3) <= '0';
  tcds_backplane_gty_refclk00(3) <= mgt132_refclk0;
  tcds_backplane_gty_refclk10(3) <= '0';
  tcds_backplane_gty_refclk01(3) <= '0';
  tcds_backplane_gty_refclk11(3) <= '0';
  tcds_backplane_gty_northrefclk00(3) <= '0';
  tcds_backplane_gty_northrefclk10(3) <= '0';
  tcds_backplane_gty_northrefclk01(3) <= '0';
  tcds_backplane_gty_northrefclk11(3) <= '0';
  tcds_backplane_gty_southrefclk00(3) <= '0';
  tcds_backplane_gty_southrefclk10(3) <= '0';
  tcds_backplane_gty_southrefclk01(3) <= '0';
  tcds_backplane_gty_southrefclk11(3) <= '0';

  ------------------------------------------

end rtl;

--======================================================================