--======================================================================
-- Golden/fall-back image.
--======================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

use work.ipbus.all;

use work.dth_tcds_infra_status.all;

--==================================================

entity dth_tcds_user_main is
  port (
    clk_ipb : in std_logic;
    rst_ipb : in std_logic;
    ipb_in : in ipb_wbus;
    ipb_out : out ipb_rbus;
    clk_aux : in std_logic;
    rst_aux : in std_logic;
    nuke : in std_logic;
    soft_rst : in std_logic;

    -- Status summary from the board infrastructure.
    infra_status : in dth_tcds_infra_status;

    -- General purpose clocks from IC51.
    clk_gp_100mhz_p : in std_logic;
    clk_gp_100mhz_n : in std_logic;
    clk_gp_125mhz_p : in std_logic;
    clk_gp_125mhz_n : in std_logic;
    clk_gp_156_25mhz_p : in std_logic;
    clk_gp_156_25mhz_n : in std_logic;

    -- Bunch clocks coming from the two clock cleaners supplying the
    -- high-precision clock to the backplane.
    clk_40_backplane_lo_p : in std_logic;
    clk_40_backplane_lo_n : in std_logic;
    clk_40_backplane_hi_p : in std_logic;
    clk_40_backplane_hi_n : in std_logic;

    -- Bunch clock coming from the 'MGT' clock cleaner (typically
    -- regenerated from either the 40 MHz or the 320 MHz backplane
    -- clock).
    clk_40_backplane_regen_p : in std_logic;
    clk_40_backplane_regen_n : in std_logic;

    -- GTH reference clocks.
    mgt_refclk_gth_mgt226_rc0_p : in std_logic;
    mgt_refclk_gth_mgt226_rc0_n : in std_logic;
    mgt_refclk_gth_mgt227_rc0_p : in std_logic;
    mgt_refclk_gth_mgt227_rc0_n : in std_logic;
    mgt_refclk_gth_mgt231_rc0_p : in std_logic;
    mgt_refclk_gth_mgt231_rc0_n : in std_logic;
    mgt_refclk_gth_mgt232_rc0_p : in std_logic;
    mgt_refclk_gth_mgt232_rc0_n : in std_logic;
    mgt_refclk_gth_mgt233_rc0_p : in std_logic;
    mgt_refclk_gth_mgt233_rc0_n : in std_logic;
    mgt_refclk_gth_mgt234_rc0_p : in std_logic;
    mgt_refclk_gth_mgt234_rc0_n : in std_logic;

    -- GTY reference clocks.
    mgt_refclk_gty_mgt127_rc0_p : in std_logic;
    mgt_refclk_gty_mgt127_rc0_n : in std_logic;
    mgt_refclk_gty_mgt128_rc0_p : in std_logic;
    mgt_refclk_gty_mgt128_rc0_n : in std_logic;
    mgt_refclk_gty_mgt130_rc0_p : in std_logic;
    mgt_refclk_gty_mgt130_rc0_n : in std_logic;
    mgt_refclk_gty_mgt132_rc0_p : in std_logic;
    mgt_refclk_gty_mgt132_rc0_n : in std_logic;
    mgt_refclk_gty_mgt132_rc1_p : in std_logic;
    mgt_refclk_gty_mgt132_rc1_n : in std_logic;
    mgt_refclk_gty_mgt133_rc0_p : in std_logic;
    mgt_refclk_gty_mgt133_rc0_n : in std_logic;
    mgt_refclk_gty_mgt134_rc0_p : in std_logic;
    mgt_refclk_gty_mgt134_rc0_n : in std_logic;

    -- -- Clock selection lines.
    -- -- - The select line of IC84, switching between the GTH and GTY
    -- --   recovered MGT clocks.
    -- sel_recclk_out : out std_logic;

    -- Recovered bunch clock outputs to the primary and secondary
    -- clock cleaners.
    tcds_clk_40_out_pri_p : out std_logic;
    tcds_clk_40_out_pri_n : out std_logic;
    tcds_clk_40_out_sec_p : out std_logic;
    tcds_clk_40_out_sec_n : out std_logic;

    -- Status/diagnostic LEDs.
    user_leds : out std_logic_vector(7 downto 0);

    -- Front-panel TCDS SFPs.
    tcds_frontpanel_a_tx_p : out std_logic;
    tcds_frontpanel_a_tx_n : out std_logic;
    tcds_frontpanel_a_rx_p : in std_logic;
    tcds_frontpanel_a_rx_n : in std_logic;
    --
    tcds_frontpanel_b_tx_p : out std_logic;
    tcds_frontpanel_b_tx_n : out std_logic;
    tcds_frontpanel_b_rx_p : in std_logic;
    tcds_frontpanel_b_rx_n : in std_logic;

    -- DAQ FPGA TCDS connection.
    tcds_daq_fpga_tx_p : out std_logic;
    tcds_daq_fpga_tx_n : out std_logic;
    tcds_daq_fpga_rx_p : in std_logic;
    tcds_daq_fpga_rx_n : in std_logic;

    -- Backplane TCDS signals.
    -- NOTE: Slot 1 (i.e., index 0) is the first hub slot, in which the DTH sits.
    tcds_backplane_slot2_tx_p : out std_logic;
    tcds_backplane_slot2_tx_n : out std_logic;
    tcds_backplane_slot2_rx_p : in std_logic;
    tcds_backplane_slot2_rx_n : in std_logic;
    --
    tcds_backplane_slot3_tx_p : out std_logic;
    tcds_backplane_slot3_tx_n : out std_logic;
    tcds_backplane_slot3_rx_p : in std_logic;
    tcds_backplane_slot3_rx_n : in std_logic;
    --
    tcds_backplane_slot4_tx_p : out std_logic;
    tcds_backplane_slot4_tx_n : out std_logic;
    tcds_backplane_slot4_rx_p : in std_logic;
    tcds_backplane_slot4_rx_n : in std_logic;
    --
    tcds_backplane_slot5_tx_p : out std_logic;
    tcds_backplane_slot5_tx_n : out std_logic;
    tcds_backplane_slot5_rx_p : in std_logic;
    tcds_backplane_slot5_rx_n : in std_logic;
    --
    tcds_backplane_slot6_tx_p : out std_logic;
    tcds_backplane_slot6_tx_n : out std_logic;
    tcds_backplane_slot6_rx_p : in std_logic;
    tcds_backplane_slot6_rx_n : in std_logic;
    --
    tcds_backplane_slot7_tx_p : out std_logic;
    tcds_backplane_slot7_tx_n : out std_logic;
    tcds_backplane_slot7_rx_p : in std_logic;
    tcds_backplane_slot7_rx_n : in std_logic;
    --
    tcds_backplane_slot8_tx_p : out std_logic;
    tcds_backplane_slot8_tx_n : out std_logic;
    tcds_backplane_slot8_rx_p : in std_logic;
    tcds_backplane_slot8_rx_n : in std_logic;
    --
    tcds_backplane_slot9_tx_p : out std_logic;
    tcds_backplane_slot9_tx_n : out std_logic;
    tcds_backplane_slot9_rx_p : in std_logic;
    tcds_backplane_slot9_rx_n : in std_logic;
    --
    tcds_backplane_slot10_tx_p : out std_logic;
    tcds_backplane_slot10_tx_n : out std_logic;
    tcds_backplane_slot10_rx_p : in std_logic;
    tcds_backplane_slot10_rx_n : in std_logic;
    --
    tcds_backplane_slot11_tx_p : out std_logic;
    tcds_backplane_slot11_tx_n : out std_logic;
    tcds_backplane_slot11_rx_p : in std_logic;
    tcds_backplane_slot11_rx_n : in std_logic;
    --
    tcds_backplane_slot12_tx_p : out std_logic;
    tcds_backplane_slot12_tx_n : out std_logic;
    tcds_backplane_slot12_rx_p : in std_logic;
    tcds_backplane_slot12_rx_n : in std_logic;
    --
    tcds_backplane_slot13_tx_p : out std_logic;
    tcds_backplane_slot13_tx_n : out std_logic;
    tcds_backplane_slot13_rx_p : in std_logic;
    tcds_backplane_slot13_rx_n : in std_logic;
    --
    tcds_backplane_slot14_tx_p : out std_logic;
    tcds_backplane_slot14_tx_n : out std_logic;
    tcds_backplane_slot14_rx_p : in std_logic;
    tcds_backplane_slot14_rx_n : in std_logic
  );

end dth_tcds_user_main;

--==================================================

architecture rtl of dth_tcds_user_main is

  -- Some signals related to the diagnostic leds.
  signal led_cnt : unsigned(23 downto 0);
  signal led_dir : std_logic;
  signal led_vec : std_logic_vector(3 downto 0);

begin

  ------------------------------------------
  -- Output buffers for the 40 MHz clocks to the primary and secondary
  -- clock cleaners.
  ------------------------------------------

  obufds_clk_40mhz_pri : obufds
   port map (
     i  => '0',
     o  => tcds_clk_40_out_pri_p,
     ob => tcds_clk_40_out_pri_n
   );

  obufds_clk_40mhz_sec : obufds
   port map (
     i  => '0',
     o  => tcds_clk_40_out_sec_p,
     ob => tcds_clk_40_out_sec_n
   );

  ------------------------------------------
  -- Front-panel diagnostic leds.
  ------------------------------------------

  -- Just a fairly typical sweeping-led signature on the front-panel,
  -- so one can easily recognize the golden image.
  led_sweep : process(clk_ipb)
  begin
    if rising_edge(clk_ipb) then
      if rst_ipb = '1' then
        led_cnt <= (others => '0');
        led_dir <= '0';
        led_vec <= (0 => '1', others => '0');
      elsif led_cnt(led_cnt'high) = '1' then
        led_cnt <= (others => '0');
        led_dir <= led_dir;
        if led_dir = '0' then
          led_vec <= led_vec(led_vec'high-1 downto led_vec'low) & '0';
        else
          led_vec <= '0' & led_vec(led_vec'high downto led_vec'low+1);
        end if;
      elsif (led_dir = '0' and led_vec(led_vec'high) = '1') or
        (led_dir = '1' and led_vec(led_vec'low) = '1') then
        led_dir <= not led_dir;
      else
        led_cnt <= led_cnt + 1;
        led_dir <= led_dir;
        led_vec <= led_vec;
      end if;
    end if;
  end process;

  ------------------------------------------

  leds : entity work.dth_tcds_user_leds
    port map (
      user_led_top_left => infra_status.pcie_link_locked_and_up,
      user_led_top_right_of_left => infra_status.pcie_link_activity,
      user_led_top_left_of_right => '0',
      user_led_top_right => '0',
      user_led_bottom_left => led_vec(3),
      user_led_bottom_right_of_left => led_vec(2),
      user_led_bottom_left_of_right => led_vec(1),
      user_led_bottom_right => led_vec(0),
      user_led_connections => user_leds
    );

  ------------------------------------------

end rtl;

--======================================================================