--====================================================================== -- Default DTH image. --====================================================================== library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- use ieee.math_real."ceil"; -- use ieee.math_real."log2"; library unisim; use unisim.vcomponents.all; use work.ipbus.all; use work.ipbus_reg_types.all; use work.tclink_lpgbt10G_pkg.all; use work.constants_tcds2.all; use work.dth_tcds_infra_status.all; use work.ipbus_decode_dth_tcds_user_main.all; use work.tcds2_choice_speed.all; use work.tcds2_link_pkg.all; use work.tcds2_link_speed_pkg.all; use work.tcds2_streams_pkg.all; --================================================== entity dth_tcds_user_main is port ( clk_ipb : in std_logic; rst_ipb : in std_logic; ipb_in : in ipb_wbus; ipb_out : out ipb_rbus; clk_aux : in std_logic; rst_aux : in std_logic; nuke : in std_logic; soft_rst : in std_logic; -- Status summary from the board infrastructure. infra_status : in dth_tcds_infra_status; -- General purpose clocks from IC51. clk_gp_100mhz_p : in std_logic; clk_gp_100mhz_n : in std_logic; clk_gp_125mhz_p : in std_logic; clk_gp_125mhz_n : in std_logic; clk_gp_156_25mhz_p : in std_logic; clk_gp_156_25mhz_n : in std_logic; -- Bunch clocks coming from the two clock cleaners supplying the -- high-precision clock to the backplane. clk_40_backplane_lo_p : in std_logic; clk_40_backplane_lo_n : in std_logic; clk_40_backplane_hi_p : in std_logic; clk_40_backplane_hi_n : in std_logic; -- Bunch clock coming from the 'MGT' clock cleaner (typically -- regenerated from either the 40 MHz or the 320 MHz backplane -- clock). clk_40_backplane_regen_p : in std_logic; clk_40_backplane_regen_n : in std_logic; -- GTH reference clocks. mgt_refclk_gth_mgt226_rc0_p : in std_logic; mgt_refclk_gth_mgt226_rc0_n : in std_logic; mgt_refclk_gth_mgt227_rc0_p : in std_logic; mgt_refclk_gth_mgt227_rc0_n : in std_logic; mgt_refclk_gth_mgt231_rc0_p : in std_logic; mgt_refclk_gth_mgt231_rc0_n : in std_logic; mgt_refclk_gth_mgt232_rc0_p : in std_logic; mgt_refclk_gth_mgt232_rc0_n : in std_logic; mgt_refclk_gth_mgt233_rc0_p : in std_logic; mgt_refclk_gth_mgt233_rc0_n : in std_logic; mgt_refclk_gth_mgt234_rc0_p : in std_logic; mgt_refclk_gth_mgt234_rc0_n : in std_logic; -- GTY reference clocks. mgt_refclk_gty_mgt127_rc0_p : in std_logic; mgt_refclk_gty_mgt127_rc0_n : in std_logic; mgt_refclk_gty_mgt128_rc0_p : in std_logic; mgt_refclk_gty_mgt128_rc0_n : in std_logic; mgt_refclk_gty_mgt130_rc0_p : in std_logic; mgt_refclk_gty_mgt130_rc0_n : in std_logic; mgt_refclk_gty_mgt132_rc0_p : in std_logic; mgt_refclk_gty_mgt132_rc0_n : in std_logic; mgt_refclk_gty_mgt132_rc1_p : in std_logic; mgt_refclk_gty_mgt132_rc1_n : in std_logic; mgt_refclk_gty_mgt133_rc0_p : in std_logic; mgt_refclk_gty_mgt133_rc0_n : in std_logic; mgt_refclk_gty_mgt134_rc0_p : in std_logic; mgt_refclk_gty_mgt134_rc0_n : in std_logic; -- -- Clock selection lines. -- -- - The select line of IC84, switching between the GTH and GTY -- -- recovered MGT clocks. -- sel_recclk_out : out std_logic; -- Recovered bunch clock outputs to the primary and secondary -- clock cleaners. tcds_clk_40_out_pri_p : out std_logic; tcds_clk_40_out_pri_n : out std_logic; tcds_clk_40_out_sec_p : out std_logic; tcds_clk_40_out_sec_n : out std_logic; -- Status/diagnostic LEDs. user_leds : out std_logic_vector(7 downto 0); -- Front-panel TCDS SFPs. tcds_frontpanel_a_tx_p : out std_logic; tcds_frontpanel_a_tx_n : out std_logic; tcds_frontpanel_a_rx_p : in std_logic; tcds_frontpanel_a_rx_n : in std_logic; -- tcds_frontpanel_b_tx_p : out std_logic; tcds_frontpanel_b_tx_n : out std_logic; tcds_frontpanel_b_rx_p : in std_logic; tcds_frontpanel_b_rx_n : in std_logic; -- DAQ FPGA TCDS connection. tcds_daq_fpga_tx_p : out std_logic; tcds_daq_fpga_tx_n : out std_logic; tcds_daq_fpga_rx_p : in std_logic; tcds_daq_fpga_rx_n : in std_logic; -- Backplane TCDS signals. -- NOTE: Slot 1 (i.e., index 0) is the first hub slot, in which the DTH sits. tcds_backplane_slot2_tx_p : out std_logic; tcds_backplane_slot2_tx_n : out std_logic; tcds_backplane_slot2_rx_p : in std_logic; tcds_backplane_slot2_rx_n : in std_logic; -- tcds_backplane_slot3_tx_p : out std_logic; tcds_backplane_slot3_tx_n : out std_logic; tcds_backplane_slot3_rx_p : in std_logic; tcds_backplane_slot3_rx_n : in std_logic; -- tcds_backplane_slot4_tx_p : out std_logic; tcds_backplane_slot4_tx_n : out std_logic; tcds_backplane_slot4_rx_p : in std_logic; tcds_backplane_slot4_rx_n : in std_logic; -- tcds_backplane_slot5_tx_p : out std_logic; tcds_backplane_slot5_tx_n : out std_logic; tcds_backplane_slot5_rx_p : in std_logic; tcds_backplane_slot5_rx_n : in std_logic; -- tcds_backplane_slot6_tx_p : out std_logic; tcds_backplane_slot6_tx_n : out std_logic; tcds_backplane_slot6_rx_p : in std_logic; tcds_backplane_slot6_rx_n : in std_logic; -- tcds_backplane_slot7_tx_p : out std_logic; tcds_backplane_slot7_tx_n : out std_logic; tcds_backplane_slot7_rx_p : in std_logic; tcds_backplane_slot7_rx_n : in std_logic; -- tcds_backplane_slot8_tx_p : out std_logic; tcds_backplane_slot8_tx_n : out std_logic; tcds_backplane_slot8_rx_p : in std_logic; tcds_backplane_slot8_rx_n : in std_logic; -- tcds_backplane_slot9_tx_p : out std_logic; tcds_backplane_slot9_tx_n : out std_logic; tcds_backplane_slot9_rx_p : in std_logic; tcds_backplane_slot9_rx_n : in std_logic; -- tcds_backplane_slot10_tx_p : out std_logic; tcds_backplane_slot10_tx_n : out std_logic; tcds_backplane_slot10_rx_p : in std_logic; tcds_backplane_slot10_rx_n : in std_logic; -- tcds_backplane_slot11_tx_p : out std_logic; tcds_backplane_slot11_tx_n : out std_logic; tcds_backplane_slot11_rx_p : in std_logic; tcds_backplane_slot11_rx_n : in std_logic; -- tcds_backplane_slot12_tx_p : out std_logic; tcds_backplane_slot12_tx_n : out std_logic; tcds_backplane_slot12_rx_p : in std_logic; tcds_backplane_slot12_rx_n : in std_logic; -- tcds_backplane_slot13_tx_p : out std_logic; tcds_backplane_slot13_tx_n : out std_logic; tcds_backplane_slot13_rx_p : in std_logic; tcds_backplane_slot13_rx_n : in std_logic; -- tcds_backplane_slot14_tx_p : out std_logic; tcds_backplane_slot14_tx_n : out std_logic; tcds_backplane_slot14_rx_p : in std_logic; tcds_backplane_slot14_rx_n : in std_logic ); end dth_tcds_user_main; --================================================== architecture rtl of dth_tcds_user_main is -- BUG BUG BUG -- This does not belong here(?)... constant C_MASTER_NUMBER_CHANNELS : integer := 14; -- BUG BUG BUG end ------------------------------------------ -- IPBus read/write buses. ------------------------------------------ signal ipbw : ipb_wbus_array(N_SLAVES - 1 downto 0); signal ipbr : ipb_rbus_array(N_SLAVES - 1 downto 0); ------------------------------------------ -- -- Resets etc. ------------------------------------------ -- signal nuke_i : std_logic; -- signal soft_rst_i : std_logic; ------------------------------------------ -- Clock signals. ------------------------------------------ signal clk_gp_100mhz : std_logic; signal clk_gp_125mhz : std_logic; signal clk_gp_156_25mhz : std_logic; signal clk_40_backplane_lo : std_logic; signal clk_40_backplane_hi : std_logic; signal clk_40_tx : std_logic; signal clk_40_rx : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); ------------------------------------------ -- MGT reference clocks from the secondary clock cleaner. ------------------------------------------ signal mgt227_refclk0 : std_logic; signal mgt231_refclk0 : std_logic; signal mgt128_refclk0 : std_logic; signal mgt132_refclk0 : std_logic; signal mgt234_refclk0 : std_logic; signal mgt134_refclk0 : std_logic; ------------------------------------------ -- MGT reference clocks from the auxiliary clock generator. ------------------------------------------ -- signal mgt226_refclk0 : std_logic; -- signal mgt232_refclk0 : std_logic; -- signal mgt127_refclk0 : std_logic; -- signal mgt132_refclk1 : std_logic; -- signal mgt130_refclk0 : std_logic; -- signal mgt133_refclk0 : std_logic; ------------------------------------------ -- MGT reference clock from the MGT clock cleaner. ------------------------------------------ -- signal mgt233_refclk0 : std_logic; ------------------------------------------ -- Misc. ------------------------------------------ signal clkdiv_i : std_logic_vector(4 downto 0); ------------------------------------------ -- Signals related to the frontpanel TCDS B SFP loopback. ------------------------------------------ -- GTH RX out clock. signal rxoutclk : std_logic; signal rxoutclk_tmp : std_logic; -- Control and status registers for the frontpanel loopback. signal ctrl_frontpanel_loopback : ipb_reg_v(0 downto 0); signal stat_frontpanel_loopback : ipb_reg_v(0 downto 0); ------------------------------------------ -- Various TCDS2 signals. ------------------------------------------ -- TCDS2 TTC2/TTS2 signals from/to the local partition managers. signal ttc2_local_0 : tcds2_ttc2; signal tts2_local_0 : tcds2_tts2_value_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal ttc2_local_1 : tcds2_ttc2; signal tts2_local_1 : tcds2_tts2_value_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); -- TCDS2 TTC2/TTS2 signals from/to the global channels. signal ttc2_global_0 : tcds2_ttc2; signal tts2_global_0 : tcds2_tts2_value_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal ttc2_global_1 : tcds2_ttc2; signal tts2_global_1 : tcds2_tts2_value_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal ttc2_0 : tcds2_ttc2_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal tts2_0 : tcds2_tts2_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal ttc2_1 : tcds2_ttc2_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal tts2_1 : tcds2_tts2_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal tts2_joined_0 : tcds2_tts2_value_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal tts2_joined_1 : tcds2_tts2_value_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal tts2_masked_local_0 : tcds2_tts2_value_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal tts2_masked_local_1 : tcds2_tts2_value_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal tts2_masked_global_0 : tcds2_tts2_value_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal tts2_masked_global_1 : tcds2_tts2_value_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal tts2_enable_local_0 : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal tts2_enable_local_1 : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal tts2_enable_global_0 : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal tts2_enable_global_1 : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); type tcds2_frame_array is array(C_MASTER_NUMBER_CHANNELS downto 0) of tcds2_frame_t; signal ttc2_frame : tcds2_frame_array; signal tts2_frame : tcds2_frame_array; signal ttc2_frame_int : tcds2_frame_array; signal tts2_frame_int : tcds2_frame_array; ------------------------------------------ -- PRBS generator/checkers signals. ------------------------------------------ -- The PRBS polynomial. Notation: x^23 + x^18 + 1 (PRBS-23). constant C_PRBS_POLYNOMIAL : std_logic_vector(23 downto 0) := "100001000000000000000001"; -- PRBS generator polynomial seed. constant C_PRBS_SEED : std_logic_vector(C_PRBS_POLYNOMIAL'length - 2 downto 0) := (others => '1'); -- Number of correct received frames for PRBS checker to lock. constant C_PRBS_GOOD_FRAME_TO_LOCK : integer := 15; -- Number of incorrect received frames for PRBS checker to unlock. constant C_PRBS_BAD_FRAME_TO_UNLOCK : integer := 5; constant C_PRBS_FRAME_WIDTH : integer := C_TCDS2_FRAME_WIDTH; signal prbsgen_reset : std_logic; signal prbschk_reset : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal prbsgen_reset_manual : std_logic; signal prbschk_reset_manual : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); -- PRBS generator output data. signal prbsgen_frame : std_logic_vector(C_PRBS_FRAME_WIDTH - 1 downto 0); -- signal prbsgen_data_valid : std_logic; -- PRBS checkers signals. -- BUG BUG BUG -- This is defined elsewhere too. Needs a look. type user_data_array is array(natural range <>) of std_logic_vector(C_TCDS2_FRAME_WIDTH - 1 downto 0); -- BUG BUG BUG end signal prbschk_frame : user_data_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal prbschk_en : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal prbschk_gen : user_data_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal prbschk_error : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal prbschk_locked : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); type counter_array is array(C_MASTER_NUMBER_CHANNELS downto 0) of std_logic_vector(31 downto 0); signal prbschk_unlock_count : counter_array; -- Control and status registers for the PRBS generator/checkers. signal ctrl_prbs : ipb_reg_v(0 downto 0); -- NOTE: We need three registers per channel for the PRBS checkers -- (hence the '3 *') and one for the PRBS generator (hence the lack -- of the '- 1'). signal stat_prbs : ipb_reg_v(3 * C_MASTER_NUMBER_CHANNELS downto 0); ------------------------------------------ -- Signal and frame routing helpers. ------------------------------------------ -- For each of the two channels there are basically two connection -- options: -- - Global (i.e., coming in on the front panel SFP). -- - Local (i.e., in this firmware) partition manager. -- NOTE: Link test mode is routed at the frame (as opposed to the channel) -- level, and is handled separately. type bool_array is array(C_MASTER_NUMBER_CHANNELS downto 0) of boolean; signal is_tcds2_connection_global_0 : bool_array; signal is_tcds2_connection_global_1 : bool_array; signal tcds2_connections_tmp_0 : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal tcds2_connections_tmp_1 : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); -- Control and status signals. -- NOTE: One larger than the number of channels, so no '- 1'. signal ctrl_routing : ipb_reg_v(C_MASTER_NUMBER_CHANNELS downto 0); -- signal stat_routing : ipb_reg_v(0 downto 0); signal is_link_test_mode : bool_array; signal is_any_link_test_mode : boolean; signal is_link_test_mode_tmp : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); begin ------------------------------------------ -- IPBus address decoder. ------------------------------------------ fabric : entity work.ipbus_fabric_sel generic map ( NSLV => N_SLAVES, SEL_WIDTH => IPBUS_SEL_WIDTH ) port map ( ipb_in => ipb_in, ipb_out => ipb_out, sel => ipbus_sel_dth_tcds_user_main(ipb_in.ipb_addr), ipb_to_slaves => ipbw, ipb_from_slaves => ipbr ); ------------------------------------------ -- Input buffers for general purpose clocks. ------------------------------------------ ibufds_100mhz : ibufds port map ( i => clk_gp_100mhz_p, ib => clk_gp_100mhz_n, o => clk_gp_100mhz ); ibufds_125mhz : ibufds port map ( i => clk_gp_125mhz_p, ib => clk_gp_125mhz_n, o => clk_gp_125mhz ); ibufds_156_25mhz : ibufds port map ( i => clk_gp_156_25mhz_p, ib => clk_gp_156_25mhz_n, o => clk_gp_156_25mhz ); ------------------------------------------ -- Input buffers for the two 40 MHz clocks from the backplane clock -- cleaners. ------------------------------------------ ibufds_40mhz_backplane_lo : ibufds port map ( i => clk_40_backplane_lo_p, ib => clk_40_backplane_lo_n, o => clk_40_backplane_lo ); ibufds_40mhz_backplane_hi : ibufds port map ( i => clk_40_backplane_hi_p, ib => clk_40_backplane_hi_n, o => clk_40_backplane_hi ); ------------------------------------------ -- Input buffer for the 40 MHz clock regenerated from either the 40 -- MHz or the 320 MHz backplane clock. ------------------------------------------ -- ibufds_40mhz_backplane_regen : ibufds -- port map ( -- i => clk_40_backplane_regen_p, -- ib => clk_40_backplane_regen_n, -- o => clk_40_backplane_regen -- ); ------------------------------------------ -- Output buffers for the 40 MHz clocks to the primary and secondary -- clock cleaners. ------------------------------------------ obufds_clk_40mhz_pri : obufds port map ( i => '0', o => tcds_clk_40_out_pri_p, ob => tcds_clk_40_out_pri_n ); obufds_clk_40mhz_sec : obufds port map ( i => '0', o => tcds_clk_40_out_sec_p, ob => tcds_clk_40_out_sec_n ); ------------------------------------------ -- Input buffers for MGT reference clocks. ------------------------------------------ -- MGT227-rc0, from the secondary clock cleaner (out3). ibufds_mgt227_refclk0 : IBUFDS_GTE4 port map ( i => mgt_refclk_gth_mgt227_rc0_p, ib => mgt_refclk_gth_mgt227_rc0_n, o => mgt227_refclk0, ceb => '0' ); -- MGT231-rc0, from the secondary clock cleaner (out4). ibufds_mgt231_refclk0 : IBUFDS_GTE4 port map ( i => mgt_refclk_gth_mgt231_rc0_p, ib => mgt_refclk_gth_mgt231_rc0_n, o => mgt231_refclk0, ceb => '0' ); -- MGT128-rc0, from the secondary clock cleaner (out5). ibufds_mgt128_refclk0 : IBUFDS_GTE4 port map ( i => mgt_refclk_gty_mgt128_rc0_p, ib => mgt_refclk_gty_mgt128_rc0_n, o => mgt128_refclk0, ceb => '0' ); -- MGT132-rc0, from the secondary clock cleaner (out6). ibufds_mgt132_refclk0 : IBUFDS_GTE4 port map ( i => mgt_refclk_gty_mgt132_rc0_p, ib => mgt_refclk_gty_mgt132_rc0_n, o => mgt132_refclk0, ceb => '0' ); -- MGT234-rc0, from the secondary clock cleaner (out7). ibufds_mgt234_refclk0 : IBUFDS_GTE4 port map ( i => mgt_refclk_gth_mgt234_rc0_p, ib => mgt_refclk_gth_mgt234_rc0_n, o => mgt234_refclk0, ceb => '0' ); -- MGT134-rc0, from the secondary clock cleaner (out8). ibufds_mgt134_refclk0 : IBUFDS_GTE4 port map ( i => mgt_refclk_gty_mgt134_rc0_p, ib => mgt_refclk_gty_mgt134_rc0_n, o => mgt134_refclk0, ceb => '0' ); -- -- MGT226-rc0, from the auxiliary clock generator. -- ibufds_mgt226_refclk0 : IBUFDS_GTE4 -- port map ( -- i => mgt_refclk_gth_mgt226_rc0_p, -- ib => mgt_refclk_gth_mgt226_rc0_n, -- o => mgt226_refclk0, -- ceb => '0' -- ); -- -- MGT232-rc0, from the auxiliary clock generator. -- ibufds_mgt232_refclk0 : IBUFDS_GTE4 -- port map ( -- i => mgt_refclk_gth_mgt232_rc0_p, -- ib => mgt_refclk_gth_mgt232_rc0_n, -- o => mgt232_refclk0, -- ceb => '0' -- ); -- -- MGT127-rc0, from the auxiliary clock generator. -- ibufds_mgt127_refclk0 : IBUFDS_GTE4 -- port map ( -- i => mgt_refclk_gty_mgt127_rc0_p, -- ib => mgt_refclk_gty_mgt127_rc0_n, -- o => mgt127_refclk0, -- ceb => '0' -- ); -- -- MGT132-rc0, from the auxiliary clock generator. -- ibufds_mgt132_refclk1 : IBUFDS_GTE4 -- port map ( -- i => mgt_refclk_gty_mgt132_rc1_p, -- ib => mgt_refclk_gty_mgt132_rc1_n, -- o => mgt132_refclk1, -- ceb => '0' -- ); -- -- MGT130-rc0, from the auxiliary clock generator. -- ibufds_mgt130_refclk0 : IBUFDS_GTE4 -- port map ( -- i => mgt_refclk_gty_mgt130_rc0_p, -- ib => mgt_refclk_gty_mgt130_rc0_n, -- o => mgt130_refclk0, -- ceb => '0' -- ); -- -- MGT133-rc0, from the auxiliary clock generator. -- ibufds_mgt133_refclk0 : IBUFDS_GTE4 -- port map ( -- i => mgt_refclk_gty_mgt133_rc0_p, -- ib => mgt_refclk_gty_mgt133_rc0_n, -- o => mgt133_refclk0, -- ceb => '0' -- ); -- -- MGT reference clock from the MGT clock cleaner. -- ibufds_mgt233_refclk0 : IBUFDS_GTE4 -- port map ( -- i => mgt_refclk_gth_mgt233_rc0_p, -- ib => mgt_refclk_gth_mgt233_rc0_n, -- o => mgt233_refclk0, -- ceb => '0' -- ); ------------------------------------------ -- Front-panel diagnostic leds. ------------------------------------------ leds : entity work.dth_tcds_user_leds port map ( user_led_top_left => infra_status.pcie_link_locked_and_up, user_led_top_right_of_left => infra_status.pcie_link_activity, user_led_top_left_of_right => '0', user_led_top_right => '0', user_led_bottom_left => '0', user_led_bottom_right_of_left => '0', user_led_bottom_left_of_right => '0', user_led_bottom_right => '0', user_led_connections => user_leds ); ------------------------------------------ -- Frequency counters to keep an eye on some of the clock signals. ------------------------------------------ freq_divs : entity work.freq_ctr_div generic map ( N_CLK => clkdiv_i'length ) port map ( -- General purpose clocks (from the auxiliary clock generator). clk(0) => clk_gp_100mhz, clk(1) => clk_gp_125mhz, clk(2) => clk_gp_156_25mhz, -- The two 40 MHz clocks from the backplane clock cleaners. clk(3) => clk_40_backplane_lo, clk(4) => clk_40_backplane_hi, -- -- The 40 MHz recovered clock from the TCDS2 backplane link. -- clk(5) => clk_40_rx, clkdiv => clkdiv_i ); freq_cntrs : entity work.ipbus_freq_ctr generic map ( N_CLK => clkdiv_i'length ) port map ( clk => clk_ipb, rst => rst_ipb, ipb_in => ipbw(N_SLV_FREQUENCY_COUNTERS), ipb_out => ipbr(N_SLV_FREQUENCY_COUNTERS), clkdiv => clkdiv_i ); ------------------------------------------ -- Loopback MGT on the frontpanel TCDS A SFP. Just for debugging of -- the link from the 'GT' to the DTH for now. ------------------------------------------ loopback_tcds_frontpanel_a : entity work.loopback_tcds_frontpanel_a port map ( clk_ipb => clk_ipb, rst_ipb => rst_ipb, ipb_in => ipbw(N_SLV_LOOPBACK_TCDS_FRONTPANEL_A), ipb_out => ipbr(N_SLV_LOOPBACK_TCDS_FRONTPANEL_A), clk_gp_100mhz => clk_gp_100mhz, mgt134_refclk0_320mhz => mgt134_refclk0, tcds_frontpanel_a_tx_p => tcds_frontpanel_a_tx_p, tcds_frontpanel_a_tx_n => tcds_frontpanel_a_tx_n, tcds_frontpanel_a_rx_p => tcds_frontpanel_a_rx_p, tcds_frontpanel_a_rx_n => tcds_frontpanel_a_rx_n, rxoutclk => open ); ------------------------------------------ -- Loopback MGT on the frontpanel TCDS B SFP. Just so we can receive -- an incoming clock from the captain. ------------------------------------------ loopback_tcds_frontpanel_b : entity work.loopback_tcds_frontpanel_b port map ( clk_ipb => clk_ipb, rst_ipb => rst_ipb, ipb_in => ipbw(N_SLV_LOOPBACK_TCDS_FRONTPANEL_B), ipb_out => ipbr(N_SLV_LOOPBACK_TCDS_FRONTPANEL_B), clk_gp_100mhz => clk_gp_100mhz, mgt234_refclk0_320mhz => mgt234_refclk0, tcds_frontpanel_b_tx_p => tcds_frontpanel_b_tx_p, tcds_frontpanel_b_tx_n => tcds_frontpanel_b_tx_n, tcds_frontpanel_b_rx_p => tcds_frontpanel_b_rx_p, tcds_frontpanel_b_rx_n => tcds_frontpanel_b_rx_n, rxoutclk => rxoutclk_tmp ); bufg_rxoutclk : bufg_gt port map ( i => rxoutclk_tmp, o => rxoutclk, ce => '1', cemask => '0', clr => '0', clrmask => '0', div => b"000" ); ------------------------------------------ -- The 40 MHz TX clock is the one cascading down from the primary -- clock cleaner. clk_40_tx <= clk_40_backplane_lo; ------------------------------------------ -- Temporary global connections. Will be connected to the -- front-panel TCDS2 input once that is implemented. ------------------------------------------ ttc2_global_0 <= C_TCDS2_TTC2_NULL; ttc2_global_1 <= C_TCDS2_TTC2_NULL; ------------------------------------------ -- TCDS2 partition manager 0. ------------------------------------------ partition_manager_0 : entity work.partition_manager generic map ( G_PARTITION_MANAGER_ID => 0, G_NUM_PARTITIONS => C_MASTER_NUMBER_CHANNELS ) port map ( clk_ipb => clk_ipb, rst_ipb => rst_ipb, ipb_in => ipbw(N_SLV_PARTITION_MANAGER_0), ipb_out => ipbr(N_SLV_PARTITION_MANAGER_0), clk_40 => clk_40_tx, ttc2_o => ttc2_local_0, tts2_i => tts2_local_0 ); ------------------------------------------ -- TCDS2 partition manager 1. ------------------------------------------ -- In 5G link speed mode there is no room for the data from the -- second partition manager. if_partition_manager_1 : if C_TCDS2_LINK_SPEED = TCDS2_LINK_SPEED_10G generate partition_manager_1 : entity work.partition_manager generic map ( G_PARTITION_MANAGER_ID => 1, G_NUM_PARTITIONS => C_MASTER_NUMBER_CHANNELS ) port map ( clk_ipb => clk_ipb, rst_ipb => rst_ipb, ipb_in => ipbw(N_SLV_PARTITION_MANAGER_1), ipb_out => ipbr(N_SLV_PARTITION_MANAGER_1), clk_40 => clk_40_tx, ttc2_o => ttc2_local_1, tts2_i => tts2_local_1 ); end generate; ------------------------------------------ -- PRBS generator (one common) and PRBS checkers (one per channel). ------------------------------------------ -- PRBS generator. prbs_gen : entity work.prbs_gen generic map ( G_PARAL_FACTOR => C_PRBS_FRAME_WIDTH, G_PRBS_POLYNOMIAL => C_PRBS_POLYNOMIAL ) port map ( clk_i => clk_40_tx, reset_i => prbsgen_reset, en_i => '1', seed_i => C_PRBS_SEED, load_i => '0', data_o => prbsgen_frame, data_valid_o => open --prbsgen_data_valid ); generate_prbs_chk : for i in C_MASTER_NUMBER_CHANNELS - 1 downto 0 generate prbs_chk : entity work.prbs_chk generic map ( G_PARAL_FACTOR => C_PRBS_FRAME_WIDTH, G_PRBS_POLYNOMIAL => C_PRBS_POLYNOMIAL, G_GOOD_FRAME_TO_LOCK => C_PRBS_GOOD_FRAME_TO_LOCK, G_BAD_FRAME_TO_UNLOCK => C_PRBS_BAD_FRAME_TO_UNLOCK ) port map ( clk_i => clk_40_rx(i), reset_i => prbschk_reset(i), en_i => '1', data_i => prbschk_frame(i), data_o => prbschk_gen(i), error_o => prbschk_error(i), locked_o => prbschk_locked(i) ); -- Each PRBS checker has a corresponding unlock counter. prbs_chk_unlock_cnt : entity work.unlock_counter generic map ( G_WIDTH => 32 ) port map ( clk => clk_40_rx(i), rst => prbschk_reset(i), locked => prbschk_locked(i), unlock_count => prbschk_unlock_count(i) ); end generate; -- In normal operation the PRBS generator and checkers are kept -- under reset. In link test mode they can be manually reset if -- needed. prbsgen_reset <= '1' when not is_any_link_test_mode else prbsgen_reset_manual; generate_prbschk_reset : for i in C_MASTER_NUMBER_CHANNELS - 1 downto 0 generate prbschk_reset(i) <= '1' when not is_link_test_mode(i) else prbschk_reset_manual(i); end generate; -- Control and status for the PRBS generator and checkers. csr_prbs : entity work.ipbus_ctrlreg_v generic map ( N_CTRL => ctrl_prbs'length, N_STAT => stat_prbs'length ) port map ( clk => clk_ipb, reset => rst_ipb, ipbus_in => ipbw(N_SLV_CSR_PRBS), ipbus_out => ipbr(N_SLV_CSR_PRBS), q => ctrl_prbs, d => stat_prbs ); prbsgen_reset_manual <= ctrl_prbs(0)(0); prbschk_reset_manual <= ctrl_prbs(0)(prbschk_reset_manual'length downto 1); -- Quick-n-dirty spy windows on the PRBS data. Helpful during -- debugging to see if things are running or not. stat_prbs(0) <= prbsgen_frame(31 downto 0); generate_csr_prbs_assignment : for i in C_MASTER_NUMBER_CHANNELS - 1 downto 0 generate -- Error flag. stat_prbs(3 * i + 1)(0) <= prbschk_error(i); -- Lock flag. stat_prbs(3 * i + 1)(1) <= prbschk_locked(i); -- The corresponding unlock count. stat_prbs(3 * i + 2) <= prbschk_unlock_count(i); -- Window on incoming PRBS data to check. stat_prbs(3 * i + 3)(15 downto 0) <= prbschk_frame(i)(15 downto 0); -- Window on PRBS data generated by the checker in response to the -- incoming data. stat_prbs(3 * i + 3)(31 downto 16) <= prbschk_gen(i)(15 downto 0); end generate; ------------------------------------------ -- CSR for TTC2 and TTS2 frame and channel routing. ------------------------------------------ csr_routing : entity work.ipbus_ctrlreg_v generic map ( N_CTRL => ctrl_routing'length, N_STAT => 0 --stat_routing'length ) port map ( clk => clk_ipb, reset => rst_ipb, ipbus_in => ipbw(N_SLV_CSR_ROUTING), ipbus_out => ipbr(N_SLV_CSR_ROUTING), q => ctrl_routing, d => open --stat_routing ); is_link_test_mode_tmp <= ctrl_routing(0)(is_link_test_mode_tmp'range); generate_tcds2_connections_tmp : for i in C_MASTER_NUMBER_CHANNELS - 1 downto 0 generate tcds2_connections_tmp_0(i) <= ctrl_routing(i + 1)(0); tcds2_connections_tmp_1(i) <= ctrl_routing(i + 1)(1); end generate; ------------------------------------------ -- TTC2 and TTS2 frame routing. ------------------------------------------ is_any_link_test_mode <= false when unsigned(is_link_test_mode_tmp) = 0 else true; generate_test_mode_flags : for i in C_MASTER_NUMBER_CHANNELS - 1 downto 0 generate is_link_test_mode(i) <= True when is_link_test_mode_tmp(i) = '1' else False; end generate; generate_frame_routing : for i in C_MASTER_NUMBER_CHANNELS - 1 downto 0 generate -- TX. ttc2_frame(i) <= prbsgen_frame when is_link_test_mode(i) else ttc2_frame_int(i); -- RX. tts2_frame_int(i) <= C_TCDS2_FRAME_NULL when is_link_test_mode(i) else tts2_frame(i); prbschk_frame(i) <= tts2_frame(i) when is_link_test_mode(i) else C_TCDS2_FRAME_NULL; end generate; ------------------------------------------ -- TTC2 routing. ------------------------------------------ generate_connection_flags : for i in C_MASTER_NUMBER_CHANNELS - 1 downto 0 generate is_tcds2_connection_global_0(i) <= True when tcds2_connections_tmp_0(i) = '1' else False; is_tcds2_connection_global_1(i) <= True when tcds2_connections_tmp_1(i) = '1' else False; end generate; generate_ttc2_routing : for i in C_MASTER_NUMBER_CHANNELS - 1 downto 0 generate ttc2_0(i) <= ttc2_global_0 when is_tcds2_connection_global_0(i) else ttc2_local_0; ttc2_1(i) <= ttc2_global_1 when is_tcds2_connection_global_1(i) else ttc2_local_1; end generate; ------------------------------------------ -- TTS2 routing. ------------------------------------------ tts2_joiner_0 : entity work.tts2_joiner generic map ( G_NUMBER_OF_INPUTS => C_MASTER_NUMBER_CHANNELS ) port map ( tts2_in => tts2_0, tts2_out => tts2_joined_0 ); tts2_joiner_1 : entity work.tts2_joiner generic map ( G_NUMBER_OF_INPUTS => C_MASTER_NUMBER_CHANNELS ) port map ( tts2_in => tts2_1, tts2_out => tts2_joined_1 ); tts2_mask_local_0 : entity work.tts2_ignore_mask generic map ( G_NUMBER_OF_INPUTS => C_MASTER_NUMBER_CHANNELS ) port map ( tts2_in_enable => tts2_enable_local_0, tts2_in => tts2_joined_0, tts2_out => tts2_masked_local_0 ); tts2_mask_local_1 : entity work.tts2_ignore_mask generic map ( G_NUMBER_OF_INPUTS => C_MASTER_NUMBER_CHANNELS ) port map ( tts2_in_enable => tts2_enable_local_1, tts2_in => tts2_joined_1, tts2_out => tts2_masked_local_1 ); tts2_mask_global_0 : entity work.tts2_ignore_mask generic map ( G_NUMBER_OF_INPUTS => C_MASTER_NUMBER_CHANNELS ) port map ( tts2_in_enable => tts2_enable_global_0, tts2_in => tts2_joined_0, tts2_out => tts2_masked_global_0 ); tts2_mask_global_1 : entity work.tts2_ignore_mask generic map ( G_NUMBER_OF_INPUTS => C_MASTER_NUMBER_CHANNELS ) port map ( tts2_in_enable => tts2_enable_global_1, tts2_in => tts2_joined_1, tts2_out => tts2_masked_global_1 ); generate_tts2_routing : for i in C_MASTER_NUMBER_CHANNELS - 1 downto 0 generate tts2_enable_local_0(i) <= '0' when is_tcds2_connection_global_0(i) else '1'; tts2_enable_local_1(i) <= '0' when is_tcds2_connection_global_1(i) else '1'; tts2_enable_global_0(i) <= '1' when is_tcds2_connection_global_0(i) else '0'; tts2_enable_global_1(i) <= '1' when is_tcds2_connection_global_1(i) else '0'; end generate; tts2_local_0 <= tts2_masked_local_0; tts2_local_1 <= tts2_masked_local_1; tts2_global_0 <= tts2_masked_global_0; tts2_global_1 <= tts2_masked_global_1; ------------------------------------------ -- TCDS2 TTC2 frame builders. (One per back-end channel.) ------------------------------------------ generate_ttc2_frame_builders : for i in C_MASTER_NUMBER_CHANNELS - 1 downto 0 generate ttc2_frame_builder : entity work.ttc2_frame_builder generic map ( G_LINK_SPEED => C_TCDS2_LINK_SPEED ) port map ( stream0_i => ttc2_0(i), stream1_i => ttc2_1(i), ic_i => C_TCDS2_IC_NULL, ec_i => C_TCDS2_EC_NULL, lm_i => C_TCDS2_LM_NULL, frame_o => ttc2_frame_int(i) ); end generate; ------------------------------------------ -- TTS2 frame splitters. (One per back-end channel.) ------------------------------------------ generate_tts2_frame_splitters : for i in C_MASTER_NUMBER_CHANNELS - 1 downto 0 generate tts2_frame_splitter : entity work.tts2_frame_splitter generic map ( G_LINK_SPEED => C_TCDS2_LINK_SPEED ) port map ( frame_i => tts2_frame_int(i), stream0_o => tts2_0(i), stream1_o => tts2_1(i), ic_o => open, ec_o => open, lm_o => open ); end generate; -- ------------------------------------------ -- -- TTS2 ignore masks for the routing. (One for each local and global -- -- TCDS2 channel.) -- ------------------------------------------ -- tts2_mask_local_0 : entity work.tts2_ignore_mask -- generic map ( -- G_NUMBER_OF_INPUTS => 2 * C_MASTER_NUMBER_CHANNELS -- ) -- port map ( -- tts2_in_enable => tts2_in_enable_local_0, -- tts2_in => tts2_monster_array, -- tts2_out => tts2_monster_array_masked_local_0 -- ); -- tts2_mask_local_1 : entity work.tts2_ignore_mask -- generic map ( -- G_NUMBER_OF_INPUTS => 2 * C_MASTER_NUMBER_CHANNELS -- ) -- port map ( -- tts2_in_enable => tts2_in_enable_local_1, -- tts2_in => tts2_monster_array, -- tts2_out => tts2_monster_array_masked_local_1 -- ); -- tts2_mask_global_0 : entity work.tts2_ignore_mask -- generic map ( -- G_NUMBER_OF_INPUTS => 2 * C_MASTER_NUMBER_CHANNELS -- ) -- port map ( -- tts2_in_enable => tts2_in_enable_global_0, -- tts2_in => tts2_monster_array, -- tts2_out => tts2_monster_array_masked_global_0 -- ); -- tts2_mask_global_1 : entity work.tts2_ignore_mask -- generic map ( -- G_NUMBER_OF_INPUTS => 2 * C_MASTER_NUMBER_CHANNELS -- ) -- port map ( -- tts2_in_enable => tts2_in_enable_global_1, -- tts2_in => tts2_monster_array, -- tts2_out => tts2_monster_array_masked_global_1 -- ); -- ------------------------------------------ -- -- TTS2 ORs. (One for each local and global TCDS2 channel.) -- ------------------------------------------ -- tts2_or_local_0 : entity work.tts2_prioritised_or -- generic map ( -- G_NUMBER_OF_INPUTS => 2 * C_MASTER_NUMBER_CHANNELS -- ) -- port map ( -- tts_in => tts2_monster_array_masked_local_0tts2_monster_array, -- tts_or_out => tts2_or_out_local_0 -- ); -- tts2_or_local_1 : entity work.tts2_prioritised_or -- generic map ( -- G_NUMBER_OF_INPUTS => 2 * C_MASTER_NUMBER_CHANNELS -- ) -- port map ( -- tts_in => tts2_monster_array_masked_local_1tts2_monster_array, -- tts_or_out => tts2_or_out_local_1 -- ); -- tts2_or_global_0 : entity work.tts2_prioritised_or -- generic map ( -- G_NUMBER_OF_INPUTS => 2 * C_MASTER_NUMBER_CHANNELS -- ) -- port map ( -- tts_in => tts2_monster_array_masked_global_0tts2_monster_array, -- tts_or_out => tts2_or_out_global_0 -- ); -- tts2_or_global_1 : entity work.tts2_prioritised_or -- generic map ( -- G_NUMBER_OF_INPUTS => 2 * C_MASTER_NUMBER_CHANNELS -- ) -- port map ( -- tts_in => tts2_monster_array_masked_global_1tts2_monster_array, -- tts_or_out => tts2_or_out_global_1 -- ); ------------------------------------------ -- TCDS2 back-end interface (grouping all channels). ------------------------------------------ dth_tcds2_backend_interface : entity work.dth_tcds2_backend_interface generic map ( G_LINK_SPEED => C_TCDS2_LINK_SPEED ) port map ( clk_ipb => clk_ipb, rst_ipb => rst_ipb, ipb_in => ipbw(N_SLV_BACKENDS_INTERFACE), ipb_out => ipbr(N_SLV_BACKENDS_INTERFACE), ------------ clk_gp_125mhz => clk_gp_125mhz, clk_40_tx => clk_40_tx, clk_40_rx => clk_40_rx, mgt_refclk_slot2 => mgt234_refclk0, mgt_refclk_slot3 => mgt227_refclk0, mgt_refclk_slot4 => mgt231_refclk0, mgt_refclk_slot5 => mgt227_refclk0, mgt_refclk_slot6 => mgt231_refclk0, mgt_refclk_slot7 => mgt227_refclk0, mgt_refclk_slot8 => mgt128_refclk0, mgt_refclk_slot9 => mgt128_refclk0, mgt_refclk_slot10 => mgt128_refclk0, mgt_refclk_slot11 => mgt128_refclk0, mgt_refclk_slot12 => mgt132_refclk0, mgt_refclk_slot13 => mgt132_refclk0, mgt_refclk_slot14 => mgt132_refclk0, mgt_refclk_daq_fpga => mgt231_refclk0, ------------ tcds2_backplane_slot2_tx_p => tcds_backplane_slot2_tx_p, tcds2_backplane_slot2_tx_n => tcds_backplane_slot2_tx_n, tcds2_backplane_slot2_rx_p => tcds_backplane_slot2_rx_p, tcds2_backplane_slot2_rx_n => tcds_backplane_slot2_rx_n, tcds2_backplane_slot3_tx_p => tcds_backplane_slot3_tx_p, tcds2_backplane_slot3_tx_n => tcds_backplane_slot3_tx_n, tcds2_backplane_slot3_rx_p => tcds_backplane_slot3_rx_p, tcds2_backplane_slot3_rx_n => tcds_backplane_slot3_rx_n, tcds2_backplane_slot4_tx_p => tcds_backplane_slot4_tx_p, tcds2_backplane_slot4_tx_n => tcds_backplane_slot4_tx_n, tcds2_backplane_slot4_rx_p => tcds_backplane_slot4_rx_p, tcds2_backplane_slot4_rx_n => tcds_backplane_slot4_rx_n, tcds2_backplane_slot5_tx_p => tcds_backplane_slot5_tx_p, tcds2_backplane_slot5_tx_n => tcds_backplane_slot5_tx_n, tcds2_backplane_slot5_rx_p => tcds_backplane_slot5_rx_p, tcds2_backplane_slot5_rx_n => tcds_backplane_slot5_rx_n, tcds2_backplane_slot6_tx_p => tcds_backplane_slot6_tx_p, tcds2_backplane_slot6_tx_n => tcds_backplane_slot6_tx_n, tcds2_backplane_slot6_rx_p => tcds_backplane_slot6_rx_p, tcds2_backplane_slot6_rx_n => tcds_backplane_slot6_rx_n, tcds2_backplane_slot7_tx_p => tcds_backplane_slot7_tx_p, tcds2_backplane_slot7_tx_n => tcds_backplane_slot7_tx_n, tcds2_backplane_slot7_rx_p => tcds_backplane_slot7_rx_p, tcds2_backplane_slot7_rx_n => tcds_backplane_slot7_rx_n, tcds2_backplane_slot8_tx_p => tcds_backplane_slot8_tx_p, tcds2_backplane_slot8_tx_n => tcds_backplane_slot8_tx_n, tcds2_backplane_slot8_rx_p => tcds_backplane_slot8_rx_p, tcds2_backplane_slot8_rx_n => tcds_backplane_slot8_rx_n, tcds2_backplane_slot9_tx_p => tcds_backplane_slot9_tx_p, tcds2_backplane_slot9_tx_n => tcds_backplane_slot9_tx_n, tcds2_backplane_slot9_rx_p => tcds_backplane_slot9_rx_p, tcds2_backplane_slot9_rx_n => tcds_backplane_slot9_rx_n, tcds2_backplane_slot10_tx_p => tcds_backplane_slot10_tx_p, tcds2_backplane_slot10_tx_n => tcds_backplane_slot10_tx_n, tcds2_backplane_slot10_rx_p => tcds_backplane_slot10_rx_p, tcds2_backplane_slot10_rx_n => tcds_backplane_slot10_rx_n, tcds2_backplane_slot11_tx_p => tcds_backplane_slot11_tx_p, tcds2_backplane_slot11_tx_n => tcds_backplane_slot11_tx_n, tcds2_backplane_slot11_rx_p => tcds_backplane_slot11_rx_p, tcds2_backplane_slot11_rx_n => tcds_backplane_slot11_rx_n, tcds2_backplane_slot12_tx_p => tcds_backplane_slot12_tx_p, tcds2_backplane_slot12_tx_n => tcds_backplane_slot12_tx_n, tcds2_backplane_slot12_rx_p => tcds_backplane_slot12_rx_p, tcds2_backplane_slot12_rx_n => tcds_backplane_slot12_rx_n, tcds2_backplane_slot13_tx_p => tcds_backplane_slot13_tx_p, tcds2_backplane_slot13_tx_n => tcds_backplane_slot13_tx_n, tcds2_backplane_slot13_rx_p => tcds_backplane_slot13_rx_p, tcds2_backplane_slot13_rx_n => tcds_backplane_slot13_rx_n, tcds2_backplane_slot14_tx_p => tcds_backplane_slot14_tx_p, tcds2_backplane_slot14_tx_n => tcds_backplane_slot14_tx_n, tcds2_backplane_slot14_rx_p => tcds_backplane_slot14_rx_p, tcds2_backplane_slot14_rx_n => tcds_backplane_slot14_rx_n, tcds2_daq_fpga_tx_p => tcds_daq_fpga_tx_p, tcds2_daq_fpga_tx_n => tcds_daq_fpga_tx_n, tcds2_daq_fpga_rx_p => tcds_daq_fpga_rx_p, tcds2_daq_fpga_rx_n => tcds_daq_fpga_rx_n, ------------ ttc2_frame_slot2 => ttc2_frame(0), ttc2_frame_slot3 => ttc2_frame(1), ttc2_frame_slot4 => ttc2_frame(2), ttc2_frame_slot5 => ttc2_frame(3), ttc2_frame_slot6 => ttc2_frame(4), ttc2_frame_slot7 => ttc2_frame(5), ttc2_frame_slot8 => ttc2_frame(6), ttc2_frame_slot9 => ttc2_frame(7), ttc2_frame_slot10 => ttc2_frame(8), ttc2_frame_slot11 => ttc2_frame(9), ttc2_frame_slot12 => ttc2_frame(10), ttc2_frame_slot13 => ttc2_frame(11), ttc2_frame_slot14 => ttc2_frame(12), ttc2_frame_daq_fpga => ttc2_frame(13), ------------ tts2_frame_slot2 => tts2_frame(0), tts2_frame_slot3 => tts2_frame(1), tts2_frame_slot4 => tts2_frame(2), tts2_frame_slot5 => tts2_frame(3), tts2_frame_slot6 => tts2_frame(4), tts2_frame_slot7 => tts2_frame(5), tts2_frame_slot8 => tts2_frame(6), tts2_frame_slot9 => tts2_frame(7), tts2_frame_slot10 => tts2_frame(8), tts2_frame_slot11 => tts2_frame(9), tts2_frame_slot12 => tts2_frame(10), tts2_frame_slot13 => tts2_frame(11), tts2_frame_slot14 => tts2_frame(12), tts2_frame_daq_fpga => tts2_frame(13) ); end rtl; --======================================================================