--====================================================================== -- TCDS2 captain. --====================================================================== library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; use work.ipbus.all; use work.ipbus_reg_types.all; use work.dth_tcds_infra_status.all; use work.ipbus_decode_dth_tcds_user_main.all; --================================================== entity dth_tcds_user_main is port ( clk_ipb : in std_logic; rst_ipb : in std_logic; ipb_in : in ipb_wbus; ipb_out : out ipb_rbus; clk_aux : in std_logic; rst_aux : in std_logic; nuke : in std_logic; soft_rst : in std_logic; -- Status summary from the board infrastructure. infra_status : in dth_tcds_infra_status; -- General purpose clocks from IC51. clk_gp_100mhz_p : in std_logic; clk_gp_100mhz_n : in std_logic; clk_gp_125mhz_p : in std_logic; clk_gp_125mhz_n : in std_logic; clk_gp_156_25mhz_p : in std_logic; clk_gp_156_25mhz_n : in std_logic; -- GTH reference clocks. mgt_refclk_gth_mgt226_rc0_p : in std_logic; mgt_refclk_gth_mgt226_rc0_n : in std_logic; mgt_refclk_gth_mgt227_rc0_p : in std_logic; mgt_refclk_gth_mgt227_rc0_n : in std_logic; mgt_refclk_gth_mgt231_rc0_p : in std_logic; mgt_refclk_gth_mgt231_rc0_n : in std_logic; mgt_refclk_gth_mgt232_rc0_p : in std_logic; mgt_refclk_gth_mgt232_rc0_n : in std_logic; mgt_refclk_gth_mgt233_rc0_p : in std_logic; mgt_refclk_gth_mgt233_rc0_n : in std_logic; mgt_refclk_gth_mgt234_rc0_p : in std_logic; mgt_refclk_gth_mgt234_rc0_n : in std_logic; -- GTY reference clocks. mgt_refclk_gty_mgt127_rc0_p : in std_logic; mgt_refclk_gty_mgt127_rc0_n : in std_logic; mgt_refclk_gty_mgt128_rc0_p : in std_logic; mgt_refclk_gty_mgt128_rc0_n : in std_logic; mgt_refclk_gty_mgt130_rc0_p : in std_logic; mgt_refclk_gty_mgt130_rc0_n : in std_logic; mgt_refclk_gty_mgt132_rc0_p : in std_logic; mgt_refclk_gty_mgt132_rc0_n : in std_logic; mgt_refclk_gty_mgt132_rc1_p : in std_logic; mgt_refclk_gty_mgt132_rc1_n : in std_logic; mgt_refclk_gty_mgt133_rc0_p : in std_logic; mgt_refclk_gty_mgt133_rc0_n : in std_logic; mgt_refclk_gty_mgt134_rc0_p : in std_logic; mgt_refclk_gty_mgt134_rc0_n : in std_logic; -- Clock selection lines. -- - The select line of IC84, switching between the GTH and GTY -- recovered MGT clocks. sel_recclk_out : out std_logic; -- Status/diagnostic LEDs. user_leds : out std_logic_vector(7 downto 0); -- Front-panel TCDS SFPs. tcds_frontpanel_a_tx_p : out std_logic; tcds_frontpanel_a_tx_n : out std_logic; tcds_frontpanel_a_rx_p : in std_logic; tcds_frontpanel_a_rx_n : in std_logic; -- tcds_frontpanel_b_tx_p : out std_logic; tcds_frontpanel_b_tx_n : out std_logic; tcds_frontpanel_b_rx_p : in std_logic; tcds_frontpanel_b_rx_n : in std_logic; -- Backplane TCDS signals. -- NOTE: Slot 1 (i.e., index 0) is the first hub slot, in which the DTH sits. tcds_backplane_slot2_tx_p : out std_logic; tcds_backplane_slot2_tx_n : out std_logic; tcds_backplane_slot2_rx_p : in std_logic; tcds_backplane_slot2_rx_n : in std_logic; -- tcds_backplane_slot3_tx_p : out std_logic; tcds_backplane_slot3_tx_n : out std_logic; tcds_backplane_slot3_rx_p : in std_logic; tcds_backplane_slot3_rx_n : in std_logic; -- tcds_backplane_slot4_tx_p : out std_logic; tcds_backplane_slot4_tx_n : out std_logic; tcds_backplane_slot4_rx_p : in std_logic; tcds_backplane_slot4_rx_n : in std_logic; -- tcds_backplane_slot5_tx_p : out std_logic; tcds_backplane_slot5_tx_n : out std_logic; tcds_backplane_slot5_rx_p : in std_logic; tcds_backplane_slot5_rx_n : in std_logic; -- tcds_backplane_slot6_tx_p : out std_logic; tcds_backplane_slot6_tx_n : out std_logic; tcds_backplane_slot6_rx_p : in std_logic; tcds_backplane_slot6_rx_n : in std_logic; -- tcds_backplane_slot7_tx_p : out std_logic; tcds_backplane_slot7_tx_n : out std_logic; tcds_backplane_slot7_rx_p : in std_logic; tcds_backplane_slot7_rx_n : in std_logic; -- tcds_backplane_slot8_tx_p : out std_logic; tcds_backplane_slot8_tx_n : out std_logic; tcds_backplane_slot8_rx_p : in std_logic; tcds_backplane_slot8_rx_n : in std_logic; -- tcds_backplane_slot9_tx_p : out std_logic; tcds_backplane_slot9_tx_n : out std_logic; tcds_backplane_slot9_rx_p : in std_logic; tcds_backplane_slot9_rx_n : in std_logic; -- tcds_backplane_slot10_tx_p : out std_logic; tcds_backplane_slot10_tx_n : out std_logic; tcds_backplane_slot10_rx_p : in std_logic; tcds_backplane_slot10_rx_n : in std_logic; -- tcds_backplane_slot11_tx_p : out std_logic; tcds_backplane_slot11_tx_n : out std_logic; tcds_backplane_slot11_rx_p : in std_logic; tcds_backplane_slot11_rx_n : in std_logic; -- tcds_backplane_slot12_tx_p : out std_logic; tcds_backplane_slot12_tx_n : out std_logic; tcds_backplane_slot12_rx_p : in std_logic; tcds_backplane_slot12_rx_n : in std_logic; -- tcds_backplane_slot13_tx_p : out std_logic; tcds_backplane_slot13_tx_n : out std_logic; tcds_backplane_slot13_rx_p : in std_logic; tcds_backplane_slot13_rx_n : in std_logic; -- tcds_backplane_slot14_tx_p : out std_logic; tcds_backplane_slot14_tx_n : out std_logic; tcds_backplane_slot14_rx_p : in std_logic; tcds_backplane_slot14_rx_n : in std_logic ); end dth_tcds_user_main; --================================================== architecture rtl of dth_tcds_user_main is -- IPBus read/write buses. signal ipbw : ipb_wbus_array(N_SLAVES - 1 downto 0); signal ipbr : ipb_rbus_array(N_SLAVES - 1 downto 0); -- Clock signals. signal clk_gp_100mhz : std_logic; signal mgt233_refclk0 : std_logic; signal mgt234_refclk0 : std_logic; -- TCDS frontpanel signals. signal tcds_frontpanel_gth_tx_p : std_logic_vector(3 downto 0); signal tcds_frontpanel_gth_tx_n : std_logic_vector(3 downto 0); signal tcds_frontpanel_gth_rx_p : std_logic_vector(3 downto 0); signal tcds_frontpanel_gth_rx_n : std_logic_vector(3 downto 0); -- TCDS frontpanel MGT reference clocks. signal tcds_frontpanel_gth_refclk0 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_refclk1 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_northrefclk0 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_northrefclk1 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_southrefclk0 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_southrefclk1 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_refclk00 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_refclk10 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_refclk01 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_refclk11 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_northrefclk00 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_northrefclk10 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_northrefclk01 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_northrefclk11 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_southrefclk00 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_southrefclk10 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_southrefclk01 : std_logic_vector(0 downto 0); signal tcds_frontpanel_gth_southrefclk11 : std_logic_vector(0 downto 0); begin ------------------------------------------ -- IPBus address decoder. ------------------------------------------ fabric : entity work.ipbus_fabric_sel generic map ( NSLV => N_SLAVES, SEL_WIDTH => IPBUS_SEL_WIDTH ) port map ( ipb_in => ipb_in, ipb_out => ipb_out, sel => ipbus_sel_dth_tcds_user_main(ipb_in.ipb_addr), ipb_to_slaves => ipbw, ipb_from_slaves => ipbr ); ------------------------------------------ -- Input buffers for general purpose clocks. ------------------------------------------ ibufds_100mhz : IBUFDS port map ( i => clk_gp_100mhz_p, ib => clk_gp_100mhz_n, o => clk_gp_100mhz ); ------------------------------------------ -- Input buffers for MGT reference clocks. ------------------------------------------ ibufds_mgt233_refclk0 : IBUFDS_GTE4 port map ( i => mgt_refclk_gth_mgt233_rc0_p, ib => mgt_refclk_gth_mgt233_rc0_n, o => mgt233_refclk0, ceb => '0' ); ibufds_mgt234_refclk0 : IBUFDS_GTE4 port map ( i => mgt_refclk_gth_mgt234_rc0_p, ib => mgt_refclk_gth_mgt234_rc0_n, o => mgt234_refclk0, ceb => '0' ); ------------------------------------------ -- Front-panel diagnostic leds. ------------------------------------------ leds : entity work.dth_tcds_user_leds port map ( user_led_top_left => infra_status.pcie_link_locked_and_up, user_led_top_right_of_left => infra_status.pcie_link_activity, user_led_top_left_of_right => '0', user_led_top_right => '0', user_led_bottom_left => '0', user_led_bottom_right_of_left => '0', user_led_bottom_left_of_right => '0', user_led_bottom_right => '0', user_led_connections => user_leds ); ------------------------------------------ -- IBERT on front-panel TCDS B (GTH) SFP. -- NOTE: For the moment this is used simply to deliver a clock to the DTH -- under development. ------------------------------------------ ibert_tcds_frontpanel_gth : entity work.ibert_tcds_frontpanel_gth_10g port map ( txp_o => tcds_frontpanel_gth_tx_p, txn_o => tcds_frontpanel_gth_tx_n, rxn_i => tcds_frontpanel_gth_rx_p, rxp_i => tcds_frontpanel_gth_rx_n, gtrefclk0_i => tcds_frontpanel_gth_refclk0, gtrefclk1_i => tcds_frontpanel_gth_refclk1, gtnorthrefclk0_i => tcds_frontpanel_gth_northrefclk0, gtnorthrefclk1_i => tcds_frontpanel_gth_northrefclk1, gtsouthrefclk0_i => tcds_frontpanel_gth_southrefclk0, gtsouthrefclk1_i => tcds_frontpanel_gth_southrefclk1, gtrefclk00_i => tcds_frontpanel_gth_refclk00, gtrefclk10_i => tcds_frontpanel_gth_refclk10, gtrefclk01_i => tcds_frontpanel_gth_refclk01, gtrefclk11_i => tcds_frontpanel_gth_refclk11, gtnorthrefclk00_i => tcds_frontpanel_gth_northrefclk00, gtnorthrefclk10_i => tcds_frontpanel_gth_northrefclk10, gtnorthrefclk01_i => tcds_frontpanel_gth_northrefclk01, gtnorthrefclk11_i => tcds_frontpanel_gth_northrefclk11, gtsouthrefclk00_i => tcds_frontpanel_gth_southrefclk00, gtsouthrefclk10_i => tcds_frontpanel_gth_southrefclk10, gtsouthrefclk01_i => tcds_frontpanel_gth_southrefclk01, gtsouthrefclk11_i => tcds_frontpanel_gth_southrefclk11, rxoutclk_o => open, clk => clk_gp_100mhz ); -- MGT234-0, not connected. -- <= tcds_frontpanel_gth_tx_p(0); -- <= tcds_frontpanel_gth_tx_n(0) <= '0'; tcds_frontpanel_gth_rx_p(0) <= '0'; tcds_frontpanel_gth_rx_n(0) <= '0'; -- MGT234-1, frontpanel TCDS B. tcds_frontpanel_b_tx_p <= tcds_frontpanel_gth_tx_p(1); tcds_frontpanel_b_tx_n <= tcds_frontpanel_gth_tx_n(1); tcds_frontpanel_gth_rx_p(1) <= tcds_frontpanel_b_rx_p; tcds_frontpanel_gth_rx_n(1) <= tcds_frontpanel_b_rx_n; -- MGT234-2, not connected. -- <= tcds_frontpanel_gth_tx_p(2); -- <= tcds_frontpanel_gth_tx_n(2); tcds_frontpanel_gth_rx_p(2) <= '0'; tcds_frontpanel_gth_rx_n(2) <= '0'; -- MGT234-3, frontpanel slot 5. -- <= tcds_frontpanel_gth_tx_p(3); -- <= tcds_frontpanel_gth_tx_n(3); tcds_frontpanel_gth_rx_p(3) <= '0'; tcds_frontpanel_gth_rx_n(3) <= '0'; -- MGT234, using MGT234-refclk0. tcds_frontpanel_gth_refclk0(0) <= mgt234_refclk0; tcds_frontpanel_gth_refclk1(0) <= '0'; tcds_frontpanel_gth_northrefclk0(0) <= '0'; tcds_frontpanel_gth_northrefclk1(0) <= '0'; tcds_frontpanel_gth_southrefclk0(0) <= '0'; tcds_frontpanel_gth_southrefclk1(0) <= '0'; tcds_frontpanel_gth_refclk00(0) <= mgt234_refclk0; tcds_frontpanel_gth_refclk10(0) <= '0'; tcds_frontpanel_gth_refclk01(0) <= '0'; tcds_frontpanel_gth_refclk11(0) <= '0'; tcds_frontpanel_gth_northrefclk00(0) <= '0'; tcds_frontpanel_gth_northrefclk10(0) <= '0'; tcds_frontpanel_gth_northrefclk01(0) <= '0'; tcds_frontpanel_gth_northrefclk11(0) <= '0'; tcds_frontpanel_gth_southrefclk00(0) <= '0'; tcds_frontpanel_gth_southrefclk10(0) <= '0'; tcds_frontpanel_gth_southrefclk01(0) <= '0'; tcds_frontpanel_gth_southrefclk11(0) <= '0'; ------------------------------------------ -- Loopback on the backplane TCDS signal. (Node functionality.) ------------------------------------------ loopback_tcds2_backplane_node : entity work.loopback_tcds_backplane_node_slot port map ( clk_ipb => clk_ipb, rst_ipb => rst_ipb, ipb_in => ipbw(N_SLV_LOOPBACK_TCDS_BACKPLANE_NODE_SLOT), ipb_out => ipbr(N_SLV_LOOPBACK_TCDS_BACKPLANE_NODE_SLOT), clk_gp_100mhz => clk_gp_100mhz, mgt233_refclk0_320mhz => mgt233_refclk0, tcds_backplane_slot2_tx_p => tcds_backplane_slot2_tx_p, tcds_backplane_slot2_tx_n => tcds_backplane_slot2_tx_n, tcds_backplane_slot2_rx_p => tcds_backplane_slot2_rx_p, tcds_backplane_slot2_rx_n => tcds_backplane_slot2_rx_n ); end rtl; --======================================================================