--====================================================================== -- TCDS2 backplane link. --====================================================================== library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; use work.lpgbtfpga_package.all; entity tcds2_link_backplane is port ( -- System clock. clk_sys_i : in std_logic; -- MGT reference clock. trxrefclk_i : in std_logic; -- MGT TX/RX user clocks. rxusrclk_o : out std_logic; txusrclk_o : out std_logic; -- MGT resets. reset_all_i : in std_logic; reset_tx_i : in std_logic; reset_rx_i : in std_logic; -- MGT TX/RX readiness flags. tx_ready_o : out std_logic; rx_ready_o : out std_logic; -- Serial MGT data interface. rx_p_i : in std_logic; rx_n_i : in std_logic; tx_p_o : out std_logic; tx_n_o : out std_logic; -- Parallel data in/out: 234 bits for FEC5 and 10.24 Gbps. data_i : in std_logic_vector(233 downto 0); data_valid_i : in std_logic; data_o : out std_logic_vector(233 downto 0); data_valid_o : out std_logic ); end tcds2_link_backplane; --============================================================================== -- architecture declaration --============================================================================== architecture rtl of tcds2_link_backplane is --! Attribute declaration attribute mark_debug : string; attribute keep : string; -- lpGBT-FPGA expert parameters (values extracted from example design for KCU105) constant c_multicyleDelay : integer := 3 ; constant c_clockRatio : integer := 8 ; constant c_mgtWordWidth : integer := 32; constant c_allowedFalseHeader : integer := 5 ; constant c_allowedFalseHeaderOverN : integer := 64; constant c_requiredTrueHeader : integer := 32; constant c_bitslip_mindly : integer := 2 ; constant c_bitslip_waitdly : integer := 40; -- Bitslip expert parameters for fixed latency applications - EBSM constant c_resetOnEven : integer := 0; --! Reset on even bitslip (1: Enabled/ 0: disabled) constant c_resetDuration : integer := 10; --! Reset duration (in clk_freeRunningClk_i periods) --! Signal declaration ------> global from/to User Datapath ---- tx signal not_mgt_tx_ready : std_logic ; signal tx_reset : std_logic ; -- reset tx datapath until transceiver tx is ready signal prbsgen_frame : std_logic_vector(data_o'length-1 downto 0); --! PRBS output data ---- lpGBT-FE tx signal tx_tx_strobe : std_logic ; signal tx_tx_data : std_logic_vector(229 downto 0) := (others => '0'); signal tx_tx_ec : std_logic_vector(1 downto 0) ; signal tx_tx_ic : std_logic_vector(1 downto 0) ; signal tx_tx_word : std_logic_vector(c_mgtWordWidth-1 downto 0) ; signal tx_scrambler_bypass : std_logic := '0' ; signal tx_interleaver_bypass : std_logic := '0' ; signal tx_tx_error : std_logic_vector(255 downto 0) := (others => '0'); -- signal tx_strobe_gen_cnt : std_logic_vector(2 downto 0); signal rx_strobe_gen_cnt : std_logic_vector(2 downto 0); attribute mark_debug of data_valid_i : signal is "true"; -- attribute keep of tx_strobe_gen_cnt : signal is "true"; attribute mark_debug of rx_strobe_gen_cnt : signal is "true"; attribute mark_debug of tx_reset : signal is "true"; attribute keep of tx_tx_strobe, tx_tx_data, tx_tx_ec, tx_tx_ic : signal is "true"; attribute mark_debug of tx_tx_strobe, tx_tx_data, tx_tx_ec, tx_tx_ic : signal is "true"; ---- rx signal rx_strobe : std_logic; signal not_mgt_rx_ready : std_logic ; signal rx_reset : std_logic ; signal rx_reset_n : std_logic ; ---- lpGBT-FPGA rx -- Clock and reset signal rx_uplinkClkOutEn : std_logic; --! Clock enable to be USEd in the USEr's logic signal rx_uplinkRst_n : std_logic; --! Uplink reset SIGNAL (rx ready from the transceiver) attribute keep of rx_uplinkClkOutEn : signal is "true"; attribute mark_debug of rx_reset, rx_reset_n, rx_strobe, rx_uplinkClkOutEn : signal is "true"; -- Input signal rx_mgt_word : std_logic_vector((c_mgtWordWidth-1) downto 0); --! Input frame coming from the MGT -- Data signal rx_USErData : std_logic_vector(229 downto 0); --! User output (decoded data). The payload size varies depENDing on the --! datarate/FEC configuration: --! * *FEC5 / 5.12 Gbps*: 112bit --! * *FEC12 / 5.12 Gbps*: 98bit --! * *FEC5 / 10.24 Gbps*: 230bit --! * *FEC12 / 10.24 Gbps*: 202bit signal rx_EcData : std_logic_vector(1 downto 0); --! EC field value received from the LpGBT signal rx_IcData : std_logic_vector(1 downto 0); --! IC field value received from the LpGBT attribute keep of rx_USErData, rx_EcData, rx_IcData : signal is "true"; attribute mark_debug of rx_USErData, rx_EcData, rx_IcData : signal is "true"; -- Control signal rx_bypassInterleaver : std_logic := '0'; --! Bypass uplink interleaver (test purpose only) signal rx_bypassFECEncoder : std_logic := '0'; --! Bypass uplink FEC (test purpose only) signal rx_bypassScrambler : std_logic := '0'; --! Bypass uplink scrambler (test purpose only) -- Transceiver control signal rx_mgt_bitslipCtrl : std_logic; --! Control the Bitslib/rxSlide PORT of the Mgt -- Status signal rx_dataCorrected : std_logic_vector(229 downto 0); --! Flag allowing to know which bit(s) were toggled by the FEC signal rx_IcCorrected : std_logic_vector(1 downto 0); --! Flag allowing to know which bit(s) of the IC field were toggled by the FEC signal rx_EcCorrected : std_logic_vector(1 downto 0); --! Flag allowing to know which bit(s) of the EC field were toggled by the FEC signal rx_rdy : std_logic; --! Ready SIGNAL from the uplink decoder attribute keep of rx_dataCorrected, rx_IcCorrected, rx_EcCorrected, rx_rdy: signal is "true"; attribute mark_debug of rx_dataCorrected, rx_IcCorrected, rx_EcCorrected, rx_rdy: signal is "true"; ------> global from/to FPGA Transceiver and auxiliary blocks -- User clocks signal mgt_txusrclk : std_logic; signal mgt_rxusrclk : std_logic; ---- Reset and Status -- Resets signal mgt_reset_all : std_logic; signal mgt_reset_tx_pll_and_datapath : std_logic; signal mgt_reset_tx_datapath : std_logic; signal mgt_reset_rx_pll_and_datapath : std_logic; -- mgt_reset_user_rx_pll_and_datapath signal mgt_reset_user_rx_pll_and_datapath : std_logic; signal mgt_reset_rx_datapath : std_logic; attribute keep of mgt_reset_all, mgt_reset_tx_pll_and_datapath, mgt_reset_tx_datapath, mgt_reset_user_rx_pll_and_datapath, mgt_reset_rx_datapath : signal is "true"; -- Status signal mgt_txpll_lock : std_logic; signal mgt_rxpll_lock : std_logic; signal mgt_buffbypass_rx_done : std_logic; signal mgt_buffbypass_rx_error : std_logic; signal mgt_reset_rx_cdr_stable : std_logic; signal mgt_reset_tx_done : std_logic; signal mgt_reset_rx_done : std_logic; signal mgt_rxpmaresetdone : std_logic; signal mgt_txpmaresetdone : std_logic; signal mgt_tx_ready : std_logic; signal mgt_rx_ready : std_logic; attribute keep of mgt_txpll_lock, mgt_rxpll_lock, mgt_buffbypass_rx_done, mgt_buffbypass_rx_error, mgt_reset_rx_cdr_stable, mgt_reset_tx_done, mgt_reset_rx_done, mgt_rxpmaresetdone, mgt_txpmaresetdone, mgt_tx_ready, mgt_rx_ready : signal is "true"; ---- Low-level control/debug -- Polarity control signal mgt_txpolarity : std_logic; signal mgt_rxpolarity : std_logic; attribute keep of mgt_txpolarity, mgt_rxpolarity : signal is "true"; signal mgt_rxeq_rxlpmen,mgt_rxeq_dfelpmreset : std_logic; -- Loopback features signal mgt_loopback : std_logic_vector(2 downto 0); -- 000 = Normal operation -- 001 = Near-End PCS Loopback -- 010 = Near-End PMA Loopback -- 100 = Far-End PMA Loopback -- 110 = Far-End PCS Loopback -- others = Reserved attribute keep of mgt_loopback : signal is "true"; -- Built-in PRBS testing structures signal mgt_txprbsforceerr : std_logic; signal mgt_txprbssel : std_logic_vector(3 downto 0); -- 0000 = Normal operation -- 0001 = PRBS-7 -- 0010 = PRBS-9 -- 0011 = PRBS-15 -- 0100 = PRBS-23 -- 0101 = PRBS-31 -- 1001 = Square wave with 2 UI (alternating 0s/1s) -- 1010 = Square wave with 32 UI -- others = Reserved signal mgt_rxprbscntreset : std_logic; signal mgt_rxprbssel : std_logic_vector(3 downto 0); -- Same convention as mgt_txprbssel signal mgt_rxprbserr : std_logic; signal mgt_rxprbslocked : std_logic; attribute keep of mgt_txprbsforceerr, mgt_txprbssel, mgt_rxprbscntreset, mgt_rxprbssel, mgt_rxprbserr, mgt_rxprbslocked : signal is "true"; -- Dynamic reconfiguration port signal mgt_drpwe : std_logic; signal mgt_drpen : std_logic; signal mgt_drpaddr : std_logic_vector(9 downto 0); signal mgt_drpdi : std_logic_vector(15 downto 0); signal mgt_drprdy_latched : std_logic; signal mgt_drpdo : std_logic_vector(15 downto 0); attribute keep of mgt_drpwe, mgt_drpen, mgt_drpaddr, mgt_drpdi, mgt_drprdy_latched, mgt_drpdo : signal is "true"; ---- HPTD IP - tx Phase Aligner -- Configuration signal mgt_hptd_tx_fifo_fill_pd_max : std_logic_vector(31 downto 0); signal mgt_hptd_tx_pi_phase_calib : std_logic_vector(6 downto 0); signal mgt_hptd_tx_ui_align_calib : std_logic; attribute keep of mgt_hptd_tx_fifo_fill_pd_max, mgt_hptd_tx_pi_phase_calib, mgt_hptd_tx_ui_align_calib : signal is "true"; -- tx PI phase value signal mgt_hptd_tx_pi_phase : std_logic_vector(6 downto 0); attribute keep of mgt_hptd_tx_pi_phase : signal is "true"; -- tx fifo fill level phase detector signal mgt_hptd_tx_fifo_fill_pd : std_logic_vector(31 downto 0); attribute keep of mgt_hptd_tx_fifo_fill_pd : signal is "true"; -- Fine Phase Shift Interface (only valid once transceiver is ready tx_ready_o=1) signal mgt_hptd_ps_strobe : std_logic; signal mgt_hptd_ps_inc_ndec : std_logic; signal mgt_hptd_ps_phase_step : std_logic_vector(3 downto 0); signal mgt_hptd_ps_done_latched : std_logic; signal user_hptd_ps_strobe : std_logic; signal user_hptd_ps_inc_ndec : std_logic; signal user_hptd_ps_phase_step : std_logic_vector(3 downto 0); signal user_hptd_ps_done_latched : std_logic; attribute keep of user_hptd_ps_strobe, user_hptd_ps_inc_ndec, user_hptd_ps_phase_step, user_hptd_ps_done_latched : signal is "true"; ---- rx Equalizer signal mgt_rxeq_rxlpmgcovrden : std_logic; signal mgt_rxeq_rxlpmhfovrden : std_logic; signal mgt_rxeq_rxlpmlfklovrden : std_logic; signal mgt_rxeq_rxlpmosovrden : std_logic; signal mgt_rxeq_dmonitor : std_logic_vector (15 downto 0); attribute keep of mgt_rxeq_rxlpmgcovrden, mgt_rxeq_rxlpmhfovrden, mgt_rxeq_rxlpmlfklovrden, mgt_rxeq_rxlpmosovrden, mgt_rxeq_dmonitor : signal is "true"; ---- MGT <-> Infrastructure signals signal gtwiz_userclk_tx_active_in : std_logic_vector(0 downto 0); signal gtwiz_userclk_rx_active_in : std_logic_vector(0 downto 0); signal gtwiz_buffbypass_rx_reset_in : std_logic_vector(0 downto 0); signal gtwiz_buffbypass_rx_start_user_in : std_logic_vector(0 downto 0); signal gtwiz_buffbypass_rx_done_out : std_logic_vector(0 downto 0); signal gtwiz_buffbypass_rx_error_out : std_logic_vector(0 downto 0); signal gtwiz_reset_all_in : std_logic_vector(0 downto 0); signal gtwiz_reset_tx_pll_and_datapath_in : std_logic_vector(0 downto 0); signal gtwiz_reset_tx_datapath_in : std_logic_vector(0 downto 0); signal gtwiz_reset_rx_pll_and_datapath_in : std_logic_vector(0 downto 0); signal gtwiz_reset_rx_datapath_in : std_logic_vector(0 downto 0); signal gtwiz_reset_rx_cdr_stable_out : std_logic_vector(0 downto 0); signal gtwiz_reset_tx_done_out : std_logic_vector(0 downto 0); signal gtwiz_reset_rx_done_out : std_logic_vector(0 downto 0); signal qpll0lock_out : std_logic_vector(0 downto 0); signal dmonitorclk_in : std_logic_vector(0 downto 0); signal drpaddr_in : std_logic_vector(9 downto 0); signal drpclk_in : std_logic_vector(0 downto 0); signal drpdi_in : std_logic_vector(15 downto 0); signal drpen_in : std_logic_vector(0 downto 0); signal drpwe_in : std_logic_vector(0 downto 0); signal rxpolarity_in : std_logic_vector(0 downto 0); signal rxprbscntreset_in : std_logic_vector(0 downto 0); signal rxprbssel_in : std_logic_vector(3 downto 0); signal txpippmen_in : std_logic_vector(0 downto 0); signal txpippmovrden_in : std_logic_vector(0 downto 0); signal txpippmpd_in : std_logic_vector(0 downto 0); signal txpippmsel_in : std_logic_vector(0 downto 0); signal txpippmstepsize_in : std_logic_vector(4 downto 0); signal txpolarity_in : std_logic_vector(0 downto 0); signal txprbsforceerr_in : std_logic_vector(0 downto 0); signal txprbssel_in : std_logic_vector(3 downto 0); signal dmonitorout_out : std_logic_vector(15 downto 0); signal drpdo_out : std_logic_vector(15 downto 0); signal drprdy_out : std_logic_vector(0 downto 0); signal rxoutclk_out : std_logic_vector(0 downto 0); signal rxpmaresetdone_out : std_logic_vector(0 downto 0); signal rxprbserr_out : std_logic_vector(0 downto 0); signal rxprbslocked_out : std_logic_vector(0 downto 0); signal txbufstatus_out : std_logic_vector(1 downto 0); signal txoutclk_out : std_logic_vector(0 downto 0); signal txpmaresetdone_out : std_logic_vector(0 downto 0); signal aux_gtwiz_reset_rx_done : std_logic_vector(0 downto 0); ------> Sync. from/to control interface signal rx_frame_locked_sync : std_logic; --! Ready SIGNAL from the uplink decoder sync. to clk_sys_i ------> TCLink Control/stat -------------------- ---- clocking signal clk_offset : std_logic; --! Clock offset for TCLink heterodyne phase measurement signal clk_offset_locked_async : std_logic; --! Clock offset is locked signal clk_offset_locked : std_logic; --! Clock offset is locked attribute keep of clk_offset_locked : signal is "true"; ---- configuration ---- CONTROL -- Loop controller signal tclink_close_loop : std_logic; --! Loop is closed signal tclink_offset_error : std_logic_vector(47 downto 0); --! Error offset --! This is a fractional signed number attribute keep of tclink_close_loop, tclink_offset_error : signal is "true"; ---- PSEUDO-STATIC signal tclink_metastability_deglitch : std_logic_vector(15 downto 0); --! Metastability deglitch threshold signal tclink_phase_detector_navg : std_logic_vector(11 downto 0); --! Averaging for phase detector signal tclink_modulo_carrier_period : std_logic_vector(47 downto 0); --! Modulo of carrier period in DDMTD UNITS (unit is index 10) attribute keep of tclink_metastability_deglitch, tclink_phase_detector_navg, tclink_modulo_carrier_period : signal is "true"; signal tclink_master_rx_ui_period : std_logic_vector(47 downto 0); attribute keep of tclink_master_rx_ui_period : signal is "true"; signal tclink_master_rx_slide_mode: std_logic; -- Loop controller signal tclink_Aie : std_logic_vector(3 downto 0); --! Integral coefficient signal tclink_Aie_enable : std_logic; --! Enables usage of integral coefficient signal tclink_Ape : std_logic_vector(3 downto 0); --! Proportional coefficient attribute keep of tclink_Aie, tclink_Aie_enable, tclink_Ape : signal is "true"; -- Sigma-delta signal tclink_sigma_delta_clk_div : std_logic_vector(15 downto 0); --! Sigma-delta clock divider modulo (unsigned) attribute keep of tclink_sigma_delta_clk_div : signal is "true"; -- Mirror compensation signal tclink_enable_mirror : std_logic; --! Enable mirror compensation scheme (a part of phase variation is compensated using this scheme, otherwise a full compensation is performed) signal tclink_Adco : std_logic_vector(47 downto 0); --! DCO coefficient for mirror compensation attribute keep of tclink_enable_mirror, tclink_Adco : signal is "true"; ---- STATUS signal tclink_phase_detector : std_logic_vector(31 downto 0); --! Phase-detector output, unit is bit 0 signal tclink_error_controller: std_logic_vector(47 downto 0); --! Error output from error processing block (should be between -1*modulo_carrier_period_i/2 and +1*modulo_carrier_period_i/2) signal tclink_phase_acc : std_logic_vector(15 downto 0); --! phase accumulated output (integrated output) --! This is an integer signed number, the LSB is the bit signal tclink_operation_error : std_logic; --! error output indicating that a clk_en_i pulse has arrived before the done_i signal arrived from the previous strobe_o request attribute keep of tclink_phase_detector, tclink_error_controller, tclink_phase_acc, tclink_operation_error : signal is "true"; ---- DCO signal tclink_hptd_ps_strobe : std_logic; signal tclink_hptd_ps_inc_ndec : std_logic; signal tclink_hptd_ps_phase_step : std_logic; signal tclink_hptd_ps_done_latched : std_logic; ---- TESTER TCLink signal tclink_debug_tester_enable_stimulis : std_logic; --! enable stimulis for TCLink signal tclink_debug_tester_fcw : std_logic_vector(9 downto 0); --! frequency control word for NCO (unsigned) signal tclink_debug_tester_nco_scale : std_logic_vector(4 downto 0); --! scale NCO output signal tclink_debug_tester_enable_stock_out : std_logic; --! enable output data stock signal tclink_debug_tester_addr_read : std_logic_vector(9 downto 0); --! read address for reading stocked TCLink phase accumulated results signal tclink_debug_tester_data_read : std_logic_vector(15 downto 0); --! data of stocked TCLink phase accumulated results attribute keep of tclink_debug_tester_enable_stimulis, tclink_debug_tester_fcw, tclink_debug_tester_nco_scale, tclink_debug_tester_enable_stock_out, tclink_debug_tester_addr_read, tclink_debug_tester_data_read : signal is "true"; --! Component declaration ---------------------------------- User datapath ---------------------------------- component lpgbt_fe_tx is generic( g_MGT_WORD_WIDTH : integer := 32; -- Word width of MGT g_DATA_RATE : integer := 2; -- 2=10G , 1=5G g_FEC : integer := 1 -- 1=FEC5, 2=FEC12 ); -- all ports are synchronous to mgt_clock_i port ( -- Clock / reset reset_i : in std_logic ; --! active high sync input mgt_clock_i : in std_logic ; --! mgt clock (320MHz) -- User data --! ___ 1-high / 7-low ___ tx_strobe_i : in std_logic ; --! ___/ \_____________________/ \_______________ tx_data_i : in std_logic_vector(229 downto 0) ; --! User frame input X FRAME0 X FRAME1 --! datarate/FEC configuration: --! FEC5 / 5.12 Gbps => 112bit --! FEC12 / 5.12 Gbps => 98bit --! FEC5 / 10.24 Gbps => 230bit --! FEC12 / 10.24 Gbps => 202bit tx_ec_i : in std_logic_vector(1 downto 0) ; tx_ic_i : in std_logic_vector(1 downto 0) ; -- MGT tx_word_o : out std_logic_vector(g_MGT_WORD_WIDTH-1 downto 0) ; -- Debugging scrambler_bypass_i : in std_logic; --! scrambler bypass interleaver_bypass_i : in std_logic; --! interleaver bypass tx_error_i : in std_logic_vector(255 downto 0) --! Debug error injection port ); end component lpgbt_fe_tx; component lpgbtfpga_uplink_fixed IS GENERIC( -- General configuration DATARATE : integer RANGE 0 to 2; --! Datarate selection can be: DATARATE_10G24 or DATARATE_5G12 FEC : integer RANGE 0 to 2; --! FEC selection can be: FEC5 or FEC12 -- Expert parameters c_multicyleDelay : integer RANGE 0 to 7 := 3; --! Multicycle delay: USEd to relax the timing constraints c_clockRatio : integer; --! Clock ratio is mgt_USErclk / 40 (shall be an integer) c_mgtWordWidth : integer; --! Bus size of the input word c_allowedFalseHeader : integer; --! Number of false header allowed to avoid unlock on frame error c_allowedFalseHeaderOverN : integer; --! Number of header checked to know wether the lock is lost or not c_requiredTrueHeader : integer; --! Number of true header required to go in locked state c_bitslip_mindly : integer := 1; --! Number of clock cycle required WHEN asserting the bitslip SIGNAL c_bitslip_waitdly : integer := 40; --! Number of clock cycle required before being back in a stable state -- Bitslip expert parameters for fixed latency applications - EBSM c_resetOnEven : integer := 0; --! Reset on even bitslip (1: Enabled/ 0: disabled) c_resetDuration : integer := 10 --! Reset duration (in clk_freeRunningClk_i periods) ); PORT ( -- Clock and reset clk_freeRunningClk_i : in std_logic; uplinkClk_i : in std_logic; --! Input clock (rx USEr clock from transceiver) uplinkClkOutEn_o : out std_logic; --! Clock enable to be USEd in the USEr's logic uplinkRst_n_i : in std_logic; --! Uplink reset SIGNAL (rx ready from the transceiver) -- Input mgt_word_o : in std_logic_vector((c_mgtWordWidth-1) downto 0); --! Input frame coming from the MGT -- Data USErData_o : out std_logic_vector(229 downto 0); --! User output (decoded data). The payload size varies depENDing on the --! datarate/FEC configuration: --! * *FEC5 / 5.12 Gbps*: 112bit --! * *FEC12 / 5.12 Gbps*: 98bit --! * *FEC5 / 10.24 Gbps*: 230bit --! * *FEC12 / 10.24 Gbps*: 202bit EcData_o : out std_logic_vector(1 downto 0); --! EC field value received from the LpGBT IcData_o : out std_logic_vector(1 downto 0); --! IC field value received from the LpGBT -- Control bypassInterleaver_i : in std_logic; --! Bypass uplink interleaver (test purpose only) bypassFECEncoder_i : in std_logic; --! Bypass uplink FEC (test purpose only) bypassScrambler_i : in std_logic; --! Bypass uplink scrambler (test purpose only) -- Transceiver control mgt_bitslipCtrl_o : out std_logic; --! Control the Bitslib/rxSlide PORT of the Mgt -- Fixed-latency applications rst_mgtctrler_i : in std_logic; --! Rst the "reset on even" controller rst_rstoneven_o : out std_logic; --! Output reset asserted -- Status dataCorrected_o : out std_logic_vector(229 downto 0); --! Flag allowing to know which bit(s) were toggled by the FEC IcCorrected_o : out std_logic_vector(1 downto 0); --! Flag allowing to know which bit(s) of the IC field were toggled by the FEC EcCorrected_o : out std_logic_vector(1 downto 0); --! Flag allowing to know which bit(s) of the EC field were toggled by the FEC rdy_o : out std_logic --! Ready SIGNAL from the uplink decoder ); END component lpgbtfpga_uplink_fixed; -------------------------------- FPGA Transceiver -------------------------------- component gth_master_timing port ( gtwiz_userclk_tx_active_in : in std_logic_vector(0 downto 0); gtwiz_userclk_rx_active_in : in std_logic_vector(0 downto 0); gtwiz_buffbypass_rx_reset_in : in std_logic_vector(0 downto 0); gtwiz_buffbypass_rx_start_user_in : in std_logic_vector(0 downto 0); gtwiz_buffbypass_rx_done_out : out std_logic_vector(0 downto 0); gtwiz_buffbypass_rx_error_out : out std_logic_vector(0 downto 0); gtwiz_reset_clk_freerun_in : in std_logic_vector(0 downto 0); gtwiz_reset_all_in : in std_logic_vector(0 downto 0); gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector(0 downto 0); gtwiz_reset_tx_datapath_in : in std_logic_vector(0 downto 0); gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector(0 downto 0); gtwiz_reset_rx_datapath_in : in std_logic_vector(0 downto 0); gtwiz_reset_rx_cdr_stable_out : out std_logic_vector(0 downto 0); gtwiz_reset_tx_done_out : out std_logic_vector(0 downto 0); gtwiz_reset_rx_done_out : out std_logic_vector(0 downto 0); gtwiz_userdata_tx_in : in std_logic_vector(31 downto 0); gtwiz_userdata_rx_out : out std_logic_vector(31 downto 0); gtrefclk00_in : in std_logic_vector(0 downto 0); qpll0lock_out : out std_logic_vector(0 downto 0); qpll0outclk_out : out std_logic_vector(0 downto 0); qpll0outrefclk_out : out std_logic_vector(0 downto 0); dmonitorclk_in : in std_logic_vector(0 downto 0); drpaddr_in : in std_logic_vector(9 downto 0); drpclk_in : in std_logic_vector(0 downto 0); drpdi_in : in std_logic_vector(15 downto 0); drpen_in : in std_logic_vector(0 downto 0); drpwe_in : in std_logic_vector(0 downto 0); gthrxn_in : in std_logic_vector(0 downto 0); gthrxp_in : in std_logic_vector(0 downto 0); loopback_in : in std_logic_vector(2 downto 0); rxdfelpmreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); rxlpmen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); rxlpmgcovrden_in : in std_logic_vector(0 downto 0); rxlpmhfovrden_in : in std_logic_vector(0 downto 0); rxlpmlfklovrden_in : in std_logic_vector(0 downto 0); rxlpmosovrden_in : in std_logic_vector(0 downto 0); rxpolarity_in : in std_logic_vector(0 downto 0); rxprbscntreset_in : in std_logic_vector(0 downto 0); rxprbssel_in : in std_logic_vector(3 downto 0); rxslide_in : in std_logic_vector(0 downto 0); rxusrclk_in : in std_logic_vector(0 downto 0); rxusrclk2_in : in std_logic_vector(0 downto 0); txpippmen_in : in std_logic_vector(0 downto 0); txpippmovrden_in : in std_logic_vector(0 downto 0); txpippmpd_in : in std_logic_vector(0 downto 0); txpippmsel_in : in std_logic_vector(0 downto 0); txpippmstepsize_in : in std_logic_vector(4 downto 0); txpolarity_in : in std_logic_vector(0 downto 0); txprbsforceerr_in : in std_logic_vector(0 downto 0); txprbssel_in : in std_logic_vector(3 downto 0); txusrclk_in : in std_logic_vector(0 downto 0); txusrclk2_in : in std_logic_vector(0 downto 0); dmonitorout_out : out std_logic_vector(15 downto 0); drpdo_out : out std_logic_vector(15 downto 0); drprdy_out : out std_logic_vector(0 downto 0); gtpowergood_out : out std_logic_vector(0 downto 0); gthtxn_out : out std_logic_vector(0 downto 0); gthtxp_out : out std_logic_vector(0 downto 0); rxoutclk_out : out std_logic_vector(0 downto 0); rxpmaresetdone_out : out std_logic_vector(0 downto 0); rxprbserr_out : out std_logic_vector(0 downto 0); rxprbslocked_out : out std_logic_vector(0 downto 0); txbufstatus_out : out std_logic_vector(1 downto 0); txoutclk_out : out std_logic_vector(0 downto 0); txpmaresetdone_out : out std_logic_vector(0 downto 0) ); end component gth_master_timing; component mgt_fixed_phase is port ( --*************************************************************** --************************ USER PORTS *************************** --*************************************************************** ----------------------------------------------------------------- --------------------- System clock / resets --------------------- ----------------------------------------------------------------- -- System clock (must come from a free-running source) clk_sys_i : in std_logic; --! system clock input reset_i : in std_logic; --! system clock reset / sync to clk_sys_i clk_txusr_i : in std_logic; --! txusrclk from transceiver clk_rxusr_i : in std_logic; --! rxusrclk from transceiver tx_ready_o : out std_logic; --! tx is ready for data transmission (use as reset for tx logic) / sync to clk_sys_i rx_ready_o : out std_logic; --! rx is ready for data transmission (use as reset for rx logic) / sync to clk_sys_i ----------------------------------------------------------------- --------------- Low-level transceiver control/debug ------------- ----------------------------------------------------------------- -- Polarity control txpolarity_i : in std_logic; --! tx serial data polarity inversion / sync to clk_sys_i rxpolarity_i : in std_logic; --! rx serial data polarity inversion / sync to clk_sys_i -- Built-in PRBS testing structures txprbsforceerr_i : in std_logic; --! tx prbs force errors / sync to clk_sys_i txprbssel_i : in std_logic_vector(3 downto 0); --! tx built-in data generator pattern selection / sync to clk_sys_i --! 0000 = Normal operation --! 0001 = PRBS-7 --! 0010 = PRBS-9 --! 0011 = PRBS-15 --! 0100 = PRBS-23 --! 0101 = PRBS-31 --! 1001 = Square wave with 2 UI (alternating 0s/1s) --! 1010 = Square wave with 32 UI --! others = Reserved rxprbscntreset_i : in std_logic; --! rx prbs error counter reset / sync to clk_sys_i rxprbssel_i : in std_logic_vector(3 downto 0); --! rx built-in data checker pattern selection (same convention as txprbssel_i) / sync to clk_sys_i rxprbserr_o : out std_logic; --! rx built-in error detection flag / sync to clk_sys_i rxprbslocked_o : out std_logic; --! rx built-in prbs locked flag / sync to clk_sys_i ----------------------------------------------------------------- ----------------------------- DRP ------------------------------- ----------------------------------------------------------------- -- Dynamic reconfiguration port drpwe_i : in std_logic; --! DRP write enable / sync to clk_sys_i drpen_i : in std_logic; --! DRP enable (a rising edge detector is included in mgt_fixed_phase to allow slow control) / sync to clk_sys_i drpaddr_i : in std_logic_vector(9 downto 0); --! DRP address / sync to clk_sys_i drpdi_i : in std_logic_vector(15 downto 0); --! DRP Data In / sync to clk_sys_i drprdy_latched_o : out std_logic; --! DRP ready (goes to 0 when drpen_i rising edge is detected, goes to 1 when transceiver drprdy issues a pulse) / sync to clk_sys_i drpdo_o : out std_logic_vector(15 downto 0); --! DRP Data Out ----------------------------------------------------------------- ------------------- HPTD IP - tx Phase Aligner ------------------ ----------------------------------------------------------------- -- Configuration tx_fifo_fill_pd_max_i : in std_logic_vector(31 downto 0); --! Minimum 0x00400000 / sync to clk_sys_i tx_pi_phase_calib_i : in std_logic_vector(6 downto 0); --! Connect to tx_pi_phase_o value after first reset / sync to clk_sys_i tx_ui_align_calib_i : in std_logic; --! Connect to 1 to freeze tx_pi_phase after first reset / sync to clk_sys_i -- tx PI phase value tx_pi_phase_o : out std_logic_vector(6 downto 0); --! tx PI phase / sync to clk_sys_i -- tx fifo fill level phase detector tx_fifo_fill_pd_o : out std_logic_vector(31 downto 0); --! tx PD value / sync to clk_sys_i -- Fine Phase Shift Interface (only valid once transceiver is ready tx_ready_o=1) ps_strobe_i : in std_logic; --! Shall be used only once tx_ready_o='1', moves tx phase / sync to clk_sys_i ps_inc_ndec_i : in std_logic; --! Increment or decrement phase / sync to clk_sys_i ps_phase_step_i : in std_logic_vector(3 downto 0); --! Step number in tx PI units / sync to clk_sys_i ps_done_latched_o : out std_logic; --! Goes to 0 when ps_strobe_i rising edge is detected, goes to 1 when requested phase shift is performed (rising edge is detected in ps_strobe_i) / sync to clk_sys_i ----------------------------------------------------------------- --------------------- Digital Monitor --------------------------- ----------------------------------------------------------------- dmonitor_o : out std_logic_vector (15 downto 0); --! rx Digital Monitor / sync to clk_sys_i --*************************************************************** --************************* MGT PORTS *************************** --*************************************************************** -- Status mgt_reset_tx_done_i : in std_logic; --! MGT tx reset is finished / sync to clk_txusr_i mgt_reset_rx_done_i : in std_logic; --! MGT rx reset is finished / sync to clk_rxusr_i -- DRP bus / sync to clk_sys_i mgt_drpaddr_o : out std_logic_vector(9 downto 0); mgt_drpclk_o : out std_logic; mgt_drpdi_o : out std_logic_vector(15 downto 0); mgt_drpen_o : out std_logic; mgt_drpwe_o : out std_logic; mgt_drpdo_i : in std_logic_vector(15 downto 0); mgt_drprdy_i : in std_logic; -- Digital Monitor / sync to clk_sys_i mgt_dmonitorclk_o : out std_logic; mgt_dmonitorout_i : in std_logic_vector(15 downto 0); -- Polarity mgt_txpolarity_o : out std_logic; --! sync to clk_txusr_i mgt_rxpolarity_o : out std_logic; --! sync to clk_rxusr_i -- tx PRBS / sync to clk_txusr_i mgt_txprbsforceerr_o : out std_logic; mgt_txprbssel_o : out std_logic_vector(3 downto 0); -- rx PRBS / sync to clk_rxusr_i mgt_rxprbserr_i : in std_logic; mgt_rxprbslocked_i : in std_logic; mgt_rxprbscntreset_o : out std_logic; mgt_rxprbssel_o : out std_logic_vector(3 downto 0); -- tx PI + FIFO Fill level flag / sync to clk_txusr_i mgt_txbufstatus_i : in std_logic_vector(1 downto 0); mgt_txpippmen_o : out std_logic; mgt_txpippmovrden_o : out std_logic; mgt_txpippmpd_o : out std_logic; mgt_txpippmsel_o : out std_logic; mgt_txpippmstepsize_o : out std_logic_vector(4 downto 0) ); end component mgt_fixed_phase; component mgt_clock_reset is port ( --*************************************************************** --************************ USER PORTS *************************** --*************************************************************** ----------------------------------------------------------------- --------------------- System clock / resets --------------------- ----------------------------------------------------------------- -- System clock (must come from a free-running source) clk_sys_i : in std_logic; --! system clock input -- MGT reset status (sync to clk_sys_i) txpll_lock_o : out std_logic; --! MGT low-level status / sync to clk_sys_i rxpll_lock_o : out std_logic; --! MGT low-level status / sync to clk_sys_i buffbypass_rx_done_o : out std_logic; --! MGT low-level status / sync to clk_sys_i buffbypass_rx_error_o : out std_logic; --! MGT low-level status / sync to clk_sys_i reset_rx_cdr_stable_o : out std_logic; --! MGT low-level status / sync to clk_sys_i reset_tx_done_o : out std_logic; --! MGT low-level status / sync to clk_sys_i reset_rx_done_o : out std_logic; --! MGT low-level status / sync to clk_sys_i rxpmaresetdone_o : out std_logic; --! MGT low-level status / sync to clk_sys_i txpmaresetdone_o : out std_logic; --! MGT low-level status / sync to clk_sys_i --*************************************************************** --************************* MGT PORTS *************************** --*************************************************************** --! rx Buffer bypass reset mgt_gtwiz_buffbypass_rx_reset_o : out std_logic; mgt_gtwiz_buffbypass_rx_start_user_o : out std_logic; -- User clocks txusrclk_o : out std_logic; --! tx data user clock rxusrclk_o : out std_logic; --! rx data user clock --! User clock network mgt_gtwiz_userclk_tx_active_o : out std_logic; mgt_gtwiz_userclk_rx_active_o : out std_logic; mgt_txoutclk_i : in std_logic; mgt_rxoutclk_i : in std_logic; --! Reset status mgt_qpll0lock_i : in std_logic; mgt_qpll1lock_i : in std_logic; mgt_gtwiz_reset_rx_cdr_stable_i : in std_logic; mgt_gtwiz_buffbypass_rx_done_i : in std_logic; mgt_gtwiz_buffbypass_rx_error_i : in std_logic; mgt_gtwiz_reset_tx_done_i : in std_logic; mgt_gtwiz_reset_rx_done_i : in std_logic; mgt_txpmaresetdone_i : in std_logic; mgt_rxpmaresetdone_i : in std_logic ); end component mgt_clock_reset; ---------------------------------------------------------------------------------- ------------------------------------- TCLink ------------------------------------ component mmcm_tclink port ( -- Clock in ports -- Clock out ports clk_out1 : out std_logic; -- Status and control signals resetn : in std_logic; locked : out std_logic; clk_in1 : in std_logic ); end component; component tclink is generic( g_ENABLE_TESTER_IMPLEMENTATION : boolean := False; g_MASTER_RX_MGT_WORD_WIDTH : integer := 32 ); port ( ----------------------------------------------------------------- --------------------- System clock / resets --------------------- ----------------------------------------------------------------- clk_sys_i : in std_logic; --! system clock input tx_ready_i : in std_logic; --! clk_tx_i is ready (used as reset) rx_ready_i : in std_logic; --! clk_rx_i is ready and link is locked (used as reset) ----------------------------------------------------------------- ------------------------- Phase-detector ------------------------ ----------------------------------------------------------------- ---- clocks clk_tx_i : in std_logic; --! Transmitter clock clk_rx_i : in std_logic; --! Receiver clock clk_offset_i : in std_logic; --! Heterodyne conversion clock ---- configuration (PSEUDO-STATIC) metastability_deglitch_i : in std_logic_vector(15 downto 0); --! Metastability deglitch threshold phase_detector_navg_i : in std_logic_vector(11 downto 0); --! Averaging for phase detector ---- status phase_detector_o : out std_logic_vector(31 downto 0); --! Phase-detector output, unit is bit 0 ----------------------------------------------------------------- ----------------------- TCLink Controller ----------------------- ----------------------------------------------------------------- ---- error-processing configuration (Read user guide on how to deal with these signals) modulo_carrier_period_i : in std_logic_vector(47 downto 0); --! Modulo of carrier period in DDMTD UNITS (unit is index 16) offset_error_i : in std_logic_vector(47 downto 0); --! Error offset --! This is a fractional signed number --! The unit bit is the index 16 -- RX SLIDE compensation for non-fixed latency master rx -- config : pseudo_static master_rx_slide_mode_i : in std_logic; --! Slide mode / 0=PMA, 1=PCS master_rx_ui_period_i : in std_logic_vector(47 downto 0); --! UI period in DDMTD UNITS (unit is index 16) master_rx_slide_clk_i : in std_logic; --! Clock used by master rx to generate rxslide pulses master_mgt_rx_ready_i : in std_logic; --! MGT rx is ready (used as reset) master_rx_slide_i : in std_logic; --! Master rx slide error_controller_o : out std_logic_vector(47 downto 0); --! Error output from error processing block (should be between -1*modulo_carrier_period_i/2 and +1*modulo_carrier_period_i/2) --! This is a fractional signed number --! The unit bit is the index 16 ---- Controller dynamics (Read user guide on how to deal with this signal) close_loop_i : in std_logic; --! Loop is closed -- Loop controller (PSEUDO-STATIC) Aie_i : in std_logic_vector(3 downto 0); --! Integral coefficient Aie_enable_i : in std_logic; --! Enables usage of integral coefficient Ape_i : in std_logic_vector(3 downto 0); --! Proportional coefficient -- Sigma-delta (PSEUDO-STATIC) sigma_delta_clk_div_i : in std_logic_vector(15 downto 0); --! Sigma-delta clock divider modulo (unsigned) -- Mirror compensation (PSEUDO-STATIC) enable_mirror_i : in std_logic; --! Enable mirror compensation scheme (a part of phase variation is compensated using this scheme, otherwise a full compensation is performed) Adco_i : in std_logic_vector(47 downto 0); --! DCO coefficient for mirror compensation ----------------------------------------------------------------- ------------------------- DCO Interface ------------------------- ----------------------------------------------------------------- -- Phase accumulated (debugging) phase_acc_o : out std_logic_vector(15 downto 0); --! phase accumulated output (integrated output) --! This is an integer signed number, the LSB is the bit 0 -- Operation error operation_error_o : out std_logic; --! error output indicating that a clk_en_i pulse has arrived before the done_i signal arrived from the previous strobe_o request --! this is mainly useful for debugging purposes, for the final user this can be removed if the user is sure about all the operational parameters of the TCLink loop control -- DCO interface strobe_o : out std_logic; --! pulse synchronous to clk_sys_i to activate a shift in the DCO (only captured rising edge, so a signal larger than a pulse is also fine) inc_ndec_o : out std_logic; --! 1 increments, 0 decrements (modulated output) phase_step_o : out std_logic; --! number of units to shift the DCO done_i : in std_logic; --! pulse synchronous to clk_sys_i to indicate a DCO shift was performed ----------------------------------------------------------------- ------------------- TCLink tester signals ----------------------- ----------------------------------------------------------------- debug_tester_enable_stimulis_i : in std_logic; --! enable stimulis for TCLink debug_tester_fcw_i : in std_logic_vector(9 downto 0); --! frequency control word for NCO (unsigned) debug_tester_nco_scale_i : in std_logic_vector(4 downto 0); --! scale NCO output debug_tester_enable_stock_out_i : in std_logic; --! enable output data stock debug_tester_addr_read_i : in std_logic_vector(9 downto 0); --! read address for reading stocked TCLink phase accumulated results debug_tester_data_read_o : out std_logic_vector(15 downto 0) --! data of stocked TCLink phase accumulated results ); end component tclink; ---------------------------------------------------------------------------------- ------------------------------- Control Interface -------------------------------- component vio_control_vcu118 port ( clk : in std_logic; probe_in0 : in std_logic_vector(0 downto 0); probe_in1 : in std_logic_vector(0 downto 0); probe_in2 : in std_logic_vector(0 downto 0); probe_in3 : in std_logic_vector(0 downto 0); probe_in4 : in std_logic_vector(0 downto 0); probe_in5 : in std_logic_vector(0 downto 0); probe_in6 : in std_logic_vector(0 downto 0); probe_in7 : in std_logic_vector(0 downto 0); probe_in8 : in std_logic_vector(0 downto 0); probe_in9 : in std_logic_vector(0 downto 0); probe_in10 : in std_logic_vector(0 downto 0); probe_in11 : in std_logic_vector(0 downto 0); probe_in12 : in std_logic_vector(0 downto 0); probe_in13 : in std_logic_vector(0 downto 0); probe_in14 : in std_logic_vector(0 downto 0); probe_in15 : in std_logic_vector(0 downto 0); probe_in16 : in std_logic_vector(0 downto 0); probe_in17 : in std_logic_vector(15 downto 0); probe_in18 : in std_logic_vector(6 downto 0); probe_in19 : in std_logic_vector(31 downto 0); probe_in20 : in std_logic_vector(0 downto 0); probe_in21 : in std_logic_vector(15 downto 0); probe_in22 : in std_logic_vector(0 downto 0); probe_in23 : in std_logic_vector(0 downto 0); probe_in24 : in std_logic_vector(31 downto 0); probe_in25 : in std_logic_vector(47 downto 0); probe_in26 : in std_logic_vector(15 downto 0); probe_in27 : in std_logic_vector(0 downto 0); probe_in28 : in std_logic_vector(15 downto 0); probe_in29 : in std_logic_vector(0 downto 0); probe_out0 : out std_logic_vector(0 downto 0); probe_out1 : out std_logic_vector(0 downto 0); probe_out2 : out std_logic_vector(0 downto 0); probe_out3 : out std_logic_vector(0 downto 0); probe_out4 : out std_logic_vector(0 downto 0); probe_out5 : out std_logic_vector(0 downto 0); probe_out6 : out std_logic_vector(0 downto 0); probe_out7 : out std_logic_vector(0 downto 0); probe_out8 : out std_logic_vector(0 downto 0); probe_out9 : out std_logic_vector(2 downto 0); probe_out10 : out std_logic_vector(0 downto 0); probe_out11 : out std_logic_vector(3 downto 0); probe_out12 : out std_logic_vector(0 downto 0); probe_out13 : out std_logic_vector(3 downto 0); probe_out14 : out std_logic_vector(0 downto 0); probe_out15 : out std_logic_vector(0 downto 0); probe_out16 : out std_logic_vector(9 downto 0); probe_out17 : out std_logic_vector(15 downto 0); probe_out18 : out std_logic_vector(31 downto 0); probe_out19 : out std_logic_vector(6 downto 0); probe_out20 : out std_logic_vector(0 downto 0); probe_out21 : out std_logic_vector(0 downto 0); probe_out22 : out std_logic_vector(0 downto 0); probe_out23 : out std_logic_vector(3 downto 0); probe_out24 : out std_logic_vector(0 downto 0); probe_out25 : out std_logic_vector(0 downto 0); probe_out26 : out std_logic_vector(0 downto 0); probe_out27 : out std_logic_vector(0 downto 0); probe_out28 : out std_logic_vector(0 downto 0); probe_out29 : out std_logic_vector(0 downto 0); probe_out30 : out std_logic_vector(0 downto 0); probe_out31 : out std_logic_vector(47 downto 0); probe_out32 : out std_logic_vector(15 downto 0); probe_out33 : out std_logic_vector(11 downto 0); probe_out34 : out std_logic_vector(47 downto 0); probe_out35 : out std_logic_vector(3 downto 0); probe_out36 : out std_logic_vector(0 downto 0); probe_out37 : out std_logic_vector(3 downto 0); probe_out38 : out std_logic_vector(15 downto 0); probe_out39 : out std_logic_vector(0 downto 0); probe_out40 : out std_logic_vector(47 downto 0); probe_out41 : out std_logic_vector(0 downto 0); probe_out42 : out std_logic_vector(9 downto 0); probe_out43 : out std_logic_vector(4 downto 0); probe_out44 : out std_logic_vector(0 downto 0); probe_out45 : out std_logic_vector(9 downto 0); probe_out46 : out std_logic_vector(0 downto 0); probe_out47 : out std_logic_vector(47 downto 0) ); end component vio_control_vcu118; ---------------------------------------------------------------------------------- ---------------------------------- Miscellaneous ---------------------------------- component bit_synchronizer is generic ( INITIALIZE : std_logic_vector(4 downto 0) := "00000" ); port ( clk_in : in std_logic; i_in : in std_logic; o_out : out std_logic ); end component; ----------------------------------------------------------------------------------- begin ---------------------------------- User datapath ---------------------------------- -- tx user datapath reset not_mgt_tx_ready <= not mgt_tx_ready; tx_reset_bit_synchronizer : bit_synchronizer port map( clk_in => mgt_txusrclk, i_in => not_mgt_tx_ready, o_out => tx_reset ); prbsgen_frame <= data_i; -- BUG BUG BUG -- This is a bit tricky. We need to derive a pulse in the MGT TX -- clock domain from data_valid_i. We can't pass it through a full -- CDC first, though, because by that time the corresponding data -- will be gone. tx_strobe_gen : process (mgt_txusrclk) variable var_tx_strobe_gen_cnt : integer range 0 to 7; begin if rising_edge(mgt_txusrclk) then if tx_reset = '1' then tx_tx_strobe <= '0'; var_tx_strobe_gen_cnt := 7; else if var_tx_strobe_gen_cnt = 7 and data_valid_i = '1' then tx_tx_strobe <= '1'; var_tx_strobe_gen_cnt := var_tx_strobe_gen_cnt - 1; elsif var_tx_strobe_gen_cnt = 6 then tx_tx_strobe <= '0'; var_tx_strobe_gen_cnt := var_tx_strobe_gen_cnt - 1; elsif var_tx_strobe_gen_cnt = 0 then var_tx_strobe_gen_cnt := 7; else var_tx_strobe_gen_cnt := var_tx_strobe_gen_cnt - 1; end if; end if; -- tx_strobe_gen_cnt <= -- std_logic_vector(to_unsigned(var_tx_strobe_gen_cnt, -- tx_strobe_gen_cnt'length)); end if; end process; -- A similar problem as above holds, but in the opposite direction, -- for the RX frame alignment strobe. rx_strobe_gen : process (mgt_rxusrclk) variable var_rx_strobe_gen_cnt : integer range 0 to 7; begin if rising_edge(mgt_rxusrclk) then if rx_reset = '1' then rx_strobe <= '0'; var_rx_strobe_gen_cnt := 7; else if var_rx_strobe_gen_cnt = 7 and rx_uplinkClkOutEn = '1' then rx_strobe <= '1'; elsif var_rx_strobe_gen_cnt = 7 then var_rx_strobe_gen_cnt := var_rx_strobe_gen_cnt; elsif var_rx_strobe_gen_cnt = 0 then rx_strobe <= '0'; var_rx_strobe_gen_cnt := 7; else var_rx_strobe_gen_cnt := var_rx_strobe_gen_cnt - 1; end if; end if; rx_strobe_gen_cnt <= std_logic_vector(to_unsigned(var_rx_strobe_gen_cnt, rx_strobe_gen_cnt'length)); end if; end process; -- BUG BUG BUG end --! ---- lpGBT-FE tx --tx_tx_strobe <= prbsgen_strobe when rising_edge(mgt_txusrclk); -- tx_tx_strobe <= data_valid_i; tx_tx_data(229 downto 0) <= prbsgen_frame(229 downto 0); tx_tx_ec <= prbsgen_frame(231 downto 230); tx_tx_ic <= prbsgen_frame(233 downto 232); cmp_lpgbt_fe_tx : lpgbt_fe_tx generic map( g_MGT_WORD_WIDTH => c_mgtWordWidth, g_DATA_RATE => DATARATE_10G24, g_FEC => FEC5 ) port map( reset_i => tx_reset , mgt_clock_i => mgt_txusrclk , tx_strobe_i => tx_tx_strobe , tx_data_i => tx_tx_data , tx_ec_i => tx_tx_ec , tx_ic_i => tx_tx_ic , tx_word_o => tx_tx_word , scrambler_bypass_i => tx_scrambler_bypass , interleaver_bypass_i => tx_interleaver_bypass, tx_error_i => tx_tx_error ); tx_scrambler_bypass <= '0'; tx_interleaver_bypass <= '0'; tx_tx_error <= (others => '0'); -- rx user datapath reset rx_reset_n <= '0' when (mgt_rx_ready = '0' or mgt_rxprbssel /= "0000") else '1'; -- Reset when not in normal operation mode rx_reset_bit_synchronizer : bit_synchronizer port map ( clk_in => mgt_rxusrclk, i_in => rx_reset_n, o_out => rx_uplinkRst_n ); rx_reset <= not rx_uplinkRst_n; --! ---- lpGBT-FPGA rx cmp_lpgbtfpga_uplink_fixed : lpgbtfpga_uplink_fixed generic map( -- General configuration DATARATE => DATARATE_10G24 , FEC => FEC5 , -- Expert parameters c_multicyleDelay => c_multicyleDelay , c_clockRatio => c_clockRatio , c_mgtWordWidth => c_mgtWordWidth , c_allowedFalseHeader => c_allowedFalseHeader , c_allowedFalseHeaderOverN => c_allowedFalseHeaderOverN, c_requiredTrueHeader => c_requiredTrueHeader , c_bitslip_mindly => c_bitslip_mindly , c_bitslip_waitdly => c_bitslip_waitdly , -- Bitslip expert parameters for fixed latency applications - EBSM c_resetOnEven => c_resetOnEven , c_resetDuration => c_resetDuration ) port map( -- Clock and reset clk_freeRunningClk_i => clk_sys_i , uplinkClk_i => mgt_rxusrclk , uplinkClkOutEn_o => rx_uplinkClkOutEn , uplinkRst_n_i => rx_uplinkRst_n , -- Input mgt_word_o => rx_mgt_word , -- Data USErData_o => rx_USErData , EcData_o => rx_EcData , IcData_o => rx_IcData , -- Control bypassInterleaver_i => rx_bypassInterleaver, bypassFECEncoder_i => rx_bypassFECEncoder , bypassScrambler_i => rx_bypassScrambler , -- Transceiver control mgt_bitslipCtrl_o => rx_mgt_bitslipCtrl , -- Fixed-latency applications rst_mgtctrler_i => '0', rst_rstoneven_o => open, -- Status dataCorrected_o => rx_dataCorrected , IcCorrected_o => rx_IcCorrected , EcCorrected_o => rx_EcCorrected , rdy_o => rx_rdy ); rx_bypassInterleaver <= '0'; rx_bypassFECEncoder <= '0'; rx_bypassScrambler <= '0'; tx_ready_o <= mgt_tx_ready; rx_ready_o <= mgt_rx_ready; data_o <= rx_IcData & rx_EcData & rx_USErData; -- data_valid_o <= rx_uplinkClkOutEn; data_valid_o <= rx_strobe; ----------------------------------------------------------------------------------- --------------------------------- Clock Output ---------------------------------- txusrclk_o <= mgt_txusrclk; rxusrclk_o <= mgt_rxusrclk; ---------------------------------------------------------------------------------- mgt_reset_all <= reset_all_i; mgt_reset_tx_pll_and_datapath <= reset_tx_i; mgt_reset_rx_datapath <= reset_rx_i; ---------------------------- FPGA Transceiver and infrastructure ------------------ cmp_mgt_master_timing : gth_master_timing port map( -- Directly connected to top-level gtwiz_reset_clk_freerun_in(0) => clk_sys_i , gtwiz_reset_all_in(0) => mgt_reset_all , gtwiz_reset_tx_pll_and_datapath_in(0) => mgt_reset_tx_pll_and_datapath , gtwiz_reset_tx_datapath_in(0) => mgt_reset_tx_datapath , gtwiz_reset_rx_pll_and_datapath_in(0) => mgt_reset_rx_pll_and_datapath , gtwiz_reset_rx_datapath_in(0) => mgt_reset_rx_datapath , gtwiz_userdata_tx_in => tx_tx_word , gtwiz_userdata_rx_out => rx_mgt_word , gtrefclk00_in(0) => trxrefclk_i , qpll0outclk_out => open , qpll0outrefclk_out => open , gthrxn_in(0) => rx_n_i , gthrxp_in(0) => rx_p_i , loopback_in => mgt_loopback , rxdfelpmreset_in(0) => mgt_rxeq_dfelpmreset, rxlpmen_in(0) => mgt_rxeq_rxlpmen, rxlpmgcovrden_in(0) => mgt_rxeq_rxlpmgcovrden , rxlpmhfovrden_in(0) => mgt_rxeq_rxlpmhfovrden , rxlpmlfklovrden_in(0) => mgt_rxeq_rxlpmlfklovrden , rxlpmosovrden_in(0) => mgt_rxeq_rxlpmosovrden , rxslide_in(0) => rx_mgt_bitslipCtrl , gtpowergood_out => open , gthtxn_out(0) => tx_n_o , gthtxp_out(0) => tx_p_o , -- Connected to infrastructure rxusrclk_in(0) => mgt_rxusrclk , rxusrclk2_in(0) => mgt_rxusrclk , txusrclk_in(0) => mgt_txusrclk , txusrclk2_in(0) => mgt_txusrclk , gtwiz_userclk_tx_active_in => gtwiz_userclk_tx_active_in , gtwiz_userclk_rx_active_in => gtwiz_userclk_rx_active_in , gtwiz_buffbypass_rx_reset_in => gtwiz_buffbypass_rx_reset_in , gtwiz_buffbypass_rx_start_user_in => gtwiz_buffbypass_rx_start_user_in , gtwiz_buffbypass_rx_done_out => gtwiz_buffbypass_rx_done_out , gtwiz_buffbypass_rx_error_out => gtwiz_buffbypass_rx_error_out , gtwiz_reset_rx_cdr_stable_out => gtwiz_reset_rx_cdr_stable_out , gtwiz_reset_tx_done_out => gtwiz_reset_tx_done_out , gtwiz_reset_rx_done_out => gtwiz_reset_rx_done_out , qpll0lock_out => qpll0lock_out , dmonitorclk_in => dmonitorclk_in , drpaddr_in => drpaddr_in , drpclk_in => drpclk_in , drpdi_in => drpdi_in , drpen_in => drpen_in , drpwe_in => drpwe_in , rxpolarity_in => rxpolarity_in , rxprbscntreset_in => rxprbscntreset_in , rxprbssel_in => rxprbssel_in , txpippmen_in => txpippmen_in , txpippmovrden_in => txpippmovrden_in , txpippmpd_in => txpippmpd_in , txpippmsel_in => txpippmsel_in , txpippmstepsize_in => txpippmstepsize_in , txpolarity_in => txpolarity_in , txprbsforceerr_in => txprbsforceerr_in , txprbssel_in => txprbssel_in , dmonitorout_out => dmonitorout_out , drpdo_out => drpdo_out , drprdy_out => drprdy_out , rxoutclk_out => rxoutclk_out , rxpmaresetdone_out => rxpmaresetdone_out , rxprbserr_out => rxprbserr_out , rxprbslocked_out => rxprbslocked_out , txbufstatus_out => txbufstatus_out , txoutclk_out => txoutclk_out , txpmaresetdone_out => txpmaresetdone_out ); cmp_mgt_fixed_phase : mgt_fixed_phase port map( --*************************************************************** --************************ USER PORTS *************************** --*************************************************************** ----------------------------------------------------------------- --------------------- System clock / resets --------------------- ----------------------------------------------------------------- -- System clock (must come from a free-running source) clk_sys_i => clk_sys_i, reset_i => mgt_reset_all, clk_txusr_i => mgt_txusrclk, clk_rxusr_i => mgt_rxusrclk, tx_ready_o => mgt_tx_ready, rx_ready_o => mgt_rx_ready, ----------------------------------------------------------------- --------------- Low-level transceiver control/debug ------------- ----------------------------------------------------------------- -- Polarity control txpolarity_i => mgt_txpolarity , rxpolarity_i => mgt_rxpolarity , -- Built-in PRBS testing structures txprbsforceerr_i => mgt_txprbsforceerr , txprbssel_i => mgt_txprbssel , rxprbscntreset_i => mgt_rxprbscntreset , rxprbssel_i => mgt_rxprbssel , rxprbserr_o => mgt_rxprbserr , rxprbslocked_o => mgt_rxprbslocked , ----------------------------------------------------------------- ----------------------------- DRP ------------------------------- ----------------------------------------------------------------- -- Dynamic reconfiguration port drpwe_i => mgt_drpwe , drpen_i => mgt_drpen , drpaddr_i => mgt_drpaddr , drpdi_i => mgt_drpdi , drprdy_latched_o => mgt_drprdy_latched , drpdo_o => mgt_drpdo , ----------------------------------------------------------------- ------------------- HPTD IP - tx Phase Aligner ------------------ ----------------------------------------------------------------- -- Configuration tx_fifo_fill_pd_max_i => mgt_hptd_tx_fifo_fill_pd_max, tx_pi_phase_calib_i => mgt_hptd_tx_pi_phase_calib , tx_ui_align_calib_i => mgt_hptd_tx_ui_align_calib , -- tx PI phase value tx_pi_phase_o => mgt_hptd_tx_pi_phase , -- tx fifo fill level phase detector tx_fifo_fill_pd_o => mgt_hptd_tx_fifo_fill_pd , -- Fine Phase Shift Interface (only valid once transceiver is ready tx_ready_o=1) ps_strobe_i => mgt_hptd_ps_strobe , ps_inc_ndec_i => mgt_hptd_ps_inc_ndec , ps_phase_step_i => mgt_hptd_ps_phase_step , ps_done_latched_o => mgt_hptd_ps_done_latched , ----------------------------------------------------------------- --------------------- Digital Monitor --------------------------- ----------------------------------------------------------------- dmonitor_o => mgt_rxeq_dmonitor , --*************************************************************** --************************* MGT PORTS *************************** --*************************************************************** -- Status mgt_reset_tx_done_i => gtwiz_reset_tx_done_out(0), mgt_reset_rx_done_i => aux_gtwiz_reset_rx_done(0), --! DRP bus / sync to clk_sys_i mgt_drpaddr_o => drpaddr_in , mgt_drpclk_o => drpclk_in(0) , mgt_drpdi_o => drpdi_in , mgt_drpen_o => drpen_in(0) , mgt_drpwe_o => drpwe_in(0) , mgt_drpdo_i => drpdo_out , mgt_drprdy_i => drprdy_out(0) , --! Digital Monitor / sync to clk_sys_i mgt_dmonitorclk_o => dmonitorclk_in(0) , mgt_dmonitorout_i => dmonitorout_out , --! Polarity mgt_txpolarity_o => txpolarity_in(0) , mgt_rxpolarity_o => rxpolarity_in(0) , --! tx PRBS / sync to clk_txusr_i mgt_txprbsforceerr_o => txprbsforceerr_in(0), mgt_txprbssel_o => txprbssel_in , --! rx PRBS / sync to clk_rxusr_i mgt_rxprbserr_i => rxprbserr_out(0) , mgt_rxprbslocked_i => rxprbslocked_out(0) , mgt_rxprbscntreset_o => rxprbscntreset_in(0), mgt_rxprbssel_o => rxprbssel_in , --! tx PI + FIFO Fill level flag / sync to clk_txusr_i mgt_txbufstatus_i => txbufstatus_out , mgt_txpippmen_o => txpippmen_in(0) , mgt_txpippmovrden_o => txpippmovrden_in(0), mgt_txpippmpd_o => txpippmpd_in(0) , mgt_txpippmsel_o => txpippmsel_in(0) , mgt_txpippmstepsize_o => txpippmstepsize_in ); aux_gtwiz_reset_rx_done(0) <= gtwiz_reset_rx_done_out(0) and gtwiz_buffbypass_rx_done_out(0); cmp_mgt_clock_reset : mgt_clock_reset port map( --*************************************************************** --************************ USER PORTS *************************** --*************************************************************** ----------------------------------------------------------------- --------------------- System clock / resets --------------------- ----------------------------------------------------------------- -- System clock (must come from a free-running source) clk_sys_i => clk_sys_i, -- MGT reset status (sync to clk_sys_i) txpll_lock_o => mgt_txpll_lock , rxpll_lock_o => mgt_rxpll_lock , buffbypass_rx_done_o => mgt_buffbypass_rx_done , buffbypass_rx_error_o => mgt_buffbypass_rx_error , reset_rx_cdr_stable_o => mgt_reset_rx_cdr_stable , reset_tx_done_o => mgt_reset_tx_done , reset_rx_done_o => mgt_reset_rx_done , rxpmaresetdone_o => mgt_rxpmaresetdone , txpmaresetdone_o => mgt_txpmaresetdone , --*************************************************************** --************************* MGT PORTS *************************** --*************************************************************** --! rx Buffer bypass reset mgt_gtwiz_buffbypass_rx_reset_o => gtwiz_buffbypass_rx_reset_in(0) , mgt_gtwiz_buffbypass_rx_start_user_o => gtwiz_buffbypass_rx_start_user_in(0), -- User clocks txusrclk_o => mgt_txusrclk , rxusrclk_o => mgt_rxusrclk , --! User clock network mgt_gtwiz_userclk_tx_active_o => gtwiz_userclk_tx_active_in(0) , mgt_gtwiz_userclk_rx_active_o => gtwiz_userclk_rx_active_in(0) , mgt_txoutclk_i => txoutclk_out(0) , mgt_rxoutclk_i => rxoutclk_out(0) , --! Reset status mgt_qpll0lock_i => qpll0lock_out(0) , mgt_qpll1lock_i => qpll0lock_out(0) , mgt_gtwiz_reset_rx_cdr_stable_i => gtwiz_reset_rx_cdr_stable_out(0) , mgt_gtwiz_buffbypass_rx_done_i => gtwiz_buffbypass_rx_done_out(0) , mgt_gtwiz_buffbypass_rx_error_i => gtwiz_buffbypass_rx_error_out(0) , mgt_gtwiz_reset_tx_done_i => gtwiz_reset_tx_done_out(0) , mgt_gtwiz_reset_rx_done_i => gtwiz_reset_rx_done_out(0) , mgt_txpmaresetdone_i => txpmaresetdone_out(0) , mgt_rxpmaresetdone_i => rxpmaresetdone_out(0) ); mgt_reset_rx_pll_and_datapath <= mgt_reset_user_rx_pll_and_datapath; mgt_hptd_ps_strobe <= tclink_hptd_ps_strobe when tclink_close_loop='1' else user_hptd_ps_strobe; mgt_hptd_ps_inc_ndec <= tclink_hptd_ps_inc_ndec when tclink_close_loop='1' else user_hptd_ps_inc_ndec; mgt_hptd_ps_phase_step <= "000"&tclink_hptd_ps_phase_step when tclink_close_loop='1' else user_hptd_ps_phase_step; tclink_hptd_ps_done_latched <= mgt_hptd_ps_done_latched when tclink_close_loop='1' else '0'; user_hptd_ps_done_latched <= mgt_hptd_ps_done_latched when tclink_close_loop='0' else '0'; ---------------------------------------------------------------------------------- ------------------------------------- TCLink ------------------------------------ cmp_mmcm_tclink : mmcm_tclink port map (-- Clock in ports -- Clock out ports clk_out1 => clk_offset, -- Status and control signals resetn => gtwiz_reset_tx_done_out(0), locked => clk_offset_locked_async, clk_in1 => mgt_txusrclk ); tclink_master_rx_slide_mode <= '1'; -- PCS MODE cmp_tclink : tclink generic map( g_ENABLE_TESTER_IMPLEMENTATION => True ) port map( ----------------------------------------------------------------- --------------------- System clock / resets --------------------- ----------------------------------------------------------------- clk_sys_i => clk_sys_i, tx_ready_i => mgt_tx_ready, rx_ready_i => rx_frame_locked_sync, ----------------------------------------------------------------- ------------------------- Phase-detector ------------------------ ----------------------------------------------------------------- ---- clocks clk_tx_i => mgt_txusrclk, clk_rx_i => mgt_rxusrclk, clk_offset_i => clk_offset, ---- configuration (PSEUDO-STATIC) metastability_deglitch_i => tclink_metastability_deglitch, phase_detector_navg_i => tclink_phase_detector_navg, ---- status phase_detector_o => tclink_phase_detector, ----------------------------------------------------------------- ----------------------- TCLink Controller ----------------------- ----------------------------------------------------------------- ---- error-processing configuration (Read user guide on how to deal with these signals) modulo_carrier_period_i => tclink_modulo_carrier_period, offset_error_i => tclink_offset_error, error_controller_o => tclink_error_controller, master_rx_slide_mode_i => tclink_master_rx_slide_mode, master_rx_ui_period_i => tclink_master_rx_ui_period , master_rx_slide_clk_i => mgt_rxusrclk , master_mgt_rx_ready_i => mgt_reset_rx_done , master_rx_slide_i => rx_mgt_bitslipCtrl , ---- Controller dynamics (Read user guide on how to deal with this signal) close_loop_i => tclink_close_loop, -- Loop controller (PSEUDO-STATIC) Aie_i => tclink_Aie, Aie_enable_i => tclink_Aie_enable, Ape_i => tclink_Ape, -- Sigma-delta (PSEUDO-STATIC) sigma_delta_clk_div_i => tclink_sigma_delta_clk_div, -- Mirror compensation (PSEUDO-STATIC) enable_mirror_i => tclink_enable_mirror, Adco_i => tclink_Adco, ----------------------------------------------------------------- ------------------------- DCO Interface ------------------------- ----------------------------------------------------------------- -- Phase accumulated (debugging) phase_acc_o => tclink_phase_acc, -- Operation error operation_error_o => tclink_operation_error, -- DCO interface strobe_o => tclink_hptd_ps_strobe, inc_ndec_o => tclink_hptd_ps_inc_ndec, phase_step_o => tclink_hptd_ps_phase_step, done_i => tclink_hptd_ps_done_latched, ----------------------------------------------------------------- ------------------- TCLink tester signals ----------------------- ----------------------------------------------------------------- debug_tester_enable_stimulis_i => tclink_debug_tester_enable_stimulis, debug_tester_fcw_i => tclink_debug_tester_fcw, debug_tester_nco_scale_i => tclink_debug_tester_nco_scale, debug_tester_enable_stock_out_i => tclink_debug_tester_enable_stock_out, debug_tester_addr_read_i => tclink_debug_tester_addr_read, debug_tester_data_read_o => tclink_debug_tester_data_read ); ---------------------------------------------------------------------------------- ------------------------------- Control Interface -------------------------------- -- All outputs have an initial value of 0 unless indicated cmp_vio_control : vio_control_vcu118 port map( clk => clk_sys_i , probe_in0(0) => rx_frame_locked_sync , probe_in1(0) => '0',--rx_prbs_locked_sync , probe_in2(0) => '0' , probe_in3(0) => mgt_txpll_lock , probe_in4(0) => mgt_rxpll_lock , probe_in5(0) => mgt_buffbypass_rx_done , probe_in6(0) => mgt_buffbypass_rx_error , probe_in7(0) => mgt_reset_rx_cdr_stable , probe_in8(0) => mgt_reset_tx_done , probe_in9(0) => mgt_reset_rx_done , probe_in10(0) => mgt_rxpmaresetdone , probe_in11(0) => mgt_txpmaresetdone , probe_in12(0) => mgt_tx_ready , probe_in13(0) => mgt_rx_ready , probe_in14(0) => mgt_rxprbserr , probe_in15(0) => mgt_rxprbslocked , probe_in16(0) => mgt_drprdy_latched , probe_in17 => mgt_drpdo , probe_in18 => mgt_hptd_tx_pi_phase , probe_in19 => mgt_hptd_tx_fifo_fill_pd , probe_in20(0) => user_hptd_ps_done_latched , probe_in21 => mgt_rxeq_dmonitor , probe_in22(0) => '0' , probe_in23(0) => '0' , probe_in24 => tclink_phase_detector , probe_in25 => tclink_error_controller , probe_in26 => tclink_phase_acc , probe_in27(0) => tclink_operation_error , probe_in28 => tclink_debug_tester_data_read , probe_in29(0) => clk_offset_locked , probe_out0(0) => mgt_rxeq_dfelpmreset , probe_out1(0) => mgt_rxeq_rxlpmen , probe_out2(0) => open, --mgt_reset_all , probe_out3(0) => open, --mgt_reset_tx_pll_and_datapath , probe_out4(0) => mgt_reset_tx_datapath , probe_out5(0) => mgt_reset_user_rx_pll_and_datapath , probe_out6(0) => open, --mgt_reset_rx_datapath , probe_out7(0) => mgt_txpolarity , probe_out8(0) => mgt_rxpolarity , probe_out9 => mgt_loopback , probe_out10(0) => mgt_txprbsforceerr , probe_out11 => mgt_txprbssel , probe_out12(0) => mgt_rxprbscntreset , probe_out13 => mgt_rxprbssel , probe_out14(0) => mgt_drpwe , probe_out15(0) => mgt_drpen , probe_out16 => mgt_drpaddr , probe_out17 => mgt_drpdi , probe_out18 => mgt_hptd_tx_fifo_fill_pd_max , -- Initial value: 0x00400000 probe_out19 => mgt_hptd_tx_pi_phase_calib , probe_out20(0) => mgt_hptd_tx_ui_align_calib , probe_out21(0) => user_hptd_ps_strobe , probe_out22(0) => user_hptd_ps_inc_ndec , probe_out23 => user_hptd_ps_phase_step , probe_out24(0) => mgt_rxeq_rxlpmgcovrden , probe_out25(0) => mgt_rxeq_rxlpmhfovrden , probe_out26(0) => mgt_rxeq_rxlpmlfklovrden , probe_out27(0) => mgt_rxeq_rxlpmosovrden , probe_out28 => open , probe_out29 => open , probe_out30(0) => tclink_close_loop , probe_out31 => tclink_offset_error , probe_out32 => tclink_metastability_deglitch , probe_out33 => tclink_phase_detector_navg , probe_out34 => tclink_modulo_carrier_period , probe_out35 => tclink_Aie , probe_out36(0) => tclink_Aie_enable , probe_out37 => tclink_Ape , probe_out38 => tclink_sigma_delta_clk_div , probe_out39(0) => tclink_enable_mirror , probe_out40 => tclink_Adco , probe_out41(0) => tclink_debug_tester_enable_stimulis, probe_out42 => tclink_debug_tester_fcw , probe_out43 => tclink_debug_tester_nco_scale , probe_out44(0) => tclink_debug_tester_enable_stock_out , probe_out45 => tclink_debug_tester_addr_read , probe_out46 => open , probe_out47 => tclink_master_rx_ui_period ); clk_offset_locked_bit_synchronizer : bit_synchronizer port map( clk_in => clk_sys_i , i_in => clk_offset_locked_async, o_out => clk_offset_locked ); rx_frame_locked_bit_synchronizer : bit_synchronizer port map( clk_in => clk_sys_i , i_in => rx_rdy , o_out => rx_frame_locked_sync ); end architecture rtl; --============================================================================== -- architecture end --==============================================================================