--======================================================================
-- Interface component holding all DTH TCDS2 backplane links as well
-- as a wrapper with PRBS generator/checker helpers for link testing.
--======================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

use work.ipbus.all;
use work.ipbus_reg_types.all;

use work.tclink_lpgbt10G_pkg.all;
use work.tcds2_link_pkg.all;

--==================================================

entity dth_tcds2_backplane_interface_with_prbs is
  generic (
    G_LINK_SPEED : TCDS2_LINK_SPEED := TCDS2_LINK_SPEED_10G
  );
  port (
    clk_ipb : in std_logic;
    rst_ipb : in std_logic;
    ipb_in  : in ipb_wbus;
    ipb_out : out ipb_rbus;

    clk_gp_125mhz : in std_logic;

    clk_40_tx : in std_logic;
    clk_40_rx : out std_logic;

    mgt_refclk_slot2 : in std_logic;
    mgt_refclk_slot3 : in std_logic;
    mgt_refclk_slot4 : in std_logic;
    mgt_refclk_slot5 : in std_logic;
    mgt_refclk_slot6 : in std_logic;
    mgt_refclk_slot7 : in std_logic;
    mgt_refclk_slot8 : in std_logic;
    mgt_refclk_slot9 : in std_logic;
    mgt_refclk_slot10 : in std_logic;
    mgt_refclk_slot11 : in std_logic;
    mgt_refclk_slot12 : in std_logic;
    mgt_refclk_slot13 : in std_logic;
    mgt_refclk_slot14 : in std_logic;

    ttc2_frame_slot2 : in tcds2_frame;
    ttc2_frame_slot3 : in tcds2_frame;
    ttc2_frame_slot4 : in tcds2_frame;
    ttc2_frame_slot5 : in tcds2_frame;
    ttc2_frame_slot6 : in tcds2_frame;
    ttc2_frame_slot7 : in tcds2_frame;
    ttc2_frame_slot8 : in tcds2_frame;
    ttc2_frame_slot9 : in tcds2_frame;
    ttc2_frame_slot10 : in tcds2_frame;
    ttc2_frame_slot11 : in tcds2_frame;
    ttc2_frame_slot12 : in tcds2_frame;
    ttc2_frame_slot13 : in tcds2_frame;
    ttc2_frame_slot14 : in tcds2_frame;

    tts2_frame_slot2 : out tcds2_frame;
    tts2_frame_slot3 : out tcds2_frame;
    tts2_frame_slot4 : out tcds2_frame;
    tts2_frame_slot5 : out tcds2_frame;
    tts2_frame_slot6 : out tcds2_frame;
    tts2_frame_slot7 : out tcds2_frame;
    tts2_frame_slot8 : out tcds2_frame;
    tts2_frame_slot9 : out tcds2_frame;
    tts2_frame_slot10 : out tcds2_frame;
    tts2_frame_slot11 : out tcds2_frame;
    tts2_frame_slot12 : out tcds2_frame;
    tts2_frame_slot13 : out tcds2_frame;
    tts2_frame_slot14 : out tcds2_frame
  );

end dth_tcds2_backplane_interface_with_prbs;

--==================================================

architecture arch of dth_tcds2_backplane_interface_with_prbs is

  ------------------------------------------
  -- PRBS-related settings and signals.
  ------------------------------------------

  -- The PRBS polynomial. Notation: x^23 + x^18 + 1 (PRBS-23).
  constant c_PRBS_POLYNOMIAL : std_logic_vector(23 downto 0) := "100001000000000000000001";

  -- Number of correct received frames for PRBS checker to lock.
  constant c_PRBS_GOOD_FRAME_TO_LOCK : integer := 15;
  -- Number of incorrect received frames for PRBS checker to unlock.
  constant c_PRBS_BAD_FRAME_TO_UNLOCK : integer := 5;

  constant c_PRBS_FRAME_WIDTH : integer := c_TCDS2_FRAME_WIDTH;

  signal not_master_core_stat_mgt_tx_ready          : std_logic_vector(c_MASTER_NUMBER_CHANNELS-1 downto 0);
  signal prbsgen_master_reset                       : std_logic_vector(c_MASTER_NUMBER_CHANNELS-1 downto 0);
  signal prbsgen_master_en                          : std_logic_vector(c_MASTER_NUMBER_CHANNELS-1 downto 0);
  signal prbsgen_master_load                        : std_logic_vector(c_MASTER_NUMBER_CHANNELS-1 downto 0);
  signal prbsgen_master_frame                       : user_data_array(c_MASTER_NUMBER_CHANNELS-1 downto 0);
  signal prbsgen_master_data_valid                  : std_logic_vector(c_MASTER_NUMBER_CHANNELS-1 downto 0);

  signal not_master_core_stat_rx_frame_locked       : std_logic_vector(c_MASTER_NUMBER_CHANNELS-1 downto 0);
  signal prbschk_master_reset                       : std_logic_vector(c_MASTER_NUMBER_CHANNELS-1 downto 0);
  signal prbschk_master_frame                       : user_data_array(c_MASTER_NUMBER_CHANNELS-1 downto 0);
  signal prbschk_master_en                          : std_logic_vector(c_MASTER_NUMBER_CHANNELS-1 downto 0);
  signal prbschk_master_gen                         : user_data_array(c_MASTER_NUMBER_CHANNELS-1 downto 0);
  signal prbschk_master_error                       : std_logic_vector(c_MASTER_NUMBER_CHANNELS-1 downto 0);
  signal prbschk_master_locked                      : std_logic_vector(c_MASTER_NUMBER_CHANNELS-1 downto 0);
  signal prbschk_master_locked_sync                 : std_logic_vector(c_MASTER_NUMBER_CHANNELS-1 downto 0);

  -- PRBS generator signals.
  signal prbsgen_reset : std_logic;
  signal prbsgen_reset_manual : std_logic;
  signal prbsgen_strobe : std_logic;
   -- PRBS generator polynomial seed.
  constant c_PRBS_SEED : std_logic_vector(c_PRBS_POLYNOMIAL'length - 2 downto 0) := (others => '1');
  -- PRBS generator output data.
  signal prbsgen_frame : std_logic_vector(c_PRBS_FRAME_WIDTH - 1 downto 0);

  -- PRBS checker signals.
  signal not_master_quad0_ch0_core_stat_rx_frame_locked : std_logic;
  signal prbschk_master_quad0_ch0_reset : std_logic;
  signal prbschk_reset : std_logic;
  signal prbschk_reset_manual : std_logic;
  signal prbschk_data : std_logic_vector(c_PRBS_FRAME_WIDTH - 1 downto 0);
  signal prbschk_frame : std_logic_vector(c_PRBS_FRAME_WIDTH - 1 downto 0);
  signal prbschk_strobe : std_logic;
  signal prbschk_error : std_logic;
  signal prbschk_locked : std_logic;

  signal ctrl_prbs : ipb_reg_v(0 downto 0);
  signal stat_prbs : ipb_reg_v(3 downto 0);

begin

  -- ------------------------------------------
  -- -- IPBus address decoder.
  -- ------------------------------------------

  -- fabric : entity work.ipbus_fabric_sel
  --   generic map (
  --     NSLV      => N_SLAVES,
  --     SEL_WIDTH => IPBUS_SEL_WIDTH
  --   )
  --   port map (
  --     ipb_in          => ipb_in,
  --     ipb_out         => ipb_out,
  --     sel             => ipbus_sel_dth_tcds2_backplane_interface(ipb_in.ipb_addr),
  --     ipb_to_slaves   => ipbw,
  --     ipb_from_slaves => ipbr
  --   );

  dth_tcds2_backplane_interface : entity work.dth_tcds2_backplane_interface_with_prbs is
    generic map (
      G_LINK_SPEED => G_LINK_SPEED
    );
    port map (
      clk_ipb => clk_ipb,
      rst_ipb => rst_ipb,
      ipb_in  => ipb_in,
      ipb_out => ipb_out,

      clk_gp_125mhz => clk_gp_125mhz,

      clk_40_tx => clk_40_tx,
      clk_40_rx => clk_40_rx,

      mgt_refclk_slot2 => mgt_refclk_slot2,
      mgt_refclk_slot3 => mgt_refclk_slot3,
      mgt_refclk_slot4 => mgt_refclk_slot4,
      mgt_refclk_slot5 => mgt_refclk_slot5,
      mgt_refclk_slot6 => mgt_refclk_slot6,
      mgt_refclk_slot7 => mgt_refclk_slot7,
      mgt_refclk_slot8 => mgt_refclk_slot8,
      mgt_refclk_slot9 => mgt_refclk_slot9,
      mgt_refclk_slot10 => mgt_refclk_slot10,
      mgt_refclk_slot11 => mgt_refclk_slot11,
      mgt_refclk_slot12 => mgt_refclk_slot12,
      mgt_refclk_slot13 => mgt_refclk_slot13,
      mgt_refclk_slot14 => mgt_refclk_slot14,

      ttc2_frame_slot2 => ttc2_frame_slot2,
      ttc2_frame_slot3 => ttc2_frame_slot3,
      ttc2_frame_slot4 => ttc2_frame_slot4,
      ttc2_frame_slot5 => ttc2_frame_slot5,
      ttc2_frame_slot6 => ttc2_frame_slot6,
      ttc2_frame_slot7 => ttc2_frame_slot7,
      ttc2_frame_slot8 => ttc2_frame_slot8,
      ttc2_frame_slot9 => ttc2_frame_slot9,
      ttc2_frame_slot10 => ttc2_frame_slot10,
      ttc2_frame_slot11 => ttc2_frame_slot11,
      ttc2_frame_slot12 => ttc2_frame_slot12,
      ttc2_frame_slot13 => ttc2_frame_slot13,
      ttc2_frame_slot14 => ttc2_frame_slot14
    );

  end dth_tcds2_backplane_interface_with_prbs;

end arch;

--======================================================================