--====================================================================== -- Interface component holding all DTH TCDS2 backend links. --====================================================================== library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; use work.ipbus.all; use work.ipbus_reg_types.all; use work.tclink_lpgbt10G_pkg.all; use work.tcds2_link_pkg.all; use work.tcds2_link_speed_pkg.all; use work.ipbus_decode_dth_tcds2_backend_interface.all; --================================================== entity dth_tcds2_backend_interface is generic ( G_LINK_SPEED : tcds2_link_speed_t := TCDS2_LINK_SPEED_10G ); port ( clk_ipb : in std_logic; rst_ipb : in std_logic; ipb_in : in ipb_wbus; ipb_out : out ipb_rbus; ------------ clk_gp_125mhz : in std_logic; clk_40_tx : in std_logic; clk_40_rx : out std_logic_vector; mgt_refclk_slot2 : in std_logic; mgt_refclk_slot3 : in std_logic; mgt_refclk_slot4 : in std_logic; mgt_refclk_slot5 : in std_logic; mgt_refclk_slot6 : in std_logic; mgt_refclk_slot7 : in std_logic; mgt_refclk_slot8 : in std_logic; mgt_refclk_slot9 : in std_logic; mgt_refclk_slot10 : in std_logic; mgt_refclk_slot11 : in std_logic; mgt_refclk_slot12 : in std_logic; mgt_refclk_slot13 : in std_logic; mgt_refclk_slot14 : in std_logic; mgt_refclk_daq_fpga : in std_logic; ------------ tcds2_backplane_slot2_tx_p : out std_logic; tcds2_backplane_slot2_tx_n : out std_logic; tcds2_backplane_slot2_rx_p : in std_logic; tcds2_backplane_slot2_rx_n : in std_logic; tcds2_backplane_slot3_tx_p : out std_logic; tcds2_backplane_slot3_tx_n : out std_logic; tcds2_backplane_slot3_rx_p : in std_logic; tcds2_backplane_slot3_rx_n : in std_logic; tcds2_backplane_slot4_tx_p : out std_logic; tcds2_backplane_slot4_tx_n : out std_logic; tcds2_backplane_slot4_rx_p : in std_logic; tcds2_backplane_slot4_rx_n : in std_logic; tcds2_backplane_slot5_tx_p : out std_logic; tcds2_backplane_slot5_tx_n : out std_logic; tcds2_backplane_slot5_rx_p : in std_logic; tcds2_backplane_slot5_rx_n : in std_logic; tcds2_backplane_slot6_tx_p : out std_logic; tcds2_backplane_slot6_tx_n : out std_logic; tcds2_backplane_slot6_rx_p : in std_logic; tcds2_backplane_slot6_rx_n : in std_logic; tcds2_backplane_slot7_tx_p : out std_logic; tcds2_backplane_slot7_tx_n : out std_logic; tcds2_backplane_slot7_rx_p : in std_logic; tcds2_backplane_slot7_rx_n : in std_logic; tcds2_backplane_slot8_tx_p : out std_logic; tcds2_backplane_slot8_tx_n : out std_logic; tcds2_backplane_slot8_rx_p : in std_logic; tcds2_backplane_slot8_rx_n : in std_logic; tcds2_backplane_slot9_tx_p : out std_logic; tcds2_backplane_slot9_tx_n : out std_logic; tcds2_backplane_slot9_rx_p : in std_logic; tcds2_backplane_slot9_rx_n : in std_logic; tcds2_backplane_slot10_tx_p : out std_logic; tcds2_backplane_slot10_tx_n : out std_logic; tcds2_backplane_slot10_rx_p : in std_logic; tcds2_backplane_slot10_rx_n : in std_logic; tcds2_backplane_slot11_tx_p : out std_logic; tcds2_backplane_slot11_tx_n : out std_logic; tcds2_backplane_slot11_rx_p : in std_logic; tcds2_backplane_slot11_rx_n : in std_logic; tcds2_backplane_slot12_tx_p : out std_logic; tcds2_backplane_slot12_tx_n : out std_logic; tcds2_backplane_slot12_rx_p : in std_logic; tcds2_backplane_slot12_rx_n : in std_logic; tcds2_backplane_slot13_tx_p : out std_logic; tcds2_backplane_slot13_tx_n : out std_logic; tcds2_backplane_slot13_rx_p : in std_logic; tcds2_backplane_slot13_rx_n : in std_logic; tcds2_backplane_slot14_tx_p : out std_logic; tcds2_backplane_slot14_tx_n : out std_logic; tcds2_backplane_slot14_rx_p : in std_logic; tcds2_backplane_slot14_rx_n : in std_logic; tcds2_daq_fpga_tx_p : out std_logic; tcds2_daq_fpga_tx_n : out std_logic; tcds2_daq_fpga_rx_p : in std_logic; tcds2_daq_fpga_rx_n : in std_logic; ------------ ttc2_frame_slot2 : in tcds2_frame_t; ttc2_frame_slot3 : in tcds2_frame_t; ttc2_frame_slot4 : in tcds2_frame_t; ttc2_frame_slot5 : in tcds2_frame_t; ttc2_frame_slot6 : in tcds2_frame_t; ttc2_frame_slot7 : in tcds2_frame_t; ttc2_frame_slot8 : in tcds2_frame_t; ttc2_frame_slot9 : in tcds2_frame_t; ttc2_frame_slot10 : in tcds2_frame_t; ttc2_frame_slot11 : in tcds2_frame_t; ttc2_frame_slot12 : in tcds2_frame_t; ttc2_frame_slot13 : in tcds2_frame_t; ttc2_frame_slot14 : in tcds2_frame_t; ttc2_frame_daq_fpga : in tcds2_frame_t; ------------ tts2_frame_slot2 : out tcds2_frame_t; tts2_frame_slot3 : out tcds2_frame_t; tts2_frame_slot4 : out tcds2_frame_t; tts2_frame_slot5 : out tcds2_frame_t; tts2_frame_slot6 : out tcds2_frame_t; tts2_frame_slot7 : out tcds2_frame_t; tts2_frame_slot8 : out tcds2_frame_t; tts2_frame_slot9 : out tcds2_frame_t; tts2_frame_slot10 : out tcds2_frame_t; tts2_frame_slot11 : out tcds2_frame_t; tts2_frame_slot12 : out tcds2_frame_t; tts2_frame_slot13 : out tcds2_frame_t; tts2_frame_slot14 : out tcds2_frame_t; tts2_frame_daq_fpga : out tcds2_frame_t ); end dth_tcds2_backend_interface; --================================================== architecture arch of dth_tcds2_backend_interface is ------------------------------------------ -- IPBus read/write buses. ------------------------------------------ signal ipbw : ipb_wbus_array(N_SLAVES - 1 downto 0); signal ipbr : ipb_rbus_array(N_SLAVES - 1 downto 0); -- Signals related to the MMCM for the TCLink heterodyne offset -- clock. signal master_clk_offset : std_logic; signal master_clk_offset_locked : std_logic; -- Utility type definition used for the instantiation of the -- back-end links. type integer_array is array(natural range <>) of integer; -- Definition of channels and quads for all back-end links. -- Quads: -- 0: 226 -- 1: 228 -- 2: 230 -- 3: 233 -- 4: 127 -- 5: 129 -- 6: 131 -- 7: 132 -- 8: 232 -- Channels: -- 0 : Slot 2 : GTH 233-1 (X0Y37). -- 1 : Slot 3 : GTH 228-1 (X0Y17). -- 2 : Slot 4 : GTH 230-3 (X0Y27). -- 3 : Slot 5 : GTH 226-3 (X0Y11). -- 4 : Slot 6 : GTH 230-1 (X0Y25). -- 5 : Slot 7 : GTH 228-3 (X0Y19). -- 6 : Slot 8 : GTY 129-0 (X0Y8). -- 7 : Slot 9 : GTY 127-0 (X0Y0). -- 8 : Slot 10 : GTY 129-2 (X0Y10). -- 9 : Slot 11 : GTY 127-2 (X0Y2). -- 10: Slot 12 : GTY 131-0 (X0Y16). -- 11: Slot 13 : GTY 131-3 (X0Y19). -- 12: Slot 14 : GTY 132-0 (X0Y20). -- 13: DAQ FPGA: GTH 232-1 (X0Y33). constant C_MASTER_NUMBER_QUADS : integer := 9; constant C_MASTER_NUMBER_CHANNELS : integer := 14; -- C_MASTER_CHANNEL_QUADS associates each channel with a quad -- following the convention (CHANNEL_NUMBER => QUAD_NUMBER). constant C_MASTER_CHANNEL_QUADS : integer_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0) := ( 0 => 3, 1 => 1, 2 => 2, 3 => 0, 4 => 2, 5 => 1, 6 => 5, 7 => 4, 8 => 5, 9 => 4, 10 => 6, 11 => 6, 12 => 7, 13 => 8 ); -- C_MASTER_PLL_RESET_CHANNELS defines a 'master' channel in each -- quad for the common PLL reset following the convention -- (QUAD_NUMBER => CHANNEL_NUMBER). constant C_MASTER_PLL_RESET_CHANNELS : integer_array(C_MASTER_NUMBER_QUADS - 1 downto 0) := ( 0 => 3, 1 => 1, 2 => 2, 3 => 0, 4 => 7, 5 => 6, 6 => 10, 7 => 12, 8 => 13 ); -- Similar to the above, but mapping channels to transceiver types. constant C_MGT_TYPE_GTH : integer := 0; constant C_MGT_TYPE_GTY : integer := 1; constant C_MASTER_QUAD_MGT_TYPES : integer_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0) := ( 0 => C_MGT_TYPE_GTH, 1 => C_MGT_TYPE_GTH, 2 => C_MGT_TYPE_GTH, 3 => C_MGT_TYPE_GTH, 4 => C_MGT_TYPE_GTH, 5 => C_MGT_TYPE_GTH, 6 => C_MGT_TYPE_GTY, 7 => C_MGT_TYPE_GTY, 8 => C_MGT_TYPE_GTY, 9 => C_MGT_TYPE_GTY, 10 => C_MGT_TYPE_GTY, 11 => C_MGT_TYPE_GTY, 12 => C_MGT_TYPE_GTY, 13 => C_MGT_TYPE_GTH ); constant N_SLV_SLOT_I_CSR : integer_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0) := ( 0 => N_SLV_SLOT_2_CSR, 1 => N_SLV_SLOT_3_CSR, 2 => N_SLV_SLOT_4_CSR, 3 => N_SLV_SLOT_5_CSR, 4 => N_SLV_SLOT_6_CSR, 5 => N_SLV_SLOT_7_CSR, 6 => N_SLV_SLOT_8_CSR, 7 => N_SLV_SLOT_9_CSR, 8 => N_SLV_SLOT_10_CSR, 9 => N_SLV_SLOT_11_CSR, 10 => N_SLV_SLOT_12_CSR, 11 => N_SLV_SLOT_13_CSR, 12 => N_SLV_SLOT_14_CSR, 13 => N_SLV_DAQ_FPGA_CSR ); constant N_SLV_SLOT_I_SPY_FRAME_TX : integer_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0) := ( 0 => N_SLV_SLOT_2_SPY_FRAME_TX, 1 => N_SLV_SLOT_3_SPY_FRAME_TX, 2 => N_SLV_SLOT_4_SPY_FRAME_TX, 3 => N_SLV_SLOT_5_SPY_FRAME_TX, 4 => N_SLV_SLOT_6_SPY_FRAME_TX, 5 => N_SLV_SLOT_7_SPY_FRAME_TX, 6 => N_SLV_SLOT_8_SPY_FRAME_TX, 7 => N_SLV_SLOT_9_SPY_FRAME_TX, 8 => N_SLV_SLOT_10_SPY_FRAME_TX, 9 => N_SLV_SLOT_11_SPY_FRAME_TX, 10 => N_SLV_SLOT_12_SPY_FRAME_TX, 11 => N_SLV_SLOT_13_SPY_FRAME_TX, 12 => N_SLV_SLOT_14_SPY_FRAME_TX, 13 => N_SLV_DAQ_FPGA_SPY_FRAME_TX ); constant N_SLV_SLOT_I_SPY_FRAME_RX : integer_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0) := ( 0 => N_SLV_SLOT_2_SPY_FRAME_RX, 1 => N_SLV_SLOT_3_SPY_FRAME_RX, 2 => N_SLV_SLOT_4_SPY_FRAME_RX, 3 => N_SLV_SLOT_5_SPY_FRAME_RX, 4 => N_SLV_SLOT_6_SPY_FRAME_RX, 5 => N_SLV_SLOT_7_SPY_FRAME_RX, 6 => N_SLV_SLOT_8_SPY_FRAME_RX, 7 => N_SLV_SLOT_9_SPY_FRAME_RX, 8 => N_SLV_SLOT_10_SPY_FRAME_RX, 9 => N_SLV_SLOT_11_SPY_FRAME_RX, 10 => N_SLV_SLOT_12_SPY_FRAME_RX, 11 => N_SLV_SLOT_13_SPY_FRAME_RX, 12 => N_SLV_SLOT_14_SPY_FRAME_RX, 13 => N_SLV_DAQ_FPGA_SPY_FRAME_RX ); signal master_trxrefclk : std_logic_vector(C_MASTER_NUMBER_QUADS - 1 downto 0); signal master_tx_p : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal master_tx_n : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal master_rx_p : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal master_rx_n : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); -- NOTE: The following array is created for all channels but only -- the RESET of the C_MASTER_PLL_RESET_CHANNELS shall be used. signal master_mgt_reset_all : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0) := (others => '0'); -- NOTE: The following array is created for all channels but only -- the RESET of the C_MASTER_PLL_RESET_CHANNELS shall be used. signal master_mgt_reset_tx_pll_and_datapath : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0) := (others => '0'); signal master_mgt_reset_tx_datapath : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal master_mgt_reset_rx_datapath : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); -- Signals: mgt_user_clock <-> MGT. signal master_txusrclk : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal master_rxusrclk : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal master_mgt_txoutclk : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal master_mgt_rxoutclk : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); -- Signals: Common <-> MGT. -- A dummy signal for the PLL reset is created for all channels -- (master_mgt_to_common_qpll0reset). Only the signals in -- C_MASTER_PLL_RESET_CHANNELS will be connected to the common via -- master_mgt_to_common_qpll0reset_common. signal master_mgt_to_common_qpll0reset : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal master_mgt_to_common_qpll0reset_common : std_logic_vector(C_MASTER_NUMBER_QUADS - 1 downto 0); signal master_common_to_mgt_qpll0lock : std_logic_vector(C_MASTER_NUMBER_QUADS - 1 downto 0); signal master_common_to_mgt_qpll0outclk : std_logic_vector(C_MASTER_NUMBER_QUADS - 1 downto 0); signal master_common_to_mgt_qpll0outrefclk : std_logic_vector(C_MASTER_NUMBER_QUADS - 1 downto 0); signal master_common_to_mgt_qpll1outclk : std_logic_vector(C_MASTER_NUMBER_QUADS - 1 downto 0); signal master_common_to_mgt_qpll1outrefclk : std_logic_vector(C_MASTER_NUMBER_QUADS - 1 downto 0); -- Signals: Core control and status. signal master_core_ctrl : tr_core_control_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal master_core_stat : tr_core_status_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal master_tclink_ctrl : tr_tclink_control_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal master_tclink_stat : tr_tclink_status_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); type counter_array is array(C_MASTER_NUMBER_CHANNELS downto 0) of std_logic_vector(31 downto 0); signal channel_unlock_count : counter_array; -- Signals: Core <-> MGT. signal master_mgt_ctrl : tr_core_to_mgt_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal master_mgt_stat : tr_mgt_to_core_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); -- TCLink frame width and data rate definitions. constant C_TCDS2_INTERFACE_FRAME_WIDTH : natural := get_tcds2_frame_width(G_LINK_SPEED); constant C_TCDS2_INTERFACE_DATA_RATE : natural := get_tcds2_tclink_data_rate(G_LINK_SPEED); -- Data frames. type user_data_array is array(natural range <>) of std_logic_vector(C_TCDS2_FRAME_WIDTH - 1 downto 0); signal ttc2_frames : user_data_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal tts2_frames : user_data_array(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal refclk_by_slot : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal clk_40_rx_tmp : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); ------------------------------------------ -- Control and status registers for all channels. signal ctrl_channels : ipb_reg_v(C_MASTER_NUMBER_CHANNELS - 1 downto 0); signal stat_channels : ipb_reg_v(3 * C_MASTER_NUMBER_CHANNELS - 1 downto 0); ------------------------------------------ -- Misc. signal is_link_speed_10g : boolean; signal clkdiv_i : std_logic_vector(C_MASTER_NUMBER_CHANNELS - 1 downto 0); ------------------------------------------ begin ------------------------------------------ -- IPBus address decoder. ------------------------------------------ fabric : entity work.ipbus_fabric_sel generic map ( NSLV => N_SLAVES, SEL_WIDTH => IPBUS_SEL_WIDTH ) port map ( ipb_in => ipb_in, ipb_out => ipb_out, sel => ipbus_sel_dth_tcds2_backend_interface(ipb_in.ipb_addr), ipb_to_slaves => ipbw, ipb_from_slaves => ipbr ); ------------------------------------------ -- MGT reference clock mapping. ------------------------------------------ refclk_by_slot(0) <= mgt_refclk_slot2; refclk_by_slot(1) <= mgt_refclk_slot3; refclk_by_slot(2) <= mgt_refclk_slot4; refclk_by_slot(3) <= mgt_refclk_slot5; refclk_by_slot(4) <= mgt_refclk_slot6; refclk_by_slot(5) <= mgt_refclk_slot7; refclk_by_slot(6) <= mgt_refclk_slot8; refclk_by_slot(7) <= mgt_refclk_slot9; refclk_by_slot(8) <= mgt_refclk_slot10; refclk_by_slot(9) <= mgt_refclk_slot11; refclk_by_slot(10) <= mgt_refclk_slot12; refclk_by_slot(11) <= mgt_refclk_slot13; refclk_by_slot(12) <= mgt_refclk_slot14; refclk_by_slot(13) <= mgt_refclk_daq_fpga; -- NOTE: The index is the quad number. -- 0: 226 -- 1: 228 -- 2: 230 -- 3: 233 -- 4: 127 -- 5: 129 -- 6: 131 -- 7: 132 generate_refclks : for i in C_MASTER_NUMBER_QUADS - 1 downto 0 generate master_trxrefclk(i) <= refclk_by_slot(C_MASTER_PLL_RESET_CHANNELS(i)); end generate; ------------------------------------------ -- MGT signal mapping. ------------------------------------------ tcds2_backplane_slot2_tx_p <= master_tx_p(0); tcds2_backplane_slot2_tx_n <= master_tx_n(0); master_rx_p(0) <= tcds2_backplane_slot2_rx_p; master_rx_n(0) <= tcds2_backplane_slot2_rx_n; tcds2_backplane_slot3_tx_p <= master_tx_p(1); tcds2_backplane_slot3_tx_n <= master_tx_n(1); master_rx_p(1) <= tcds2_backplane_slot3_rx_p; master_rx_n(1) <= tcds2_backplane_slot3_rx_n; tcds2_backplane_slot4_tx_p <= master_tx_p(2); tcds2_backplane_slot4_tx_n <= master_tx_n(2); master_rx_p(2) <= tcds2_backplane_slot4_rx_p; master_rx_n(2) <= tcds2_backplane_slot4_rx_n; tcds2_backplane_slot5_tx_p <= master_tx_p(3); tcds2_backplane_slot5_tx_n <= master_tx_n(3); master_rx_p(3) <= tcds2_backplane_slot5_rx_p; master_rx_n(3) <= tcds2_backplane_slot5_rx_n; tcds2_backplane_slot6_tx_p <= master_tx_p(4); tcds2_backplane_slot6_tx_n <= master_tx_n(4); master_rx_p(4) <= tcds2_backplane_slot6_rx_p; master_rx_n(4) <= tcds2_backplane_slot6_rx_n; tcds2_backplane_slot7_tx_p <= master_tx_p(5); tcds2_backplane_slot7_tx_n <= master_tx_n(5); master_rx_p(5) <= tcds2_backplane_slot7_rx_p; master_rx_n(5) <= tcds2_backplane_slot7_rx_n; tcds2_backplane_slot8_tx_p <= master_tx_p(6); tcds2_backplane_slot8_tx_n <= master_tx_n(6); master_rx_p(6) <= tcds2_backplane_slot8_rx_p; master_rx_n(6) <= tcds2_backplane_slot8_rx_n; tcds2_backplane_slot9_tx_p <= master_tx_p(7); tcds2_backplane_slot9_tx_n <= master_tx_n(7); master_rx_p(7) <= tcds2_backplane_slot9_rx_p; master_rx_n(7) <= tcds2_backplane_slot9_rx_n; tcds2_backplane_slot10_tx_p <= master_tx_p(8); tcds2_backplane_slot10_tx_n <= master_tx_n(8); master_rx_p(8) <= tcds2_backplane_slot10_rx_p; master_rx_n(8) <= tcds2_backplane_slot10_rx_n; tcds2_backplane_slot11_tx_p <= master_tx_p(9); tcds2_backplane_slot11_tx_n <= master_tx_n(9); master_rx_p(9) <= tcds2_backplane_slot11_rx_p; master_rx_n(9) <= tcds2_backplane_slot11_rx_n; tcds2_backplane_slot12_tx_p <= master_tx_p(10); tcds2_backplane_slot12_tx_n <= master_tx_n(10); master_rx_p(10) <= tcds2_backplane_slot12_rx_p; master_rx_n(10) <= tcds2_backplane_slot12_rx_n; tcds2_backplane_slot13_tx_p <= master_tx_p(11); tcds2_backplane_slot13_tx_n <= master_tx_n(11); master_rx_p(11) <= tcds2_backplane_slot13_rx_p; master_rx_n(11) <= tcds2_backplane_slot13_rx_n; tcds2_backplane_slot14_tx_p <= master_tx_p(12); tcds2_backplane_slot14_tx_n <= master_tx_n(12); master_rx_p(12) <= tcds2_backplane_slot14_rx_p; master_rx_n(12) <= tcds2_backplane_slot14_rx_n; tcds2_daq_fpga_tx_p <= master_tx_p(13); tcds2_daq_fpga_tx_n <= master_tx_n(13); master_rx_p(13) <= tcds2_daq_fpga_rx_p; master_rx_n(13) <= tcds2_daq_fpga_rx_n; ------------------------------------------ -- Data frame mapping. ------------------------------------------ ttc2_frames(0) <= ttc2_frame_slot2; ttc2_frames(1) <= ttc2_frame_slot3; ttc2_frames(2) <= ttc2_frame_slot4; ttc2_frames(3) <= ttc2_frame_slot5; ttc2_frames(4) <= ttc2_frame_slot6; ttc2_frames(5) <= ttc2_frame_slot7; ttc2_frames(6) <= ttc2_frame_slot8; ttc2_frames(7) <= ttc2_frame_slot9; ttc2_frames(8) <= ttc2_frame_slot10; ttc2_frames(9) <= ttc2_frame_slot11; ttc2_frames(10) <= ttc2_frame_slot12; ttc2_frames(11) <= ttc2_frame_slot13; ttc2_frames(12) <= ttc2_frame_slot14; ttc2_frames(13) <= ttc2_frame_daq_fpga; tts2_frame_slot2 <= tts2_frames(0); tts2_frame_slot3 <= tts2_frames(1); tts2_frame_slot4 <= tts2_frames(2); tts2_frame_slot5 <= tts2_frames(3); tts2_frame_slot6 <= tts2_frames(4); tts2_frame_slot7 <= tts2_frames(5); tts2_frame_slot8 <= tts2_frames(6); tts2_frame_slot9 <= tts2_frames(7); tts2_frame_slot10 <= tts2_frames(8); tts2_frame_slot11 <= tts2_frames(9); tts2_frame_slot12 <= tts2_frames(10); tts2_frame_slot13 <= tts2_frames(11); tts2_frame_slot14 <= tts2_frames(12); tts2_frame_daq_fpga <= tts2_frames(13); ------------------------------------------ -- MMCM generating the TCLink 'offset' heterodyne clock for all -- backend TCDS2 links. ------------------------------------------ -- NOTE: The TX clock of the first channel is taken here to drive -- the MMCM. This should be okay, because _all_ TX clocks are -- expected to be exactly the same. mmcm_tclink : entity work.mmcm_tclink_ultrascale_plus port map ( clk_in1 => master_txusrclk(0), clk_out1 => master_clk_offset, resetn => master_mgt_stat(0).gtwiz_reset_tx_done_out(0), locked => master_clk_offset_locked ); ------------------------------------------ -- MGT quads. ------------------------------------------ generate_quads : for i in C_MASTER_NUMBER_QUADS - 1 downto 0 generate if_gth : if C_MASTER_QUAD_MGT_TYPES(C_MASTER_PLL_RESET_CHANNELS(i)) = C_MGT_TYPE_GTH generate gth_master_timing_gthe4_common_wrapper : entity work.gth_master_timing_gthe4_common_wrapper port map ( gthe4_common_bgbypassb => std_logic_vector'("1"), gthe4_common_bgmonitorenb => std_logic_vector'("1"), gthe4_common_bgpdb => std_logic_vector'("1"), gthe4_common_bgrcalovrd => std_logic_vector'("11111"), gthe4_common_bgrcalovrdenb => std_logic_vector'("1"), gthe4_common_drpaddr => std_logic_vector'("0000000000000000"), gthe4_common_drpclk => std_logic_vector'("0"), gthe4_common_drpdi => std_logic_vector'("0000000000000000"), gthe4_common_drpen => std_logic_vector'("0"), gthe4_common_drpwe => std_logic_vector'("0"), gthe4_common_gtgrefclk0 => std_logic_vector'("0"), gthe4_common_gtgrefclk1 => std_logic_vector'("0"), gthe4_common_gtnorthrefclk00 => std_logic_vector'("0"), gthe4_common_gtnorthrefclk01 => std_logic_vector'("0"), gthe4_common_gtnorthrefclk10 => std_logic_vector'("0"), gthe4_common_gtnorthrefclk11 => std_logic_vector'("0"), gthe4_common_gtrefclk00(0) => master_trxrefclk(i), gthe4_common_gtrefclk01(0) => master_trxrefclk(i), gthe4_common_gtrefclk10 => std_logic_vector'("0"), gthe4_common_gtrefclk11 => std_logic_vector'("0"), gthe4_common_gtsouthrefclk00 => std_logic_vector'("0"), gthe4_common_gtsouthrefclk01 => std_logic_vector'("0"), gthe4_common_gtsouthrefclk10 => std_logic_vector'("0"), gthe4_common_gtsouthrefclk11 => std_logic_vector'("0"), gthe4_common_pcierateqpll0 => std_logic_vector'("000"), gthe4_common_pcierateqpll1 => std_logic_vector'("000"), gthe4_common_pmarsvd0 => std_logic_vector'("00000000"), gthe4_common_pmarsvd1 => std_logic_vector'("00000000"), gthe4_common_qpll0clkrsvd0 => std_logic_vector'("0"), gthe4_common_qpll0clkrsvd1 => std_logic_vector'("0"), gthe4_common_qpll0fbdiv => std_logic_vector'("00000000"), gthe4_common_qpll0lockdetclk => std_logic_vector'("0"), gthe4_common_qpll0locken => std_logic_vector'("1"), gthe4_common_qpll0pd => std_logic_vector'("0"), gthe4_common_qpll0refclksel => std_logic_vector'("001"), gthe4_common_qpll0reset(0) => master_mgt_to_common_qpll0reset_common(i), gthe4_common_qpll1clkrsvd0 => std_logic_vector'("0"), gthe4_common_qpll1clkrsvd1 => std_logic_vector'("0"), gthe4_common_qpll1fbdiv => std_logic_vector'("00000000"), gthe4_common_qpll1lockdetclk => std_logic_vector'("0"), gthe4_common_qpll1locken => std_logic_vector'("0"), gthe4_common_qpll1pd => std_logic_vector'("1"), gthe4_common_qpll1refclksel => std_logic_vector'("001"), gthe4_common_qpll1reset => std_logic_vector'("0"), gthe4_common_qpllrsvd1 => std_logic_vector'("00000000"), gthe4_common_qpllrsvd2 => std_logic_vector'("00000"), gthe4_common_qpllrsvd3 => std_logic_vector'("00000"), gthe4_common_qpllrsvd4 => std_logic_vector'("00000000"), gthe4_common_rcalenb => std_logic_vector'("1"), gthe4_common_sdm0data => std_logic_vector'("0000000000000000000000000"), gthe4_common_sdm0reset => std_logic_vector'("0"), gthe4_common_sdm0toggle => std_logic_vector'("0"), gthe4_common_sdm0width => std_logic_vector'("00"), gthe4_common_sdm1data => std_logic_vector'("0000000000000000000000000"), gthe4_common_sdm1reset => std_logic_vector'("0"), gthe4_common_sdm1toggle => std_logic_vector'("0"), gthe4_common_sdm1width => std_logic_vector'("00"), gthe4_common_tcongpi => std_logic_vector'("0000000000"), gthe4_common_tconpowerup => std_logic_vector'("0"), gthe4_common_tconreset => std_logic_vector'("00"), gthe4_common_tconrsvdin1 => std_logic_vector'("00"), gthe4_common_drpdo => open, gthe4_common_drprdy => open, gthe4_common_pmarsvdout0 => open, gthe4_common_pmarsvdout1 => open, gthe4_common_qpll0fbclklost => open, gthe4_common_qpll0lock(0) => master_common_to_mgt_qpll0lock(i), gthe4_common_qpll0outclk(0) => master_common_to_mgt_qpll0outclk(i), gthe4_common_qpll0outrefclk(0) => master_common_to_mgt_qpll0outrefclk(i), gthe4_common_qpll0refclklost => open, gthe4_common_qpll1fbclklost => open, gthe4_common_qpll1lock => open, gthe4_common_qpll1outclk(0) => master_common_to_mgt_qpll1outclk(i), gthe4_common_qpll1outrefclk(0) => master_common_to_mgt_qpll1outrefclk(i), gthe4_common_qpll1refclklost => open, gthe4_common_qplldmonitor0 => open, gthe4_common_qplldmonitor1 => open, gthe4_common_refclkoutmonitor0 => open, gthe4_common_refclkoutmonitor1 => open, gthe4_common_rxrecclk0sel => open, gthe4_common_rxrecclk1sel => open, gthe4_common_sdm0finalout => open, gthe4_common_sdm0testdata => open, gthe4_common_sdm1finalout => open, gthe4_common_sdm1testdata => open, gthe4_common_tcongpo => open, gthe4_common_tconrsvdout0 => open ); end generate; if_gty : if C_MASTER_QUAD_MGT_TYPES(C_MASTER_PLL_RESET_CHANNELS(i)) = C_MGT_TYPE_GTY generate gty_master_timing_gtye4_common_wrapper : entity work.gty_master_timing_gtye4_common_wrapper port map ( gtye4_common_bgbypassb => std_logic_vector'("1"), gtye4_common_bgmonitorenb => std_logic_vector'("1"), gtye4_common_bgpdb => std_logic_vector'("1"), gtye4_common_bgrcalovrd => std_logic_vector'("10000"), gtye4_common_bgrcalovrdenb => std_logic_vector'("1"), gtye4_common_drpaddr => std_logic_vector'("0000000000000000"), gtye4_common_drpclk => std_logic_vector'("0"), gtye4_common_drpdi => std_logic_vector'("0000000000000000"), gtye4_common_drpen => std_logic_vector'("0"), gtye4_common_drpwe => std_logic_vector'("0"), gtye4_common_gtgrefclk0 => std_logic_vector'("0"), gtye4_common_gtgrefclk1 => std_logic_vector'("0"), gtye4_common_gtnorthrefclk00 => std_logic_vector'("0"), gtye4_common_gtnorthrefclk01 => std_logic_vector'("0"), gtye4_common_gtnorthrefclk10 => std_logic_vector'("0"), gtye4_common_gtnorthrefclk11 => std_logic_vector'("0"), gtye4_common_gtrefclk00(0) => master_trxrefclk(i), gtye4_common_gtrefclk01(0) => master_trxrefclk(i), gtye4_common_gtrefclk10 => std_logic_vector'("0"), gtye4_common_gtrefclk11 => std_logic_vector'("0"), gtye4_common_gtsouthrefclk00 => std_logic_vector'("0"), gtye4_common_gtsouthrefclk01 => std_logic_vector'("0"), gtye4_common_gtsouthrefclk10 => std_logic_vector'("0"), gtye4_common_gtsouthrefclk11 => std_logic_vector'("0"), gtye4_common_pcierateqpll0 => std_logic_vector'("000"), gtye4_common_pcierateqpll1 => std_logic_vector'("000"), gtye4_common_pmarsvd0 => std_logic_vector'("00000000"), gtye4_common_pmarsvd1 => std_logic_vector'("00000000"), gtye4_common_qpll0clkrsvd0 => std_logic_vector'("0"), gtye4_common_qpll0clkrsvd1 => std_logic_vector'("0"), gtye4_common_qpll0fbdiv => std_logic_vector'("00000000"), gtye4_common_qpll0lockdetclk => std_logic_vector'("0"), gtye4_common_qpll0locken => std_logic_vector'("1"), gtye4_common_qpll0pd => std_logic_vector'("0"), gtye4_common_qpll0refclksel => std_logic_vector'("001"), gtye4_common_qpll0reset(0) => master_mgt_to_common_qpll0reset_common(i), gtye4_common_qpll1clkrsvd0 => std_logic_vector'("0"), gtye4_common_qpll1clkrsvd1 => std_logic_vector'("0"), gtye4_common_qpll1fbdiv => std_logic_vector'("00000000"), gtye4_common_qpll1lockdetclk => std_logic_vector'("0"), gtye4_common_qpll1locken => std_logic_vector'("0"), gtye4_common_qpll1pd => std_logic_vector'("1"), gtye4_common_qpll1refclksel => std_logic_vector'("001"), gtye4_common_qpll1reset => std_logic_vector'("0"), gtye4_common_qpllrsvd1 => std_logic_vector'("00000000"), gtye4_common_qpllrsvd2 => std_logic_vector'("00000"), gtye4_common_qpllrsvd3 => std_logic_vector'("00000"), gtye4_common_qpllrsvd4 => std_logic_vector'("00000000"), gtye4_common_rcalenb => std_logic_vector'("1"), gtye4_common_sdm0data => std_logic_vector'("0000000000000000000000000"), gtye4_common_sdm0reset => std_logic_vector'("0"), gtye4_common_sdm0toggle => std_logic_vector'("0"), gtye4_common_sdm0width => std_logic_vector'("00"), gtye4_common_sdm1data => std_logic_vector'("0000000000000000000000000"), gtye4_common_sdm1reset => std_logic_vector'("0"), gtye4_common_sdm1toggle => std_logic_vector'("0"), gtye4_common_sdm1width => std_logic_vector'("00"), gtye4_common_ubcfgstreamen => std_logic_vector'("0"), gtye4_common_ubdo => std_logic_vector'("0000000000000000"), gtye4_common_ubdrdy => std_logic_vector'("0"), gtye4_common_ubenable => std_logic_vector'("0"), gtye4_common_ubgpi => std_logic_vector'("00"), gtye4_common_ubintr => std_logic_vector'("00"), gtye4_common_ubiolmbrst => std_logic_vector'("0"), gtye4_common_ubmbrst => std_logic_vector'("0"), gtye4_common_ubmdmcapture => std_logic_vector'("0"), gtye4_common_ubmdmdbgrst => std_logic_vector'("0"), gtye4_common_ubmdmdbgupdate => std_logic_vector'("0"), gtye4_common_ubmdmregen => std_logic_vector'("0000"), gtye4_common_ubmdmshift => std_logic_vector'("0"), gtye4_common_ubmdmsysrst => std_logic_vector'("0"), gtye4_common_ubmdmtck => std_logic_vector'("0"), gtye4_common_ubmdmtdi => std_logic_vector'("0"), gtye4_common_drpdo => open, gtye4_common_drprdy => open, gtye4_common_pmarsvdout0 => open, gtye4_common_pmarsvdout1 => open, gtye4_common_qpll0fbclklost => open, gtye4_common_qpll0lock(0) => master_common_to_mgt_qpll0lock(i), gtye4_common_qpll0outclk(0) => master_common_to_mgt_qpll0outclk(i), gtye4_common_qpll0outrefclk(0) => master_common_to_mgt_qpll0outrefclk(i), gtye4_common_qpll0refclklost => open, gtye4_common_qpll1fbclklost => open, gtye4_common_qpll1lock => open, gtye4_common_qpll1outclk(0) => master_common_to_mgt_qpll1outclk(i), gtye4_common_qpll1outrefclk(0) => master_common_to_mgt_qpll1outrefclk(i), gtye4_common_qpll1refclklost => open, gtye4_common_qplldmonitor0 => open, gtye4_common_qplldmonitor1 => open, gtye4_common_refclkoutmonitor0 => open, gtye4_common_refclkoutmonitor1 => open, gtye4_common_rxrecclk0sel => open, gtye4_common_rxrecclk1sel => open, gtye4_common_sdm0finalout => open, gtye4_common_sdm0testdata => open, gtye4_common_sdm1finalout => open, gtye4_common_sdm1testdata => open, gtye4_common_ubdaddr => open, gtye4_common_ubden => open, gtye4_common_ubdi => open, gtye4_common_ubdwe => open, gtye4_common_ubmdmtdo => open, gtye4_common_ubrsvdout => open, gtye4_common_ubtxuart => open ); end generate; master_mgt_to_common_qpll0reset_common(i) <= master_mgt_to_common_qpll0reset(C_MASTER_PLL_RESET_CHANNELS(i)); end generate; ------------------------------------------ -- MGT channels. ------------------------------------------ generate_channels : for i in C_MASTER_NUMBER_CHANNELS - 1 downto 0 generate -- MGT user clock network. mgt_user_clock : entity work.mgt_user_clock generic map ( G_NUMBER_CHANNELS => 1 ) port map ( -- User clocks. txusrclk_o(0) => master_txusrclk(i), rxusrclk_o(0) => master_rxusrclk(i), -- User clock network. mgt_txoutclk_i(0) => master_mgt_txoutclk(i), mgt_rxoutclk_i(0) => master_mgt_rxoutclk(i) ); -- MGT. if_gth : if C_MASTER_QUAD_MGT_TYPES(i) = C_MGT_TYPE_GTH generate if_gth_5g : if G_LINK_SPEED = TCDS2_LINK_SPEED_5G generate gth_master_timing : entity work.gthe4_master_timing_5g port map ( gtwiz_reset_clk_freerun_in(0) => clk_gp_125mhz, gtwiz_reset_all_in(0) => master_mgt_reset_all(i), gtwiz_reset_tx_pll_and_datapath_in(0) => master_mgt_reset_tx_pll_and_datapath(i), gtwiz_reset_rx_pll_and_datapath_in(0) => std_logic'('0'), gtwiz_reset_tx_datapath_in(0) => master_mgt_reset_tx_datapath(i), gtwiz_reset_rx_datapath_in(0) => master_mgt_reset_rx_datapath(i), gtwiz_reset_qpll0lock_in(0) => master_common_to_mgt_qpll0lock(c_MASTER_CHANNEL_QUADS(i)), gtwiz_reset_qpll0reset_out(0) => master_mgt_to_common_qpll0reset(i), qpll0clk_in(0) => master_common_to_mgt_qpll0outclk(c_MASTER_CHANNEL_QUADS(i)), qpll0refclk_in(0) => master_common_to_mgt_qpll0outrefclk(c_MASTER_CHANNEL_QUADS(i)), qpll1clk_in(0) => master_common_to_mgt_qpll1outclk(c_MASTER_CHANNEL_QUADS(i)), qpll1refclk_in(0) => master_common_to_mgt_qpll1outrefclk(c_MASTER_CHANNEL_QUADS(i)), -- User clocking. rxusrclk_in(0) => master_rxusrclk(i), rxusrclk2_in(0) => master_rxusrclk(i), txusrclk_in(0) => master_txusrclk(i), txusrclk2_in(0) => master_txusrclk(i), rxoutclk_out(0) => master_mgt_rxoutclk(i), txoutclk_out(0) => master_mgt_txoutclk(i), -- Channel. gtwiz_userclk_tx_active_in => master_mgt_ctrl(i).gtwiz_userclk_tx_active_in, gtwiz_userclk_rx_active_in => master_mgt_ctrl(i).gtwiz_userclk_rx_active_in, gtwiz_buffbypass_rx_reset_in => master_mgt_ctrl(i).gtwiz_buffbypass_rx_reset_in, gtwiz_buffbypass_rx_start_user_in => master_mgt_ctrl(i).gtwiz_buffbypass_rx_start_user_in, gtwiz_buffbypass_rx_done_out => master_mgt_stat(i).gtwiz_buffbypass_rx_done_out, gtwiz_buffbypass_rx_error_out => master_mgt_stat(i).gtwiz_buffbypass_rx_error_out, gtwiz_reset_rx_cdr_stable_out => master_mgt_stat(i).gtwiz_reset_rx_cdr_stable_out, gtwiz_reset_tx_done_out => master_mgt_stat(i).gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out => master_mgt_stat(i).gtwiz_reset_rx_done_out, loopback_in => master_mgt_ctrl(i).loopback_in, rxdfeagcovrden_in => master_mgt_ctrl(i).rxdfeagcovrden_in, rxdfelfovrden_in => master_mgt_ctrl(i).rxdfelfovrden_in, rxdfelpmreset_in => master_mgt_ctrl(i).rxdfelpmreset_in, rxdfeutovrden_in => master_mgt_ctrl(i).rxdfeutovrden_in, rxdfevpovrden_in => master_mgt_ctrl(i).rxdfevpovrden_in, rxlpmen_in => master_mgt_ctrl(i).rxlpmen_in, rxosovrden_in => master_mgt_ctrl(i).rxosovrden_in, rxlpmgcovrden_in => master_mgt_ctrl(i).rxlpmgcovrden_in, rxlpmhfovrden_in => master_mgt_ctrl(i).rxlpmhfovrden_in, rxlpmlfklovrden_in => master_mgt_ctrl(i).rxlpmlfklovrden_in, rxlpmosovrden_in => master_mgt_ctrl(i).rxlpmosovrden_in, rxslide_in => master_mgt_ctrl(i).rxslide_in, dmonitorclk_in => master_mgt_ctrl(i).dmonitorclk_in, drpaddr_in => master_mgt_ctrl(i).drpaddr_in, drpclk_in => master_mgt_ctrl(i).drpclk_in, drpdi_in => master_mgt_ctrl(i).drpdi_in, drpen_in => master_mgt_ctrl(i).drpen_in, drpwe_in => master_mgt_ctrl(i).drpwe_in, rxpolarity_in => master_mgt_ctrl(i).rxpolarity_in, rxprbscntreset_in => master_mgt_ctrl(i).rxprbscntreset_in, rxprbssel_in => master_mgt_ctrl(i).rxprbssel_in, txpippmen_in => master_mgt_ctrl(i).txpippmen_in, txpippmovrden_in => master_mgt_ctrl(i).txpippmovrden_in, txpippmpd_in => master_mgt_ctrl(i).txpippmpd_in, txpippmsel_in => master_mgt_ctrl(i).txpippmsel_in, txpippmstepsize_in => master_mgt_ctrl(i).txpippmstepsize_in, txpolarity_in => master_mgt_ctrl(i).txpolarity_in, txprbsforceerr_in => master_mgt_ctrl(i).txprbsforceerr_in, txprbssel_in => master_mgt_ctrl(i).txprbssel_in, dmonitorout_out => master_mgt_stat(i).dmonitorout_out, drpdo_out => master_mgt_stat(i).drpdo_out, drprdy_out => master_mgt_stat(i).drprdy_out, rxprbserr_out => master_mgt_stat(i).rxprbserr_out, rxprbslocked_out => master_mgt_stat(i).rxprbslocked_out, txbufstatus_out => master_mgt_stat(i).txbufstatus_out, txpmaresetdone_out => master_mgt_stat(i).txpmaresetdone_out, rxpmaresetdone_out => master_mgt_stat(i).rxpmaresetdone_out, gtpowergood_out => master_mgt_stat(i).gtpowergood_out, gtwiz_userdata_tx_in => master_mgt_ctrl(i).txdata_in(15 downto 0), gtwiz_userdata_rx_out => master_mgt_stat(i).rxdata_out(15 downto 0), gthtxp_out(0) => master_tx_p(i), gthtxn_out(0) => master_tx_n(i), gthrxp_in(0) => master_rx_p(i), gthrxn_in(0) => master_rx_n(i) ); end generate; if_gth_10g : if G_LINK_SPEED = TCDS2_LINK_SPEED_10G generate gth_master_timing : entity work.gthe4_master_timing port map ( gtwiz_reset_clk_freerun_in(0) => clk_gp_125mhz, gtwiz_reset_all_in(0) => master_mgt_reset_all(i), gtwiz_reset_tx_pll_and_datapath_in(0) => master_mgt_reset_tx_pll_and_datapath(i), gtwiz_reset_rx_pll_and_datapath_in(0) => std_logic'('0'), gtwiz_reset_tx_datapath_in(0) => master_mgt_reset_tx_datapath(i), gtwiz_reset_rx_datapath_in(0) => master_mgt_reset_rx_datapath(i), gtwiz_reset_qpll0lock_in(0) => master_common_to_mgt_qpll0lock(c_MASTER_CHANNEL_QUADS(i)), gtwiz_reset_qpll0reset_out(0) => master_mgt_to_common_qpll0reset(i), qpll0clk_in(0) => master_common_to_mgt_qpll0outclk(c_MASTER_CHANNEL_QUADS(i)), qpll0refclk_in(0) => master_common_to_mgt_qpll0outrefclk(c_MASTER_CHANNEL_QUADS(i)), qpll1clk_in(0) => master_common_to_mgt_qpll1outclk(c_MASTER_CHANNEL_QUADS(i)), qpll1refclk_in(0) => master_common_to_mgt_qpll1outrefclk(c_MASTER_CHANNEL_QUADS(i)), -- User clocking. rxusrclk_in(0) => master_rxusrclk(i), rxusrclk2_in(0) => master_rxusrclk(i), txusrclk_in(0) => master_txusrclk(i), txusrclk2_in(0) => master_txusrclk(i), rxoutclk_out(0) => master_mgt_rxoutclk(i), txoutclk_out(0) => master_mgt_txoutclk(i), -- Channel. gtwiz_userclk_tx_active_in => master_mgt_ctrl(i).gtwiz_userclk_tx_active_in, gtwiz_userclk_rx_active_in => master_mgt_ctrl(i).gtwiz_userclk_rx_active_in, gtwiz_buffbypass_rx_reset_in => master_mgt_ctrl(i).gtwiz_buffbypass_rx_reset_in, gtwiz_buffbypass_rx_start_user_in => master_mgt_ctrl(i).gtwiz_buffbypass_rx_start_user_in, gtwiz_buffbypass_rx_done_out => master_mgt_stat(i).gtwiz_buffbypass_rx_done_out, gtwiz_buffbypass_rx_error_out => master_mgt_stat(i).gtwiz_buffbypass_rx_error_out, gtwiz_reset_rx_cdr_stable_out => master_mgt_stat(i).gtwiz_reset_rx_cdr_stable_out, gtwiz_reset_tx_done_out => master_mgt_stat(i).gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out => master_mgt_stat(i).gtwiz_reset_rx_done_out, loopback_in => master_mgt_ctrl(i).loopback_in, rxdfeagcovrden_in => master_mgt_ctrl(i).rxdfeagcovrden_in, rxdfelfovrden_in => master_mgt_ctrl(i).rxdfelfovrden_in, rxdfelpmreset_in => master_mgt_ctrl(i).rxdfelpmreset_in, rxdfeutovrden_in => master_mgt_ctrl(i).rxdfeutovrden_in, rxdfevpovrden_in => master_mgt_ctrl(i).rxdfevpovrden_in, rxlpmen_in => master_mgt_ctrl(i).rxlpmen_in, rxosovrden_in => master_mgt_ctrl(i).rxosovrden_in, rxlpmgcovrden_in => master_mgt_ctrl(i).rxlpmgcovrden_in, rxlpmhfovrden_in => master_mgt_ctrl(i).rxlpmhfovrden_in, rxlpmlfklovrden_in => master_mgt_ctrl(i).rxlpmlfklovrden_in, rxlpmosovrden_in => master_mgt_ctrl(i).rxlpmosovrden_in, rxslide_in => master_mgt_ctrl(i).rxslide_in, dmonitorclk_in => master_mgt_ctrl(i).dmonitorclk_in, drpaddr_in => master_mgt_ctrl(i).drpaddr_in, drpclk_in => master_mgt_ctrl(i).drpclk_in, drpdi_in => master_mgt_ctrl(i).drpdi_in, drpen_in => master_mgt_ctrl(i).drpen_in, drpwe_in => master_mgt_ctrl(i).drpwe_in, rxpolarity_in => master_mgt_ctrl(i).rxpolarity_in, rxprbscntreset_in => master_mgt_ctrl(i).rxprbscntreset_in, rxprbssel_in => master_mgt_ctrl(i).rxprbssel_in, txpippmen_in => master_mgt_ctrl(i).txpippmen_in, txpippmovrden_in => master_mgt_ctrl(i).txpippmovrden_in, txpippmpd_in => master_mgt_ctrl(i).txpippmpd_in, txpippmsel_in => master_mgt_ctrl(i).txpippmsel_in, txpippmstepsize_in => master_mgt_ctrl(i).txpippmstepsize_in, txpolarity_in => master_mgt_ctrl(i).txpolarity_in, txprbsforceerr_in => master_mgt_ctrl(i).txprbsforceerr_in, txprbssel_in => master_mgt_ctrl(i).txprbssel_in, dmonitorout_out => master_mgt_stat(i).dmonitorout_out, drpdo_out => master_mgt_stat(i).drpdo_out, drprdy_out => master_mgt_stat(i).drprdy_out, rxprbserr_out => master_mgt_stat(i).rxprbserr_out, rxprbslocked_out => master_mgt_stat(i).rxprbslocked_out, txbufstatus_out => master_mgt_stat(i).txbufstatus_out, txpmaresetdone_out => master_mgt_stat(i).txpmaresetdone_out, rxpmaresetdone_out => master_mgt_stat(i).rxpmaresetdone_out, gtpowergood_out => master_mgt_stat(i).gtpowergood_out, gtwiz_userdata_tx_in => master_mgt_ctrl(i).txdata_in, gtwiz_userdata_rx_out => master_mgt_stat(i).rxdata_out, gthtxp_out(0) => master_tx_p(i), gthtxn_out(0) => master_tx_n(i), gthrxp_in(0) => master_rx_p(i), gthrxn_in(0) => master_rx_n(i) ); end generate; end generate; if_gty : if C_MASTER_QUAD_MGT_TYPES(i) = C_MGT_TYPE_GTY generate if_gty_5g : if G_LINK_SPEED = TCDS2_LINK_SPEED_5G generate gty_master_timing : entity work.gtye4_master_timing_5g port map ( gtwiz_reset_clk_freerun_in(0) => clk_gp_125mhz, gtwiz_reset_all_in(0) => master_mgt_reset_all(i), gtwiz_reset_tx_pll_and_datapath_in(0) => master_mgt_reset_tx_pll_and_datapath(i), gtwiz_reset_rx_pll_and_datapath_in(0) => std_logic'('0'), gtwiz_reset_tx_datapath_in(0) => master_mgt_reset_tx_datapath(i), gtwiz_reset_rx_datapath_in(0) => master_mgt_reset_rx_datapath(i), gtwiz_reset_qpll0lock_in(0) => master_common_to_mgt_qpll0lock(c_MASTER_CHANNEL_QUADS(i)), gtwiz_reset_qpll0reset_out(0) => master_mgt_to_common_qpll0reset(i), qpll0clk_in(0) => master_common_to_mgt_qpll0outclk(c_MASTER_CHANNEL_QUADS(i)), qpll0refclk_in(0) => master_common_to_mgt_qpll0outrefclk(c_MASTER_CHANNEL_QUADS(i)), qpll1clk_in(0) => master_common_to_mgt_qpll1outclk(c_MASTER_CHANNEL_QUADS(i)), qpll1refclk_in(0) => master_common_to_mgt_qpll1outrefclk(c_MASTER_CHANNEL_QUADS(i)), -- User clocking. rxusrclk_in(0) => master_rxusrclk(i), rxusrclk2_in(0) => master_rxusrclk(i), txusrclk_in(0) => master_txusrclk(i), txusrclk2_in(0) => master_txusrclk(i), rxoutclk_out(0) => master_mgt_rxoutclk(i), txoutclk_out(0) => master_mgt_txoutclk(i), -- Channel. gtwiz_userclk_tx_active_in => master_mgt_ctrl(i).gtwiz_userclk_tx_active_in, gtwiz_userclk_rx_active_in => master_mgt_ctrl(i).gtwiz_userclk_rx_active_in, gtwiz_buffbypass_rx_reset_in => master_mgt_ctrl(i).gtwiz_buffbypass_rx_reset_in, gtwiz_buffbypass_rx_start_user_in => master_mgt_ctrl(i).gtwiz_buffbypass_rx_start_user_in, gtwiz_buffbypass_rx_done_out => master_mgt_stat(i).gtwiz_buffbypass_rx_done_out, gtwiz_buffbypass_rx_error_out => master_mgt_stat(i).gtwiz_buffbypass_rx_error_out, gtwiz_reset_rx_cdr_stable_out => master_mgt_stat(i).gtwiz_reset_rx_cdr_stable_out, gtwiz_reset_tx_done_out => master_mgt_stat(i).gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out => master_mgt_stat(i).gtwiz_reset_rx_done_out, loopback_in => master_mgt_ctrl(i).loopback_in, rxdfeagcovrden_in => master_mgt_ctrl(i).rxdfeagcovrden_in, rxdfelfovrden_in => master_mgt_ctrl(i).rxdfelfovrden_in, rxdfelpmreset_in => master_mgt_ctrl(i).rxdfelpmreset_in, rxdfeutovrden_in => master_mgt_ctrl(i).rxdfeutovrden_in, rxdfevpovrden_in => master_mgt_ctrl(i).rxdfevpovrden_in, rxlpmen_in => master_mgt_ctrl(i).rxlpmen_in, rxosovrden_in => master_mgt_ctrl(i).rxosovrden_in, rxlpmgcovrden_in => master_mgt_ctrl(i).rxlpmgcovrden_in, rxlpmhfovrden_in => master_mgt_ctrl(i).rxlpmhfovrden_in, rxlpmlfklovrden_in => master_mgt_ctrl(i).rxlpmlfklovrden_in, rxlpmosovrden_in => master_mgt_ctrl(i).rxlpmosovrden_in, rxslide_in => master_mgt_ctrl(i).rxslide_in, dmonitorclk_in => master_mgt_ctrl(i).dmonitorclk_in, drpaddr_in => master_mgt_ctrl(i).drpaddr_in, drpclk_in => master_mgt_ctrl(i).drpclk_in, drpdi_in => master_mgt_ctrl(i).drpdi_in, drpen_in => master_mgt_ctrl(i).drpen_in, drpwe_in => master_mgt_ctrl(i).drpwe_in, rxpolarity_in => master_mgt_ctrl(i).rxpolarity_in, rxprbscntreset_in => master_mgt_ctrl(i).rxprbscntreset_in, rxprbssel_in => master_mgt_ctrl(i).rxprbssel_in, txpippmen_in => master_mgt_ctrl(i).txpippmen_in, txpippmovrden_in => master_mgt_ctrl(i).txpippmovrden_in, txpippmpd_in => master_mgt_ctrl(i).txpippmpd_in, txpippmsel_in => master_mgt_ctrl(i).txpippmsel_in, txpippmstepsize_in => master_mgt_ctrl(i).txpippmstepsize_in, txpolarity_in => master_mgt_ctrl(i).txpolarity_in, txprbsforceerr_in => master_mgt_ctrl(i).txprbsforceerr_in, txprbssel_in => master_mgt_ctrl(i).txprbssel_in, dmonitorout_out => master_mgt_stat(i).dmonitorout_out, drpdo_out => master_mgt_stat(i).drpdo_out, drprdy_out => master_mgt_stat(i).drprdy_out, rxprbserr_out => master_mgt_stat(i).rxprbserr_out, rxprbslocked_out => master_mgt_stat(i).rxprbslocked_out, txbufstatus_out => master_mgt_stat(i).txbufstatus_out, txpmaresetdone_out => master_mgt_stat(i).txpmaresetdone_out, rxpmaresetdone_out => master_mgt_stat(i).rxpmaresetdone_out, gtpowergood_out => master_mgt_stat(i).gtpowergood_out, gtwiz_userdata_tx_in => master_mgt_ctrl(i).txdata_in(15 downto 0), gtwiz_userdata_rx_out => master_mgt_stat(i).rxdata_out(15 downto 0), gtytxp_out(0) => master_tx_p(i), gtytxn_out(0) => master_tx_n(i), gtyrxp_in(0) => master_rx_p(i), gtyrxn_in(0) => master_rx_n(i) ); end generate; if_gty_10g : if G_LINK_SPEED = TCDS2_LINK_SPEED_10G generate gty_master_timing : entity work.gtye4_master_timing port map ( gtwiz_reset_clk_freerun_in(0) => clk_gp_125mhz, gtwiz_reset_all_in(0) => master_mgt_reset_all(i), gtwiz_reset_tx_pll_and_datapath_in(0) => master_mgt_reset_tx_pll_and_datapath(i), gtwiz_reset_rx_pll_and_datapath_in(0) => std_logic'('0'), gtwiz_reset_tx_datapath_in(0) => master_mgt_reset_tx_datapath(i), gtwiz_reset_rx_datapath_in(0) => master_mgt_reset_rx_datapath(i), gtwiz_reset_qpll0lock_in(0) => master_common_to_mgt_qpll0lock(c_MASTER_CHANNEL_QUADS(i)), gtwiz_reset_qpll0reset_out(0) => master_mgt_to_common_qpll0reset(i), qpll0clk_in(0) => master_common_to_mgt_qpll0outclk(c_MASTER_CHANNEL_QUADS(i)), qpll0refclk_in(0) => master_common_to_mgt_qpll0outrefclk(c_MASTER_CHANNEL_QUADS(i)), qpll1clk_in(0) => master_common_to_mgt_qpll1outclk(c_MASTER_CHANNEL_QUADS(i)), qpll1refclk_in(0) => master_common_to_mgt_qpll1outrefclk(c_MASTER_CHANNEL_QUADS(i)), -- User clocking. rxusrclk_in(0) => master_rxusrclk(i), rxusrclk2_in(0) => master_rxusrclk(i), txusrclk_in(0) => master_txusrclk(i), txusrclk2_in(0) => master_txusrclk(i), rxoutclk_out(0) => master_mgt_rxoutclk(i), txoutclk_out(0) => master_mgt_txoutclk(i), -- Channel. gtwiz_userclk_tx_active_in => master_mgt_ctrl(i).gtwiz_userclk_tx_active_in, gtwiz_userclk_rx_active_in => master_mgt_ctrl(i).gtwiz_userclk_rx_active_in, gtwiz_buffbypass_rx_reset_in => master_mgt_ctrl(i).gtwiz_buffbypass_rx_reset_in, gtwiz_buffbypass_rx_start_user_in => master_mgt_ctrl(i).gtwiz_buffbypass_rx_start_user_in, gtwiz_buffbypass_rx_done_out => master_mgt_stat(i).gtwiz_buffbypass_rx_done_out, gtwiz_buffbypass_rx_error_out => master_mgt_stat(i).gtwiz_buffbypass_rx_error_out, gtwiz_reset_rx_cdr_stable_out => master_mgt_stat(i).gtwiz_reset_rx_cdr_stable_out, gtwiz_reset_tx_done_out => master_mgt_stat(i).gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out => master_mgt_stat(i).gtwiz_reset_rx_done_out, loopback_in => master_mgt_ctrl(i).loopback_in, rxdfeagcovrden_in => master_mgt_ctrl(i).rxdfeagcovrden_in, rxdfelfovrden_in => master_mgt_ctrl(i).rxdfelfovrden_in, rxdfelpmreset_in => master_mgt_ctrl(i).rxdfelpmreset_in, rxdfeutovrden_in => master_mgt_ctrl(i).rxdfeutovrden_in, rxdfevpovrden_in => master_mgt_ctrl(i).rxdfevpovrden_in, rxlpmen_in => master_mgt_ctrl(i).rxlpmen_in, rxosovrden_in => master_mgt_ctrl(i).rxosovrden_in, rxlpmgcovrden_in => master_mgt_ctrl(i).rxlpmgcovrden_in, rxlpmhfovrden_in => master_mgt_ctrl(i).rxlpmhfovrden_in, rxlpmlfklovrden_in => master_mgt_ctrl(i).rxlpmlfklovrden_in, rxlpmosovrden_in => master_mgt_ctrl(i).rxlpmosovrden_in, rxslide_in => master_mgt_ctrl(i).rxslide_in, dmonitorclk_in => master_mgt_ctrl(i).dmonitorclk_in, drpaddr_in => master_mgt_ctrl(i).drpaddr_in, drpclk_in => master_mgt_ctrl(i).drpclk_in, drpdi_in => master_mgt_ctrl(i).drpdi_in, drpen_in => master_mgt_ctrl(i).drpen_in, drpwe_in => master_mgt_ctrl(i).drpwe_in, rxpolarity_in => master_mgt_ctrl(i).rxpolarity_in, rxprbscntreset_in => master_mgt_ctrl(i).rxprbscntreset_in, rxprbssel_in => master_mgt_ctrl(i).rxprbssel_in, txpippmen_in => master_mgt_ctrl(i).txpippmen_in, txpippmovrden_in => master_mgt_ctrl(i).txpippmovrden_in, txpippmpd_in => master_mgt_ctrl(i).txpippmpd_in, txpippmsel_in => master_mgt_ctrl(i).txpippmsel_in, txpippmstepsize_in => master_mgt_ctrl(i).txpippmstepsize_in, txpolarity_in => master_mgt_ctrl(i).txpolarity_in, txprbsforceerr_in => master_mgt_ctrl(i).txprbsforceerr_in, txprbssel_in => master_mgt_ctrl(i).txprbssel_in, dmonitorout_out => master_mgt_stat(i).dmonitorout_out, drpdo_out => master_mgt_stat(i).drpdo_out, drprdy_out => master_mgt_stat(i).drprdy_out, rxprbserr_out => master_mgt_stat(i).rxprbserr_out, rxprbslocked_out => master_mgt_stat(i).rxprbslocked_out, txbufstatus_out => master_mgt_stat(i).txbufstatus_out, txpmaresetdone_out => master_mgt_stat(i).txpmaresetdone_out, rxpmaresetdone_out => master_mgt_stat(i).rxpmaresetdone_out, gtpowergood_out => master_mgt_stat(i).gtpowergood_out, gtwiz_userdata_tx_in => master_mgt_ctrl(i).txdata_in, gtwiz_userdata_rx_out => master_mgt_stat(i).rxdata_out, gtytxp_out(0) => master_tx_p(i), gtytxn_out(0) => master_tx_n(i), gtyrxp_in(0) => master_rx_p(i), gtyrxn_in(0) => master_rx_n(i) ); end generate; end generate; master_mgt_stat(i).txplllock_out(0) <= master_common_to_mgt_qpll0lock(C_MASTER_CHANNEL_QUADS(i)); master_mgt_stat(i).rxplllock_out(0) <= master_common_to_mgt_qpll0lock(C_MASTER_CHANNEL_QUADS(i)); ------------------------------------------ -- TCLink cores. ------------------------------------------ tclink : entity work.tclink_lpgbt10G generic map ( G_MASTER_NSLAVE => True, G_MASTER_TCLINK_TESTER_ENABLE => True, G_USER_DATA_WIDTH => C_TCDS2_INTERFACE_FRAME_WIDTH, G_DATA_RATE => C_TCDS2_INTERFACE_DATA_RATE ) port map ( -- System clock/resets. clk_sys_i => clk_gp_125mhz, reset_all_i => master_mgt_reset_tx_datapath(i), -- Core control/status. (Synchronous to clk_sys_i.) core_ctrl_i => master_core_ctrl(i), core_stat_o => master_core_stat(i), -- TCLink. master_tclink_clk_offset_i => master_clk_offset, master_tclink_ctrl_i => master_tclink_ctrl(i), master_tclink_stat_o => master_tclink_stat(i), -- Recovered clock. slave_clk40_oddr_o => open, -- User data. tx_clk40_i => clk_40_tx, tx_data_i => ttc2_frames(i), tx_clk40_stable_i => '1', rx_clk40_i => clk_40_rx_tmp(i), rx_data_o => tts2_frames(i), rx_clk40_stable_i => '1', -- MGT interface. mgt_txclk_i => master_txusrclk(i), mgt_rxclk_i => master_rxusrclk(i), mgt_ctrl_o => master_mgt_ctrl(i), mgt_stat_i => master_mgt_stat(i) ); ------------------------------------------------------------ -- BUG BUG BUG -- Signals below - encouraged to be set to static value for a final implementation. --master_tclink_ctrl(i).tclink_metastability_deglitch <= x"0052" ; --master_tclink_ctrl(i).tclink_phase_detector_navg <= x"040" ; --master_tclink_ctrl(i).tclink_modulo_carrier_period <= x"00007ff48348"; --master_tclink_ctrl(i).tclink_master_rx_ui_period <= x"000003ffa41a"; --master_tclink_ctrl(i).tclink_Aie <= x"0" ; --master_tclink_ctrl(i).tclink_Aie_enable <= '1' ; --master_tclink_ctrl(i).tclink_Ape <= x"e" ; --master_tclink_ctrl(i).tclink_sigma_delta_clk_div <= x"0197" ; --master_tclink_ctrl(i).tclink_enable_mirror <= '1' ; --master_tclink_ctrl(i).tclink_Adco <= x"0000000ffe90"; -- BUG BUG BUG end -- Each channel has a dedicated frame unlock counter. channel_rx_unlock_cnt : entity work.unlock_counter generic map ( G_WIDTH => channel_unlock_count(0)'length ) port map ( clk => clk_gp_125mhz, rst => master_mgt_reset_tx_datapath(i), locked => master_core_stat(i).rx_frame_locked, unlock_count => channel_unlock_count(i) ); -- BUG BUG BUG -- The following needs work. -- The 40 MHz RX clock is the one recovered from the incoming serial -- stream. bufgce_clk_40_rx : bufgce_div generic map ( -- Divide from 320 MHz to 40 MHz. BUFGCE_DIVIDE => 8 ) port map ( i => master_rxusrclk(i), o => clk_40_rx_tmp(i), ce => master_core_stat(i).rx_frame_locked, clr => not master_core_stat(i).rx_frame_locked ); -- BUG BUG BUG end end generate; clk_40_rx <= clk_40_rx_tmp; ------------------------------------------ -- Frequency counters to keep an eye on the recovered RX clock -- signals. -- NOTE: If all is well on the back-end side, that side uses the 320 -- MHz backplane clock as MGT reference clock. In that case the -- back-end TX and RX clocks are exactly the same, and exactly the -- same as the DTH TX clock. If the back-end MGT reference clock -- unlocks from the backplane clock (i.e., from the DTH 320 MHz DTH -- reference clock), the back-end TX clock will follow the back-end -- reference clock, and on the DTH side one will measure a recovered -- RX clock frequency that differs slightly from the TX clock -- frequency. ------------------------------------------ freq_divs : entity work.freq_ctr_div generic map ( N_CLK => clkdiv_i'length ) port map ( clk => clk_40_rx_tmp, clkdiv => clkdiv_i ); freq_cntrs : entity work.ipbus_freq_ctr generic map ( N_CLK => clkdiv_i'length ) port map ( clk => clk_ipb, rst => rst_ipb, ipb_in => ipbw(N_SLV_FREQUENCY_COUNTERS), ipb_out => ipbr(N_SLV_FREQUENCY_COUNTERS), clkdiv => clkdiv_i ); ------------------------------------------ -- Control and status for all channels. ------------------------------------------ generate_csr_assignment : for i in C_MASTER_NUMBER_CHANNELS - 1 downto 0 generate csr_channel : entity work.ipbus_ctrlreg_v generic map ( N_CTRL => 1, N_STAT => 3 ) port map ( clk => clk_ipb, reset => rst_ipb, ipbus_in => ipbw(N_SLV_SLOT_I_CSR(i)), ipbus_out => ipbr(N_SLV_SLOT_I_CSR(i)), q => ctrl_channels(i downto i), d => stat_channels(3 * i + 2 downto 3 * i) ); -- MGT resets. master_mgt_reset_all(i) <= ctrl_channels(i)(0); master_mgt_reset_tx_pll_and_datapath(i) <= ctrl_channels(i)(1); master_mgt_reset_rx_datapath(i) <= ctrl_channels(i)(2); -- Link speed indicator. stat_channels(3 * i)(0) <= '1' when is_link_speed_10g else '0'; -- TCLink heterodyne MMCM lock flag. stat_channels(3 * i)(1) <= master_clk_offset_locked; -- 'Power good' flag for the MGT quad. stat_channels(3 * i + 1)(0) <= master_core_stat(i).mgt_powergood; -- PLL lock flags for the MGT quad. stat_channels(3 * i + 1)(1) <= master_core_stat(i).mgt_txpll_lock; stat_channels(3 * i + 1)(2) <= master_core_stat(i).mgt_txpll_lock; -- Reset status flags for the MGT quad. stat_channels(3 * i + 1)(3) <= master_core_stat(i).mgt_reset_tx_done; stat_channels(3 * i + 1)(4) <= master_core_stat(i).mgt_reset_rx_done; -- TCLink status. stat_channels(3 * i + 1)(5) <= master_core_stat(i).mgt_tx_ready; stat_channels(3 * i + 1)(6) <= master_core_stat(i).mgt_rx_ready; stat_channels(3 * i + 1)(7) <= master_core_stat(i).rx_frame_locked; stat_channels(3 * i + 2)(channel_unlock_count(i)'range) <= channel_unlock_count(i); end generate; is_link_speed_10g <= true when G_LINK_SPEED = TCDS2_LINK_SPEED_10G else false; ------------------------------------------ -- Spy access to what comes and goes on all channels. ------------------------------------------ generate_spies : for i in C_MASTER_NUMBER_CHANNELS - 1 downto 0 generate spy_frame_tx : entity work.tcds2_frame_spy port map ( clk_ipb => clk_ipb, rst_ipb => rst_ipb, ipb_in => ipbw(N_SLV_SLOT_I_SPY_FRAME_TX(i)), ipb_out => ipbr(N_SLV_SLOT_I_SPY_FRAME_TX(i)), frame_i => ttc2_frames(i) ); spy_frame_rx : entity work.tcds2_frame_spy port map ( clk_ipb => clk_ipb, rst_ipb => rst_ipb, ipb_in => ipbw(N_SLV_SLOT_I_SPY_FRAME_RX(i)), ipb_out => ipbr(N_SLV_SLOT_I_SPY_FRAME_RX(i)), frame_i => tts2_frames(i) ); end generate; end arch; --======================================================================