--======================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.ipbus.all;
use work.ipbus_reg_types.all;

use work.loopback_tcds_pkg.all;

--==================================================

entity loopback_tcds_frontpanel_b is
  port (
    -- IPBus interface.
    clk_ipb : in std_logic;
    rst_ipb : in std_logic;
    ipb_in : in ipb_wbus;
    ipb_out : out ipb_rbus;

    -- The 100 MHz general purpose clock.
    clk_gp_100mhz : in std_logic;

    -- The 320 MHz MGT reference clock.
    mgt234_refclk0_320mhz : in std_logic;

    -- The MGT connections.
    tcds_frontpanel_b_tx_p : out std_logic;
    tcds_frontpanel_b_tx_n : out std_logic;
    tcds_frontpanel_b_rx_p : in std_logic;
    tcds_frontpanel_b_rx_n : in std_logic;

    -- The recovered RX clock.
    rxoutclk : out std_logic
  );
end loopback_tcds_frontpanel_b;

--==================================================

architecture arch of loopback_tcds_frontpanel_b is
begin

  loopback_tcds_frontpanel_b : entity work.loopback_tcds
    generic map (
      loopback_type => LOOPBACK_TYPE_FRONTPANEL_B
    )
    port map (
      clk_ipb => clk_ipb,
      rst_ipb => rst_ipb,
      ipb_in  => ipb_in,
      ipb_out => ipb_out,

      clk_gp_100mhz => clk_gp_100mhz,

      mgt_refclk0_320mhz => mgt234_refclk0_320mhz,

      tcds_tx_p => tcds_frontpanel_b_tx_p,
      tcds_tx_n => tcds_frontpanel_b_tx_n,
      tcds_rx_p => tcds_frontpanel_b_rx_p,
      tcds_rx_n => tcds_frontpanel_b_rx_n,

      rxoutclk => rxoutclk
    );

end arch;

--======================================================================