--======================================================================
-- This code expects the following constants to be defined:
--   - constant C_SYSTEM_ID        : tcds2_id;
--   - constant C_BOARD_ID         : tcds2_id;
--   - constant C_FUNCTION_ID      : tcds2_id;
--   - constant C_FW_VERSION_MAJOR : tcds2_version;
--   - constant C_FW_VERSION_MINOR : tcds2_version;
--   - constant C_FW_VERSION_PATCH : tcds2_version;
-- The corresponding types are defined in board_and_fw_id_pkg.vhd.
--======================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

use work.ipbus.all;

use work.constants_functions_and_versions.all;
use work.board_and_fw_id_pkg.all;

--======================================================================

entity board_and_fw_id is
  port (
    ipb_in  : in ipb_wbus;
    ipb_out : out ipb_rbus
  );
end entity board_and_fw_id;

--==========

architecture rtl of board_and_fw_id is

  constant C_SYSTEM_ID_HI : std_logic_vector(31 downto 0) :=
      id_to_std_logic_vector(C_SYSTEM_ID)(63 downto 32);
  constant C_SYSTEM_ID_LO : std_logic_vector(31 downto 0) :=
      id_to_std_logic_vector(C_SYSTEM_ID)(31 downto 0);

  constant C_BOARD_ID_HI : std_logic_vector(31 downto 0) :=
      id_to_std_logic_vector(C_BOARD_ID)(63 downto 32);
  constant C_BOARD_ID_LO : std_logic_vector(31 downto 0) :=
      id_to_std_logic_vector(C_BOARD_ID)(31 downto 0);

  constant C_FUNCTION_ID_HI : std_logic_vector(31 downto 0) :=
      id_to_std_logic_vector(C_FUNCTION_ID)(63 downto 32);
  constant C_FUNCTION_ID_LO : std_logic_vector(31 downto 0) :=
      id_to_std_logic_vector(C_FUNCTION_ID)(31 downto 0);

  constant C_FW_VERSION : std_logic_vector(31 downto 0) :=
    X"00"
    & std_logic_vector(to_unsigned(C_FW_VERSION_MAJOR, 8))
    & std_logic_vector(to_unsigned(C_FW_VERSION_MINOR, 8))
    & std_logic_vector(to_unsigned(C_FW_VERSION_PATCH, 8));

  signal build_timestamp : std_logic_vector(31 downto 0);

begin

  ipb_out.ipb_ack <= ipb_in.ipb_strobe;
  ipb_out.ipb_err <= ipb_in.ipb_write when ipb_in.ipb_strobe = '1' else '0';

  -- Special Xilinx register to hold an auto-updated build timestamp.
  build_timestamp_reg : usr_accesse2
    port map (
      cfgclk    => open,
      data      => build_timestamp,
      datavalid => open
    );

  -- System, board, and function identifiers, and firmware version and
  -- build timestamp.
  -- NOTE: These constants are expected to be defined in a constants
  -- file in the main project area.
  with ipb_in.ipb_addr(3 downto 0) select ipb_out.ipb_rdata <=
    -- System identifier, e.g. 'TCDS2'.
    C_SYSTEM_ID_LO when "000",
    C_SYSTEM_ID_HI when "001",

    -- Board identifier, e.g 'DTH_P1V1'.
    C_BOARD_ID_LO when "010",
    C_BOARD_ID_HI when "011",

    -- Function identifier, e.g. 'MSTR_EMU'.
    C_FUNCTION_ID_LO when "100",
    C_FUNCTION_ID_HI when "101",

    -- Firmware version.
    C_FW_VERSION when "110",

    -- Build timestamp.
    build_timestamp when "111",

    -- Shouldn't need the next line. It helps future-proof against
    -- editing goofs though.
    X"00000000" when others;

end rtl;

--======================================================================