######################################################################
## DTH P1V1 pin-connections XDC.
######################################################################

######################################################################
# General purpose clocks, from the general purpose clokc generator
# (IC51).
######################################################################

# NOTE: Output 0 delivers 320 MHz to clock fan-out IC80.

# Output 1: 100 MHz.
set_property PACKAGE_PIN M18 [get_ports clk_gp_100mhz_p]
set_property PACKAGE_PIN L18 [get_ports clk_gp_100mhz_n]
set_property IOSTANDARD LVDS_25 [get_ports clk_gp_100mhz_*]

# Output 2: 125 MHz.
set_property PACKAGE_PIN AR30 [get_ports clk_gp_125mhz_p]
set_property PACKAGE_PIN AR31 [get_ports clk_gp_125mhz_n]
set_property IOSTANDARD LVDS [get_ports clk_gp_125mhz_*]

# Output 3: 156.25 MHz.
set_property PACKAGE_PIN AU21 [get_ports clk_gp_156_25mhz_p]
set_property PACKAGE_PIN AV20 [get_ports clk_gp_156_25mhz_n]
set_property IOSTANDARD LVDS [get_ports clk_gp_156_25mhz_*]

######################################################################
# Control lines for the SiLabs clock generators/cleaners.
######################################################################

# General purpose clock generator (IC51) reset and control lines.
set_property PACKAGE_PIN BA30 [get_ports clkgen_gp_reset_b]
set_property PACKAGE_PIN BA31 [get_ports clkgen_gp_intr_b]
set_property PACKAGE_PIN AW30 [get_ports clkgen_gp_lol_b]
set_property PACKAGE_PIN BB31 [get_ports clkgen_gp_los_b]
set_property IOSTANDARD LVCMOS18 [get_ports clkgen_gp_*]

# Master clock generator (IC50) reset and control lines.
set_property PACKAGE_PIN BB28 [get_ports clkgen_master_reset_b]
set_property PACKAGE_PIN BB29 [get_ports {clkgen_master_in_sel[0]}]
set_property PACKAGE_PIN BA29 [get_ports {clkgen_master_in_sel[1]}]
# set_property PACKAGE_PIN AY28 [get_ports clkgen_master_finc_n]
# set_property PACKAGE_PIN BA28 [get_ports clkgen_master_fdec_n]
set_property PACKAGE_PIN AY30 [get_ports clkgen_master_intr_b]
set_property PACKAGE_PIN AW22 [get_ports clkgen_master_lol_b]
set_property IOSTANDARD LVCMOS18 [get_ports clkgen_master_*]

# Secondary clock generator (IC40) reset and control lines.
set_property PACKAGE_PIN AP32 [get_ports clkgen_secondary_reset_b]
set_property PACKAGE_PIN AK22 [get_ports {clkgen_secondary_in_sel[0]}]
set_property PACKAGE_PIN AK20 [get_ports {clkgen_secondary_in_sel[1]}]
# set_property PACKAGE_PIN AJ22 [get_ports clkgen_secondary_finc_n]
# set_property PACKAGE_PIN AN21 [get_ports clkgen_secondary_fdec_n]
set_property PACKAGE_PIN AL19 [get_ports clkgen_secondary_intr_b]
set_property PACKAGE_PIN AJ19 [get_ports clkgen_secondary_lol_b]
set_property IOSTANDARD LVCMOS18 [get_ports clkgen_secondary_*]

# Clock generator for the 'lower half' of the backplane (IC55) reset
# and control lines.
set_property PACKAGE_PIN AW20 [get_ports clkgen_backplane_lo_reset_b]
set_property PACKAGE_PIN AR22 [get_ports {clkgen_backplane_lo_in_sel[0]}]
set_property PACKAGE_PIN BA21 [get_ports {clkgen_backplane_lo_in_sel[1]}]
#set_property PACKAGE_PIN BB22 [get_ports clkgen_backplane_lo_finc_n]
#set_property PACKAGE_PIN AP22 [get_ports clkgen_backplane_lo_fdec_n]
set_property PACKAGE_PIN BA20 [get_ports clkgen_backplane_lo_intr_b]
set_property PACKAGE_PIN AT21 [get_ports clkgen_backplane_lo_lol_b]
set_property IOSTANDARD LVCMOS18 [get_ports clkgen_backplane_lo_*]

# Clock generator for the 'upper half' of the backplane (IC53) reset
# and control lines.
set_property PACKAGE_PIN AT29 [get_ports clkgen_backplane_hi_reset_b]
set_property PACKAGE_PIN AT31 [get_ports {clkgen_backplane_hi_in_sel[0]}]
set_property PACKAGE_PIN AP28 [get_ports {clkgen_backplane_hi_in_sel[1]}]
# set_property PACKAGE_PIN AU31 [get_ports clkgen_backplane_hi_finc_n]
# set_property PACKAGE_PIN AW28 [get_ports clkgen_backplane_hi_fdec_n]
set_property PACKAGE_PIN AU28 [get_ports clkgen_backplane_hi_intr_b]
set_property PACKAGE_PIN AY31 [get_ports clkgen_backplane_hi_lol_b]
set_property IOSTANDARD LVCMOS18 [get_ports clkgen_backplane_hi_*]

# Clock generator for MGT reference clocks (IC41) reset and control
# lines.
set_property PACKAGE_PIN BB18 [get_ports clkgen_mgt_refs_reset_b]
set_property PACKAGE_PIN AM22 [get_ports {clkgen_mgt_refs_in_sel[0]}]
set_property PACKAGE_PIN AT18 [get_ports {clkgen_mgt_refs_in_sel[1]}]
# set_property PACKAGE_PIN AP19 [get_ports clkgen_mgt_refs_finc_n]
# set_property PACKAGE_PIN AV19 [get_ports clkgen_mgt_refs_fdec_n]
set_property PACKAGE_PIN AU18 [get_ports clkgen_mgt_refs_intr_b]
set_property PACKAGE_PIN AN19 [get_ports clkgen_mgt_refs_lol_b]
set_property IOSTANDARD LVCMOS18 [get_ports clkgen_mgt_refs_*]

#######################################################################

# Bunch clocks from jitter cleaners supplying the high-precision
# clock to the backplane.

# - Backplane lo.
set_property PACKAGE_PIN H26 [get_ports clk_40_backplane_lo_p]
set_property PACKAGE_PIN G26 [get_ports clk_40_backplane_lo_n]
set_property IOSTANDARD LVDS [get_ports clk_40_backplane_lo_*]

# - Backplane hi.
set_property PACKAGE_PIN K25 [get_ports clk_40_backplane_hi_p]
set_property PACKAGE_PIN J25 [get_ports clk_40_backplane_hi_n]
set_property IOSTANDARD LVDS [get_ports clk_40_backplane_hi_*]

#######################################################################

# Bunch clock from the 'MGT' clock cleaner.

# NOTE: This is also the how the backplane clock (either the 40 MHz or
# the 320 MHz, selectable in the clock cleaner) gets to the FPGA.

set_property PACKAGE_PIN AR20 [get_ports clk_40_backplane_regen_p]
set_property PACKAGE_PIN AT20 [get_ports clk_40_backplane_regen_n]
set_property IOSTANDARD LVDS [get_ports clk_40_backplane_regen_*]

#######################################################################

##special clock input from TCDS

#set_property PACKAGE_PIN L15 [get_ports Bunch_clock_p]
#set_property IOSTANDARD LVCMOS33 [get_ports Bunch_clock_p]

#set_property PACKAGE_PIN K18 [get_ports TTC_Orbit_p]
#set_property PACKAGE_PIN J18 [get_ports TTC_Orbit_n]
#set_property IOSTANDARD LVPECL [get_ports TTC_Orbit_p]
#set_property IOSTANDARD LVPECL [get_ports TTC_Orbit_n]
##set_property PACKAGE_PIN AT19 [get_ports TTC_Orbit_p]
##set_property PACKAGE_PIN AU19 [get_ports TTC_Orbit_n]
##set_property IOSTANDARD LVDS [get_ports TTC_Orbit_p]

######################################################################
# I2C bus for power regulators.
######################################################################

#set_property PACKAGE_PIN J12 [get_ports POWER_MAIN_SCL]
#set_property IOSTANDARD LVCMOS33 [get_ports POWER_MAIN_SCL]
#set_property PACKAGE_PIN H14 [get_ports POWER_MAIN_SDA]
#set_property IOSTANDARD LVCMOS33 [get_ports POWER_MAIN_SDA]

#set_property PACKAGE_PIN G12 [get_ports I2C_sel]
#set_property IOSTANDARD LVCMOS33 [get_ports I2C_sel]

######################################################################
# The Xilinx SysMon I2C interface.
######################################################################

set_property PACKAGE_PIN AL24 [get_ports i2c_sysmon_scl]
set_property PACKAGE_PIN AL25 [get_ports i2c_sysmon_sda]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_sysmon_*]

######################################################################
# I2C bus for the EEPROM holding the serial number.
######################################################################

set_property PACKAGE_PIN N14 [get_ports i2c_eeprom_scl]
set_property PACKAGE_PIN N16 [get_ports i2c_eeprom_sda]
set_property IOSTANDARD LVCMOS33 [get_ports i2c_eeprom_*]

######################################################################
# I2C bus for all SiLabs clock generators, as well as the retimers
# for the backplane TCDS signals.
######################################################################

set_property PACKAGE_PIN D12 [get_ports i2c_clks_scl]
set_property PACKAGE_PIN D13 [get_ports i2c_clks_sda]
set_property IOSTANDARD LVCMOS33 [get_ports i2c_clks_*]

######################################################################
# Flash/PROM interface.
######################################################################

# Control lines.
set_property PACKAGE_PIN BA24 [get_ports flash_oen]
set_property IOSTANDARD LVCMOS18 [get_ports flash_oen]
set_property PACKAGE_PIN BA25 [get_ports flash_wen]
set_property IOSTANDARD LVCMOS18 [get_ports flash_wen]
#set_property PACKAGE_PIN AL18 [get_ports flash_cen]
#set_property IOSTANDARD LVCMOS18 [get_ports flash_cen]

# Address lines.
set_property PACKAGE_PIN AN25 [get_ports {flash_add[0]}]
set_property PACKAGE_PIN AN26 [get_ports {flash_add[1]}]
set_property PACKAGE_PIN AP23 [get_ports {flash_add[2]}]
set_property PACKAGE_PIN AR23 [get_ports {flash_add[3]}]
set_property PACKAGE_PIN AR25 [get_ports {flash_add[4]}]
set_property PACKAGE_PIN AR26 [get_ports {flash_add[5]}]
set_property PACKAGE_PIN AT25 [get_ports {flash_add[6]}]
set_property PACKAGE_PIN AT26 [get_ports {flash_add[7]}]
set_property PACKAGE_PIN AT24 [get_ports {flash_add[8]}]
set_property PACKAGE_PIN AU24 [get_ports {flash_add[9]}]
set_property PACKAGE_PIN AV24 [get_ports {flash_add[10]}]
set_property PACKAGE_PIN AV25 [get_ports {flash_add[11]}]
set_property PACKAGE_PIN AU26 [get_ports {flash_add[12]}]
set_property PACKAGE_PIN AU27 [get_ports {flash_add[13]}]
set_property PACKAGE_PIN AT23 [get_ports {flash_add[14]}]
set_property PACKAGE_PIN AU23 [get_ports {flash_add[15]}]
set_property PACKAGE_PIN AV26 [get_ports {flash_add[16]}]
set_property PACKAGE_PIN AV27 [get_ports {flash_add[17]}]
set_property PACKAGE_PIN AW23 [get_ports {flash_add[18]}]
set_property PACKAGE_PIN AW24 [get_ports {flash_add[19]}]
set_property PACKAGE_PIN AY26 [get_ports {flash_add[20]}]
set_property PACKAGE_PIN AY27 [get_ports {flash_add[21]}]
set_property PACKAGE_PIN AY23 [get_ports {flash_add[22]}]
set_property PACKAGE_PIN BA23 [get_ports {flash_add[23]}]
set_property PACKAGE_PIN AY25 [get_ports {flash_add[24]}]
set_property PACKAGE_PIN BA26 [get_ports {flash_add[25]}]

set_property IOSTANDARD LVCMOS18 [get_ports {flash_add[*]}]

# Data lines.
#set_property PACKAGE_PIN AN12 [get_ports flash_data[0]]
#set_property PACKAGE_PIN AM14 [get_ports flash_data[1]]
#set_property PACKAGE_PIN AN14 [get_ports flash_data[2]]
#set_property PACKAGE_PIN AN15 [get_ports flash_data[3]]
set_property PACKAGE_PIN AJ25 [get_ports {flash_data[4]}]
set_property PACKAGE_PIN AK26 [get_ports {flash_data[5]}]
set_property PACKAGE_PIN AM26 [get_ports {flash_data[6]}]
set_property PACKAGE_PIN AM27 [get_ports {flash_data[7]}]
set_property PACKAGE_PIN AK25 [get_ports {flash_data[8]}]
set_property PACKAGE_PIN AL26 [get_ports {flash_data[9]}]
set_property PACKAGE_PIN AM23 [get_ports {flash_data[10]}]
set_property PACKAGE_PIN AM24 [get_ports {flash_data[11]}]
set_property PACKAGE_PIN AP27 [get_ports {flash_data[12]}]
set_property PACKAGE_PIN AR27 [get_ports {flash_data[13]}]
set_property PACKAGE_PIN AN24 [get_ports {flash_data[14]}]
set_property PACKAGE_PIN AP24 [get_ports {flash_data[15]}]

set_property IOSTANDARD LVCMOS18 [get_ports {flash_data[*]}]

######################################################################
# Front-panel clock input SFP.
######################################################################

# - Signal.
# NOTE: The clock signal goes straight into the primary clock cleaner.
# - Control and monitoring.
set_property PACKAGE_PIN C17 [get_ports sfp_clk_frontpanel_modabs]
set_property PACKAGE_PIN G16 [get_ports sfp_clk_frontpanel_los]
set_property PACKAGE_PIN B18 [get_ports sfp_clk_frontpanel_txfault]
set_property PACKAGE_PIN D18 [get_ports sfp_clk_frontpanel_disable]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_clk_frontpanel_*]

######################################################################
# Front-panel TCDS SFPs.
######################################################################

# GTY.
# - TCDS signal (A).
set_property PACKAGE_PIN H36 [get_ports tcds_frontpanel_a_tx_p]
# - Control and monitoring.
set_property PACKAGE_PIN A15 [get_ports sfp_tcds_frontpanel_a_modabs]
set_property PACKAGE_PIN E16 [get_ports sfp_tcds_frontpanel_a_los]
set_property PACKAGE_PIN A16 [get_ports sfp_tcds_frontpanel_a_txfault]
set_property PACKAGE_PIN B16 [get_ports sfp_tcds_frontpanel_a_disable]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_tcds_frontpanel_a_*]

# GTH.
# - TCDS signal (B).
set_property PACKAGE_PIN D6 [get_ports tcds_frontpanel_b_tx_p]
# - Control and monitoring.
set_property PACKAGE_PIN C14 [get_ports sfp_tcds_frontpanel_b_modabs]
set_property PACKAGE_PIN F13 [get_ports sfp_tcds_frontpanel_b_los]
set_property PACKAGE_PIN F15 [get_ports sfp_tcds_frontpanel_b_txfault]
set_property PACKAGE_PIN A14 [get_ports sfp_tcds_frontpanel_b_disable]
set_property IOSTANDARD LVCMOS33 [get_ports sfp_tcds_frontpanel_b_*]

######################################################################
# TCDS connection to the DAQ FPGA.
######################################################################

# MGT 232-1, GTH.
set_property PACKAGE_PIN K6 [get_ports tcds_daq_fpga_tx_p]

######################################################################
# Backplane TCDS signals.
# NOTE: The order etc. is a bit cumbersome due to the fact that the P1
#       mixes GTHs and GTYs, etc.
######################################################################

# NOTE: Slot 1 is the first hub slot, in which the DTH sits, so no pin
# mapping needed for that one.

# - Slot 2. MGT 233-1, GTH X0Y37.
set_property PACKAGE_PIN G8 [get_ports tcds_backplane_slot2_tx_p]
# - Slot 3. MGT 228-1, GTH X0Y17.
set_property PACKAGE_PIN AF6 [get_ports tcds_backplane_slot3_tx_p]
# - Slot 4. MGT 230-3, GTH X0Y27.
set_property PACKAGE_PIN T6 [get_ports tcds_backplane_slot4_tx_p]
# - Slot 5. MGT 226-3, GTH X0Y11.
set_property PACKAGE_PIN AM6 [get_ports tcds_backplane_slot5_tx_p]
# - Slot 6. MGT 230-1, GTH.
set_property PACKAGE_PIN V6 [get_ports tcds_backplane_slot6_tx_p]
# - Slot 7. MGT 228-3, GTH X0Y19.
set_property PACKAGE_PIN AD6 [get_ports tcds_backplane_slot7_tx_p]
# - Slot 8. MGT 129-0, GTY X0Y8.
set_property PACKAGE_PIN AF36 [get_ports tcds_backplane_slot8_tx_p]
# - Slot 9. MGT 127-0, GTY X0Y0.
set_property PACKAGE_PIN AM36 [get_ports tcds_backplane_slot9_tx_p]
# - Slot 10. MGT 129-2, GTY.
set_property PACKAGE_PIN AD36 [get_ports tcds_backplane_slot10_tx_p]
# - Slot 11. MGT 127-2, GTY X0Y2.
set_property PACKAGE_PIN AK36 [get_ports tcds_backplane_slot11_tx_p]
# - Slot 12. MGT 131-0, GTY.
set_property PACKAGE_PIN W38 [get_ports tcds_backplane_slot12_tx_p]
# - Slot 13. MGT 131-3, GTY X0Y19.
set_property PACKAGE_PIN U38 [get_ports tcds_backplane_slot13_tx_p]
# - Slot 14. MGT 132-0, GTY.
set_property PACKAGE_PIN U34 [get_ports tcds_backplane_slot14_tx_p]

######################################################################
## MGT reference clocks.
######################################################################

## GTH.

# MGT224 refclk0: PCIe reference clock.
# MGT224 refclk1: not connected.

# MGT225 refclk0: not connected.
# MGT225 refclk1: not connected.

# MGT226 refclk0: from auxiliary clock generator (IC51).
set_property PACKAGE_PIN AG12 [get_ports mgt_refclk_gth_mgt226_rc0_p]
# MGT226 refclk1: not connected.

# MGT227 refclk0: from secondary clock cleaner (IC40).
set_property PACKAGE_PIN AE12 [get_ports mgt_refclk_gth_mgt227_rc0_p]
# MGT227 refclk1: not connected.

# MGT228 refclk0: not connected.
# MGT228 refclk1: not connected.

# MGT229 refclk0: not connected.
# MGT229 refclk1: not connected.

# MGT230 refclk0: not connected.
# MGT230 refclk1: not connected.

# MGT231 refclk0: from secondary clock cleaner (IC40).
set_property PACKAGE_PIN U12 [get_ports mgt_refclk_gth_mgt231_rc0_p]
# MGT231 refclk1: not connected.

# MGT232 refclk0: from auxiliary clock generator (IC51).
set_property PACKAGE_PIN R12 [get_ports mgt_refclk_gth_mgt232_rc0_p]
# MGT232 refclk1: not connected.

# MGT233 refclk0: from MGT reference clock generator (IC41).
set_property PACKAGE_PIN N12 [get_ports mgt_refclk_gth_mgt233_rc0_p]
# MGT233 refclk1: to MGT reference clock generator (IC41).
# set_property PACKAGE_PIN ??? [get_ports {???}]

# MGT234 refclk0: from secondary clock cleaner (IC40).
set_property PACKAGE_PIN L12 [get_ports mgt_refclk_gth_mgt234_rc0_p]
# MGT234 refclk1: output to recovered clock selector (IC84).
# set_property PACKAGE_PIN ??? [get_ports {???}]

## GTY.

# MGT127 refclk0: from auxiliary clock generator (IC51).
set_property PACKAGE_PIN AG30 [get_ports mgt_refclk_gty_mgt127_rc0_p]
# MGT127 refclk1: not connected.

# MGT128 refclk0: from secondary clock cleaner (IC40).
set_property PACKAGE_PIN AD32 [get_ports mgt_refclk_gty_mgt128_rc0_p]
# MGT128 refclk1: not connected.

# MGT129 refclk0: not connected.
# MGT129 refclk1: not connected.

# MGT130 refclk0: from auxiliary clock generator (IC51), for SLinkRocket.
set_property PACKAGE_PIN Y32 [get_ports mgt_refclk_gty_mgt130_rc0_p]
# MGT130 refclk1: not connected.

# MGT131 refclk0: not connected.
# MGT131 refclk1: not connected.

# MGT132 refclk0: from secondary clock cleaner (IC40).
set_property PACKAGE_PIN T32 [get_ports mgt_refclk_gty_mgt132_rc0_p]
# MGT132 refclk1: from auxiliary clock generator (IC51).
set_property PACKAGE_PIN R30 [get_ports mgt_refclk_gty_mgt132_rc1_p]

# MGT133 refclk0: from auxiliary clock generator (IC51), for FireFly.
set_property PACKAGE_PIN P32 [get_ports mgt_refclk_gty_mgt133_rc0_p]
# MGT133 refclk1: not connected.

# MGT134 refclk0: from secondary clock cleaner (IC40).
set_property PACKAGE_PIN M32 [get_ports mgt_refclk_gty_mgt134_rc0_p]
# MGT134 refclk1: output to recovered clock selector (IC84).
# set_property PACKAGE_PIN ??? [get_ports {???}]

######################################################################

#set_property PACKAGE_PIN D14 [get_ports ClockGen_MAIN_reset]
#set_property IOSTANDARD LVCMOS33 [get_ports ClockGen_MAIN_reset]

###	TCDS  GTH
###  ###############################################################
#set_property PACKAGE_PIN AN8 [get_ports {TCDS_gth_tx_p[0]}]
#set_property PACKAGE_PIN AM6 [get_ports {TCDS_gth_tx_p[1]}]
#set_property PACKAGE_PIN AF6 [get_ports {TCDS_gth_tx_p[2]}]
#set_property PACKAGE_PIN AD6 [get_ports {TCDS_gth_tx_p[3]}]
##  REF CLOCK QPLL0
#set_property PACKAGE_PIN AG12 [get_ports {TCDS_ref_clock_p[0]}]
#set_property PACKAGE_PIN AG11 [get_ports {TCDS_ref_clock_n[0]}]
#set_property PACKAGE_PIN AE12 [get_ports {TCDS_ref_cleaned_clock_p[0]}]
#set_property PACKAGE_PIN AE11 [get_ports {TCDS_ref_cleaned_clock_n[0]}]

##  ###############################################################
#set_property PACKAGE_PIN V6 [get_ports {TCDS_gth_tx_p[4]}]
#set_property PACKAGE_PIN T6 [get_ports {TCDS_gth_tx_p[5]}]
#set_property PACKAGE_PIN K6 [get_ports {TCDS_gth_tx_p[6]}]
#set_property PACKAGE_PIN H6 [get_ports {TCDS_gth_tx_p[7]}]

##  REF CLOCK QPLL0
#set_property PACKAGE_PIN R11 [get_ports {TCDS_ref_clock_n[1]}]
#set_property PACKAGE_PIN R12 [get_ports {TCDS_ref_clock_p[1]}]
#set_property PACKAGE_PIN U12 [get_ports {TCDS_ref_cleaned_clock_p[1]}]
#set_property PACKAGE_PIN U11 [get_ports {TCDS_ref_cleaned_clock_n[1]}]

##  TCDS GTY
##   ###############################################################
#set_property PACKAGE_PIN AM36 [get_ports {TCDS_gty_tx_p[0]}]
#set_property PACKAGE_PIN AK36 [get_ports {TCDS_gty_tx_p[1]}]
#set_property PACKAGE_PIN AF36 [get_ports {TCDS_gty_tx_p[2]}]
#set_property PACKAGE_PIN AD36 [get_ports {TCDS_gty_tx_p[3]}]

##  REF CLOCK QPLL0
#set_property PACKAGE_PIN AG30 [get_ports {TCDS_ref_clock_p[2]}]
#set_property PACKAGE_PIN AG31 [get_ports {TCDS_ref_clock_n[2]}]
#set_property PACKAGE_PIN AD32 [get_ports {TCDS_ref_cleaned_clock_p[2]}]
#set_property PACKAGE_PIN AD33 [get_ports {TCDS_ref_cleaned_clock_n[2]}]

##  ###############################################################
#set_property PACKAGE_PIN W38 [get_ports {TCDS_gty_tx_p[4]}]
#set_property PACKAGE_PIN U38 [get_ports {TCDS_gty_tx_p[5]}]
#set_property PACKAGE_PIN U34 [get_ports {TCDS_gty_tx_p[6]}]
#set_property PACKAGE_PIN R34 [get_ports {TCDS_gty_tx_p[7]}]

##  REF CLOCK QPLL0
#set_property PACKAGE_PIN R31 [get_ports {TCDS_ref_clock_n[3]}]
#set_property PACKAGE_PIN R30 [get_ports {TCDS_ref_clock_p[3]}]
#set_property PACKAGE_PIN T32 [get_ports {TCDS_ref_cleaned_clock_p[3]}]
#set_property PACKAGE_PIN T33 [get_ports {TCDS_ref_cleaned_clock_n[3]}]

##################################################################
##TCDS connection when card in node
#set_property PACKAGE_PIN G8 [get_ports {TCDS_DAQ_tx_p}]

#set_property PACKAGE_PIN N12 [get_ports {TCDS_DAQ_ref_clock_p}]

#set_property PACKAGE_PIN M10 [get_ports {tcds_daq_refclock_out_p}]

######################################################################
# Select line of IC84, which selects the recovered MGT clock from the
# TCDS input SFP between the GTY and GTY banks.
######################################################################

set_property PACKAGE_PIN A18 [get_ports sel_recclk_out]
set_property IOSTANDARD LVCMOS33 [get_ports sel_recclk_out]

######################################################################

## SELECT clock from backplane
#set_property PACKAGE_PIN A19 [get_ports SEL_BP_INPUT]
#set_property IOSTANDARD LVCMOS33 [get_ports SEL_BP_INPUT]

## reconstructed clock out shared between  GTY GTH
#set_property PACKAGE_PIN AP30 [get_ports tcds_sfp_clk_out_n]
#set_property IOSTANDARD LVCMOS18 [get_ports tcds_sfp_clk_out_n]
#set_property PACKAGE_PIN AP29 [get_ports tcds_sfp_clk_out_p]
#set_property IOSTANDARD LVCMOS18 [get_ports tcds_sfp_clk_out_p]

## Ref RECONSTRUCTED clock OUT
#set_property PACKAGE_PIN K9 [get_ports tcds_gth_refclock_out_n]
#set_property PACKAGE_PIN K10 [get_ports tcds_gth_refclock_out_p]
## Ref recontruCtred  clock OUT
#set_property PACKAGE_PIN L31 [get_ports tcds_gty_refclock_out_n]
#set_property PACKAGE_PIN L30 [get_ports tcds_gty_refclock_out_p]

######################################################################
## Reconstructed bunch clock outputs.
######################################################################

## To primary clock cleaner.
set_property PACKAGE_PIN H27 [get_ports tcds_clk_40_out_pri_p]
set_property PACKAGE_PIN G27 [get_ports tcds_clk_40_out_pri_n]
set_property IOSTANDARD LVDS [get_ports tcds_clk_40_out_pri_*]

## To secondary clock cleaner.
set_property PACKAGE_PIN K26 [get_ports tcds_clk_40_out_sec_p]
set_property PACKAGE_PIN J27 [get_ports tcds_clk_40_out_sec_n]
set_property IOSTANDARD LVDS [get_ports tcds_clk_40_out_sec_*]

######################################################################
# I2C bus for the TCDS SFPs and FireFly,
# as well as the P1 temperature sensors.
######################################################################

set_property PACKAGE_PIN C12 [get_ports i2c_optics_scl]
set_property PACKAGE_PIN A13 [get_ports i2c_optics_sda]
set_property IOSTANDARD LVCMOS33 [get_ports i2c_optics_*]

#set_property PACKAGE_PIN B12 [get_ports SFPP_reset]
#set_property IOSTANDARD LVCMOS33 [get_ports SFPP_reset]

#set_property PACKAGE_PIN E18 [get_ports TCDS_TEMP_RESET]
#set_property IOSTANDARD LVCMOS33 [get_ports TCDS_TEMP_RESET]
##    ###############################################################

#set_property PACKAGE_PIN AV21 [get_ports lhc_clock_0_present]
#set_property IOSTANDARD LVCMOS18 [get_ports lhc_clock_0_present]
#set_property PACKAGE_PIN AR21 [get_ports lhc_clock_1_present]
#set_property IOSTANDARD LVCMOS18 [get_ports lhc_clock_1_present]

##    ###############################################################
##  tcds signal sent and received on transceiver 10Gb (DS110DF410)
#set_property PACKAGE_PIN P19 [get_ports DS100_0_CDR_UNLOCKED]
#set_property PACKAGE_PIN R18 [get_ports DS100_0_CDR0_UNLOCKED]
#set_property PACKAGE_PIN J19 [get_ports DS100_0_CDR2_UNLOCKED]
#set_property PACKAGE_PIN G18 [get_ports DS100_0_CDR3_UNLOCKED]
#set_property PACKAGE_PIN H17 [get_ports DS100_0_CDR4_UNLOCKED]
#set_property PACKAGE_PIN J17 [get_ports DS100_1_CDR_UNLOCKED]
#set_property PACKAGE_PIN H19 [get_ports DS100_1_CDR0_UNLOCKED]
#set_property PACKAGE_PIN K17 [get_ports DS100_1_CDR2_UNLOCKED]
#set_property PACKAGE_PIN M19 [get_ports DS100_1_CDR3_UNLOCKED]
#set_property PACKAGE_PIN N19 [get_ports DS100_1_CDR4_UNLOCKED]

#set_property IOSTANDARD LVCMOS25 [get_ports DS100_0_CDR_UNLOCKED]
#set_property IOSTANDARD LVCMOS25 [get_ports DS100_0_CDR0_UNLOCKED]
#set_property IOSTANDARD LVCMOS25 [get_ports DS100_0_CDR2_UNLOCKED]
#set_property IOSTANDARD LVCMOS25 [get_ports DS100_0_CDR3_UNLOCKED]
#set_property IOSTANDARD LVCMOS25 [get_ports DS100_0_CDR4_UNLOCKED]
#set_property IOSTANDARD LVCMOS25 [get_ports DS100_1_CDR_UNLOCKED]
#set_property IOSTANDARD LVCMOS25 [get_ports DS100_1_CDR0_UNLOCKED]
#set_property IOSTANDARD LVCMOS25 [get_ports DS100_1_CDR2_UNLOCKED]
#set_property IOSTANDARD LVCMOS25 [get_ports DS100_1_CDR3_UNLOCKED]
#set_property IOSTANDARD LVCMOS25 [get_ports DS100_1_CDR4_UNLOCKED]

## mux for Analog inpout
#set_property PACKAGE_PIN J14 [get_ports {sel_analog_addr[0]}]
#set_property PACKAGE_PIN J15 [get_ports {sel_analog_addr[1]}]
#set_property PACKAGE_PIN K15 [get_ports {sel_analog_addr[2]}]
#set_property PACKAGE_PIN L14 [get_ports {sel_analog_addr[3]}]
#set_property PACKAGE_PIN L16 [get_ports {sel_analog_addr[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sel_analog_addr[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sel_analog_addr[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sel_analog_addr[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sel_analog_addr[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sel_analog_addr[4]}]

##################
##  Slink Rocket
#set_property PACKAGE_PIN Y32 [get_ports Ref_clock_SR_p]

#set_property PACKAGE_PIN AB36 [get_ports SR_TX_p[0]]
#set_property PACKAGE_PIN AA34 [get_ports SR_TX_p[1]]

#set_property PACKAGE_PIN P32 [get_ports Ref_clock_SR_FF_p]

#set_property LOC GTYE4_CHANNEL_X0Y24 [get_cells {Firefly_GTY_ibert_i1/inst/QUAD[0].u_q/CH[0].u_ch/u_gtye4_channel}]
#set_property PACKAGE_PIN P36 [get_ports {SR_FF_TX_p[0]}]
##set_property PACKAGE_PIN H41 [get_ports SR_FF_RX_p[0]]
#set_property LOC GTYE4_CHANNEL_X0Y25 [get_cells {Firefly_GTY_ibert_i1/inst/QUAD[0].u_q/CH[1].u_ch/u_gtye4_channel}]
#set_property PACKAGE_PIN N34 [get_ports {SR_FF_TX_p[1]}]
##set_property PACKAGE_PIN G39 [get_ports SR_FF_RX_p[1]]
#set_property LOC GTYE4_CHANNEL_X0Y26 [get_cells {Firefly_GTY_ibert_i1/inst/QUAD[0].u_q/CH[2].u_ch/u_gtye4_channel}]
#set_property PACKAGE_PIN M36 [get_ports {SR_FF_TX_p[2]}]
##set_property PACKAGE_PIN F41 [get_ports SR_FF_RX_p[2]]
#set_property LOC GTYE4_CHANNEL_X0Y27 [get_cells {Firefly_GTY_ibert_i1/inst/QUAD[0].u_q/CH[3].u_ch/u_gtye4_channel}]
#set_property PACKAGE_PIN L34 [get_ports {SR_FF_TX_p[3]}]
##set_property PACKAGE_PIN E39 [get_ports SR_FF_RX_p[3]]

#set_property PACKAGE_PIN D20 [get_ports FF_PRESENT]
#set_property IOSTANDARD LVCMOS33 [get_ports FF_PRESENT]
#set_property PACKAGE_PIN C19 [get_ports FF_RESET_L]
#set_property IOSTANDARD LVCMOS33 [get_ports FF_RESET_L]
#set_property PACKAGE_PIN A20 [get_ports FF_CS]
#set_property IOSTANDARD LVCMOS33 [get_ports FF_CS]
#set_property PACKAGE_PIN F19 [get_ports FF_INTL_L]
#set_property IOSTANDARD LVCMOS33 [get_ports FF_INTL_L]

######################################################################
# Single lane PCIe interface.
######################################################################

set_property PACKAGE_PIN AL12 [get_ports pcie_sys_clk_p]

set_property PACKAGE_PIN AN27 [get_ports pcie_sys_rst_n]
set_property IOSTANDARD LVCMOS18 [get_ports pcie_sys_rst_n]
set_property PULLUP true [get_ports pcie_sys_rst_n]

set_property PACKAGE_PIN BB6 [get_ports {pcie_rx_p[0]}]
set_property PACKAGE_PIN AW8 [get_ports {pcie_tx_p[0]}]

######################################################################
# Diagnostic LEDs.
######################################################################

set_property PACKAGE_PIN AM28 [get_ports {user_leds[0]}]
set_property PACKAGE_PIN AL29 [get_ports {user_leds[1]}]
set_property PACKAGE_PIN AK28 [get_ports {user_leds[2]}]
set_property PACKAGE_PIN AJ29 [get_ports {user_leds[3]}]
set_property PACKAGE_PIN AN30 [get_ports {user_leds[4]}]
set_property PACKAGE_PIN AL30 [get_ports {user_leds[5]}]
set_property PACKAGE_PIN AM31 [get_ports {user_leds[6]}]
set_property PACKAGE_PIN AK32 [get_ports {user_leds[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {user_leds[*]}]

######################################################################
# Reserved pins.
######################################################################

#set_property PACKAGE_PIN N28 [get_ports {reserved[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[0]}]
#set_property PACKAGE_PIN N28 [get_ports {reserved_o[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved_o[0]}]
#set_property PACKAGE_PIN M28 [get_ports {reserved[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[1]}]
#set_property PACKAGE_PIN M28 [get_ports {reserved_o[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved_o[1]}]
#set_property PACKAGE_PIN L28 [get_ports {reserved[2]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[2]}]
#set_property PACKAGE_PIN K27 [get_ports {reserved[3]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[3]}]
#set_property PACKAGE_PIN F28 [get_ports {reserved[4]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[4]}]
#set_property PACKAGE_PIN E27 [get_ports {reserved[5]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[5]}]
#set_property PACKAGE_PIN A29 [get_ports {reserved[6]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[6]}]
#set_property PACKAGE_PIN D28 [get_ports {reserved[7]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[7]}]
#set_property PACKAGE_PIN B28 [get_ports {reserved[8]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[8]}]
#set_property PACKAGE_PIN A28 [get_ports {reserved[9]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[9]}]
#set_property PACKAGE_PIN C27 [get_ports {reserved[10]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[10]}]
#set_property PACKAGE_PIN B27 [get_ports {reserved[11]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[11]}]
#set_property PACKAGE_PIN C26 [get_ports {reserved[12]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[12]}]
#set_property PACKAGE_PIN B26 [get_ports {reserved[13]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[13]}]
#set_property PACKAGE_PIN A26 [get_ports {reserved[14]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[14]}]
#set_property PACKAGE_PIN F26 [get_ports {reserved[15]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[15]}]
#set_property PACKAGE_PIN A25 [get_ports {reserved[16]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[16]}]
#set_property PACKAGE_PIN C25 [get_ports {reserved[17]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[17]}]
#set_property PACKAGE_PIN E25 [get_ports {reserved[18]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[18]}]
#set_property PACKAGE_PIN F25 [get_ports {reserved[19]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[19]}]
#set_property PACKAGE_PIN H25 [get_ports {reserved[20]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[20]}]
#set_property PACKAGE_PIN M27 [get_ports {reserved[21]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[21]}]
#set_property PACKAGE_PIN N27 [get_ports {reserved[22]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[22]}]
#set_property PACKAGE_PIN L26 [get_ports {reserved[23]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[23]}]
#set_property PACKAGE_PIN M26 [get_ports {reserved[24]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[24]}]
#set_property PACKAGE_PIN N26 [get_ports {reserved[25]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[25]}]
#set_property PACKAGE_PIN L25 [get_ports {reserved[26]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[26]}]
#set_property PACKAGE_PIN M24 [get_ports {reserved[27]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {reserved[27]}]

#set_property PACKAGE_PIN A9 [get_ports {reserved[28]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {reserved[28]}]
#set_property PACKAGE_PIN A10 [get_ports {reserved[29]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {reserved[29]}]
#set_property PACKAGE_PIN A11 [get_ports {reserved[30]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {reserved[30]}]
#set_property PACKAGE_PIN B10 [get_ports {reserved[31]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {reserved[31]}]

######################################################################