--====================================================================== library ieee; use ieee.std_logic_1164.all; library unisim; use unisim.vcomponents.all; use work.ipbus.all; use work.dth_tcds_infra_status.all; use work.ipbus_decode_dth_tcds_top.all; --================================================== entity top is port ( -- PCIe clock and reset. pcie_sys_clk_p : in std_logic; pcie_sys_clk_n : in std_logic; -- Note: reset is active low. pcie_sys_rst_n : in std_logic; -- PCIe data lane. pcie_rx_p : in std_logic_vector(0 downto 0); pcie_rx_n : in std_logic_vector(0 downto 0); pcie_tx_p : out std_logic_vector(0 downto 0); pcie_tx_n : out std_logic_vector(0 downto 0); -- Xilinx SysMon I2C interface. -- NOTE: This is a slave. i2c_sysmon_scl : in std_logic; i2c_sysmon_sda : in std_logic; -- I2C bus for the EEPROM holding the serial number. i2c_eeprom_scl : out std_logic; i2c_eeprom_sda : inout std_logic; -- I2C bus for all SiLabs clock generators. i2c_clks_scl : out std_logic; i2c_clks_sda : inout std_logic; -- I2C bus for the TCDS SFPs and FireFly. -- NOTE: On the P1, the additional temperature sensors are -- connected to this bus as well. i2c_optics_scl : out std_logic; i2c_optics_sda : inout std_logic; -- Flash interface. -- NOTE: This is a 16-bit interface, but the bottom four bits are -- governed under the hood by the STARTUPE3 primitive (which rules -- the FPGA configuration) pins. flash_data : inout std_logic_vector(15 downto 4); flash_add : out std_logic_vector(25 downto 0); flash_oen : out std_logic; flash_wen : out std_logic; -- General purpose clocks from IC51. clk_gp_100mhz_p : in std_logic; clk_gp_100mhz_n : in std_logic; clk_gp_125mhz_p : in std_logic; clk_gp_125mhz_n : in std_logic; clk_gp_156_25mhz_p : in std_logic; clk_gp_156_25mhz_n : in std_logic; -- Bunch clocks coming from the two clock cleaners supplying the -- high-precision clock to the backplane. clk_40_backplane_lo_p : in std_logic; clk_40_backplane_lo_n : in std_logic; clk_40_backplane_hi_p : in std_logic; clk_40_backplane_hi_n : in std_logic; -- Bunch clock coming from the 'MGT' clock cleaner (typically -- regenerated from either the 40 MHz or the 320 MHz backplane -- clock). clk_40_backplane_regen_p : in std_logic; clk_40_backplane_regen_n : in std_logic; -- GTH reference clocks. mgt_refclk_gth_mgt226_rc0_p : in std_logic; mgt_refclk_gth_mgt226_rc0_n : in std_logic; mgt_refclk_gth_mgt227_rc0_p : in std_logic; mgt_refclk_gth_mgt227_rc0_n : in std_logic; mgt_refclk_gth_mgt231_rc0_p : in std_logic; mgt_refclk_gth_mgt231_rc0_n : in std_logic; mgt_refclk_gth_mgt232_rc0_p : in std_logic; mgt_refclk_gth_mgt232_rc0_n : in std_logic; mgt_refclk_gth_mgt233_rc0_p : in std_logic; mgt_refclk_gth_mgt233_rc0_n : in std_logic; mgt_refclk_gth_mgt234_rc0_p : in std_logic; mgt_refclk_gth_mgt234_rc0_n : in std_logic; -- GTY reference clocks. mgt_refclk_gty_mgt127_rc0_p : in std_logic; mgt_refclk_gty_mgt127_rc0_n : in std_logic; mgt_refclk_gty_mgt128_rc0_p : in std_logic; mgt_refclk_gty_mgt128_rc0_n : in std_logic; mgt_refclk_gty_mgt130_rc0_p : in std_logic; mgt_refclk_gty_mgt130_rc0_n : in std_logic; mgt_refclk_gty_mgt132_rc0_p : in std_logic; mgt_refclk_gty_mgt132_rc0_n : in std_logic; mgt_refclk_gty_mgt132_rc1_p : in std_logic; mgt_refclk_gty_mgt132_rc1_n : in std_logic; mgt_refclk_gty_mgt133_rc0_p : in std_logic; mgt_refclk_gty_mgt133_rc0_n : in std_logic; mgt_refclk_gty_mgt134_rc0_p : in std_logic; mgt_refclk_gty_mgt134_rc0_n : in std_logic; -- General purpose clock generator (IC51) reset and status lines. clkgen_gp_reset_b : out std_logic; clkgen_gp_intr_b : in std_logic; clkgen_gp_lol_b : in std_logic; clkgen_gp_los_b : in std_logic; -- Master clock generator (IC50) reset, control, and status lines. clkgen_master_reset_b : out std_logic; clkgen_master_in_sel : out std_logic_vector(1 downto 0); clkgen_master_intr_b : in std_logic; clkgen_master_lol_b : in std_logic; -- Secondary clock generator (IC40) reset, control, and status lines. clkgen_secondary_reset_b : out std_logic; clkgen_secondary_in_sel : out std_logic_vector(1 downto 0); clkgen_secondary_intr_b : in std_logic; clkgen_secondary_lol_b : in std_logic; -- Backplane clock generators (IC55 and IC53) reset and control lines. clkgen_backplane_lo_reset_b : out std_logic; clkgen_backplane_lo_in_sel : out std_logic_vector(1 downto 0); clkgen_backplane_lo_intr_b : in std_logic; clkgen_backplane_lo_lol_b : in std_logic; clkgen_backplane_hi_reset_b : out std_logic; clkgen_backplane_hi_in_sel : out std_logic_vector(1 downto 0); clkgen_backplane_hi_intr_b : in std_logic; clkgen_backplane_hi_lol_b : in std_logic; -- MGT reference clocks generator (IC41) reset and control lines. clkgen_mgt_refs_reset_b : out std_logic; clkgen_mgt_refs_in_sel : out std_logic_vector(1 downto 0); clkgen_mgt_refs_intr_b : in std_logic; clkgen_mgt_refs_lol_b : in std_logic; -- Clock selection lines. -- - The select line of IC84, switching between the GTH and GTY -- recovered MGT clocks. sel_recclk_out : out std_logic; -- Recover bunch clock outputs to the primary and secondary clock -- cleaners. tcds_clk_40_out_pri_p : out std_logic; tcds_clk_40_out_pri_n : out std_logic; tcds_clk_40_out_sec_p : out std_logic; tcds_clk_40_out_sec_n : out std_logic; -- Status/diagnostic LEDs. user_leds : out std_logic_vector(7 downto 0); -- Front-panel clock input SFP control and monitoring. sfp_clk_frontpanel_modabs : in std_logic; sfp_clk_frontpanel_los : in std_logic; sfp_clk_frontpanel_txfault : in std_logic; sfp_clk_frontpanel_disable : out std_logic; -- Front-panel TCDS SFPs. -- TCDS A (GTY), signal. tcds_frontpanel_a_tx_p : out std_logic; tcds_frontpanel_a_tx_n : out std_logic; tcds_frontpanel_a_rx_p : in std_logic; tcds_frontpanel_a_rx_n : in std_logic; -- TCDS A (GTY), control and monitoring. sfp_tcds_frontpanel_a_modabs : in std_logic; sfp_tcds_frontpanel_a_los : in std_logic; sfp_tcds_frontpanel_a_txfault : in std_logic; sfp_tcds_frontpanel_a_disable : out std_logic; -- TCDS B (GTH), signal. tcds_frontpanel_b_tx_p : out std_logic; tcds_frontpanel_b_tx_n : out std_logic; tcds_frontpanel_b_rx_p : in std_logic; tcds_frontpanel_b_rx_n : in std_logic; -- TCDS B (GTH), control and monitoring. sfp_tcds_frontpanel_b_modabs : in std_logic; sfp_tcds_frontpanel_b_los : in std_logic; sfp_tcds_frontpanel_b_txfault : in std_logic; sfp_tcds_frontpanel_b_disable : out std_logic; -- DAQ FPGA TCDS connection. tcds_daq_fpga_tx_p : out std_logic; tcds_daq_fpga_tx_n : out std_logic; tcds_daq_fpga_rx_p : in std_logic; tcds_daq_fpga_rx_n : in std_logic; -- Backplane TCDS signals. -- NOTE: Slot 1 (i.e., index 0) is the first hub slot, in which the DTH sits. tcds_backplane_slot2_tx_p : out std_logic; tcds_backplane_slot2_tx_n : out std_logic; tcds_backplane_slot2_rx_p : in std_logic; tcds_backplane_slot2_rx_n : in std_logic; -- tcds_backplane_slot3_tx_p : out std_logic; tcds_backplane_slot3_tx_n : out std_logic; tcds_backplane_slot3_rx_p : in std_logic; tcds_backplane_slot3_rx_n : in std_logic; -- tcds_backplane_slot4_tx_p : out std_logic; tcds_backplane_slot4_tx_n : out std_logic; tcds_backplane_slot4_rx_p : in std_logic; tcds_backplane_slot4_rx_n : in std_logic; -- tcds_backplane_slot5_tx_p : out std_logic; tcds_backplane_slot5_tx_n : out std_logic; tcds_backplane_slot5_rx_p : in std_logic; tcds_backplane_slot5_rx_n : in std_logic; -- tcds_backplane_slot6_tx_p : out std_logic; tcds_backplane_slot6_tx_n : out std_logic; tcds_backplane_slot6_rx_p : in std_logic; tcds_backplane_slot6_rx_n : in std_logic; -- tcds_backplane_slot7_tx_p : out std_logic; tcds_backplane_slot7_tx_n : out std_logic; tcds_backplane_slot7_rx_p : in std_logic; tcds_backplane_slot7_rx_n : in std_logic; -- tcds_backplane_slot8_tx_p : out std_logic; tcds_backplane_slot8_tx_n : out std_logic; tcds_backplane_slot8_rx_p : in std_logic; tcds_backplane_slot8_rx_n : in std_logic; -- tcds_backplane_slot9_tx_p : out std_logic; tcds_backplane_slot9_tx_n : out std_logic; tcds_backplane_slot9_rx_p : in std_logic; tcds_backplane_slot9_rx_n : in std_logic; -- tcds_backplane_slot10_tx_p : out std_logic; tcds_backplane_slot10_tx_n : out std_logic; tcds_backplane_slot10_rx_p : in std_logic; tcds_backplane_slot10_rx_n : in std_logic; -- tcds_backplane_slot11_tx_p : out std_logic; tcds_backplane_slot11_tx_n : out std_logic; tcds_backplane_slot11_rx_p : in std_logic; tcds_backplane_slot11_rx_n : in std_logic; -- tcds_backplane_slot12_tx_p : out std_logic; tcds_backplane_slot12_tx_n : out std_logic; tcds_backplane_slot12_rx_p : in std_logic; tcds_backplane_slot12_rx_n : in std_logic; -- tcds_backplane_slot13_tx_p : out std_logic; tcds_backplane_slot13_tx_n : out std_logic; tcds_backplane_slot13_rx_p : in std_logic; tcds_backplane_slot13_rx_n : in std_logic; -- tcds_backplane_slot14_tx_p : out std_logic; tcds_backplane_slot14_tx_n : out std_logic; tcds_backplane_slot14_rx_p : in std_logic; tcds_backplane_slot14_rx_n : in std_logic ); end top; --================================================== architecture rtl of top is signal clk_ipb, rst_ipb : std_logic; signal clk_aux, rst_aux : std_logic; signal nuke_i, soft_rst_i : std_logic; signal infra_status_i : dth_tcds_infra_status; -- IPBus read/write buses. signal ipb_in : ipb_wbus; signal ipb_out : ipb_rbus; signal ipbw : ipb_wbus_array(N_SLAVES - 1 downto 0); signal ipbr : ipb_rbus_array(N_SLAVES - 1 downto 0); begin -- Infrastructure: PCIe interface, etc. infra : entity work.dth_tcds_infra port map ( pcie_sys_clk_p => pcie_sys_clk_p, pcie_sys_clk_n => pcie_sys_clk_n, pcie_sys_rst_n => pcie_sys_rst_n, pcie_rx_p => pcie_rx_p, pcie_rx_n => pcie_rx_n, pcie_tx_p => pcie_tx_p, pcie_tx_n => pcie_tx_n, clk_ipb_o => clk_ipb, rst_ipb_o => rst_ipb, ipb_in => ipb_out, ipb_out => ipb_in, clk_aux_o => clk_aux, rst_aux_o => rst_aux, nuke => nuke_i, soft_rst => soft_rst_i, status => infra_status_i ); ------------------------------------------ -- IPBus address decoder. fabric : entity work.ipbus_fabric_sel generic map ( NSLV => N_SLAVES, SEL_WIDTH => IPBUS_SEL_WIDTH ) port map ( ipb_in => ipb_in, ipb_out => ipb_out, sel => ipbus_sel_dth_tcds_top(ipb_in.ipb_addr), ipb_to_slaves => ipbw, ipb_from_slaves => ipbr ); ------------------------------------------ sys_main : entity work.dth_tcds_sys_main port map ( clk_ipb => clk_ipb, rst_ipb => rst_ipb, ipb_in => ipbw(N_SLV_SYSTEM_MAIN), ipb_out => ipbr(N_SLV_SYSTEM_MAIN), clk_aux => clk_aux, rst_aux => rst_aux, nuke => nuke_i, soft_rst => soft_rst_i, infra_status => infra_status_i, i2c_sysmon_scl => i2c_sysmon_scl, i2c_sysmon_sda => i2c_sysmon_sda, i2c_eeprom_scl => i2c_eeprom_scl, i2c_eeprom_sda => i2c_eeprom_sda, i2c_clks_scl => i2c_clks_scl, i2c_clks_sda => i2c_clks_sda, i2c_optics_scl => i2c_optics_scl, i2c_optics_sda => i2c_optics_sda, flash_data => flash_data, flash_add => flash_add, flash_oen => flash_oen, flash_wen => flash_wen, clkgen_gp_reset_b => clkgen_gp_reset_b, clkgen_gp_intr_b => clkgen_gp_intr_b, clkgen_gp_lol_b => clkgen_gp_lol_b, clkgen_gp_los_b => clkgen_gp_los_b, clkgen_master_reset_b => clkgen_master_reset_b, clkgen_master_in_sel => clkgen_master_in_sel, clkgen_master_intr_b => clkgen_master_intr_b, clkgen_master_lol_b => clkgen_master_lol_b, clkgen_secondary_reset_b => clkgen_secondary_reset_b, clkgen_secondary_in_sel => clkgen_secondary_in_sel, clkgen_secondary_intr_b => clkgen_secondary_intr_b, clkgen_secondary_lol_b => clkgen_secondary_lol_b, clkgen_backplane_lo_reset_b => clkgen_backplane_lo_reset_b, clkgen_backplane_lo_in_sel => clkgen_backplane_lo_in_sel, clkgen_backplane_lo_intr_b => clkgen_backplane_lo_intr_b, clkgen_backplane_lo_lol_b => clkgen_backplane_lo_lol_b, clkgen_backplane_hi_reset_b => clkgen_backplane_hi_reset_b, clkgen_backplane_hi_in_sel => clkgen_backplane_hi_in_sel, clkgen_backplane_hi_intr_b => clkgen_backplane_hi_intr_b, clkgen_backplane_hi_lol_b => clkgen_backplane_hi_lol_b, clkgen_mgt_refs_reset_b => clkgen_mgt_refs_reset_b, clkgen_mgt_refs_in_sel => clkgen_mgt_refs_in_sel, clkgen_mgt_refs_intr_b => clkgen_mgt_refs_intr_b, clkgen_mgt_refs_lol_b => clkgen_mgt_refs_lol_b, sfp_clk_frontpanel_modabs => sfp_clk_frontpanel_modabs, sfp_clk_frontpanel_los => sfp_clk_frontpanel_los, sfp_clk_frontpanel_txfault => sfp_clk_frontpanel_txfault, sfp_clk_frontpanel_disable => sfp_clk_frontpanel_disable, sfp_tcds_frontpanel_a_modabs => sfp_tcds_frontpanel_a_modabs, sfp_tcds_frontpanel_a_los => sfp_tcds_frontpanel_a_los, sfp_tcds_frontpanel_a_txfault => sfp_tcds_frontpanel_a_txfault, sfp_tcds_frontpanel_a_disable => sfp_tcds_frontpanel_a_disable, sfp_tcds_frontpanel_b_modabs => sfp_tcds_frontpanel_b_modabs, sfp_tcds_frontpanel_b_los => sfp_tcds_frontpanel_b_los, sfp_tcds_frontpanel_b_txfault => sfp_tcds_frontpanel_b_txfault, sfp_tcds_frontpanel_b_disable => sfp_tcds_frontpanel_b_disable ); ------------------------------------------ -- Main user payload. user_main : entity work.dth_tcds_user_main port map ( clk_ipb => clk_ipb, rst_ipb => rst_ipb, ipb_in => ipbw(N_SLV_USER_MAIN), ipb_out => ipbr(N_SLV_USER_MAIN), clk_aux => clk_aux, rst_aux => rst_aux, nuke => nuke_i, soft_rst => soft_rst_i, infra_status => infra_status_i, clk_gp_100mhz_p => clk_gp_100mhz_p, clk_gp_100mhz_n => clk_gp_100mhz_n, clk_gp_125mhz_p => clk_gp_125mhz_p, clk_gp_125mhz_n => clk_gp_125mhz_n, clk_gp_156_25mhz_p => clk_gp_156_25mhz_p, clk_gp_156_25mhz_n => clk_gp_156_25mhz_n, clk_40_backplane_lo_p => clk_40_backplane_lo_p, clk_40_backplane_lo_n => clk_40_backplane_lo_n, clk_40_backplane_hi_p => clk_40_backplane_hi_p, clk_40_backplane_hi_n => clk_40_backplane_hi_n, clk_40_backplane_regen_p => clk_40_backplane_regen_p, clk_40_backplane_regen_n => clk_40_backplane_regen_n, mgt_refclk_gth_mgt226_rc0_p => mgt_refclk_gth_mgt226_rc0_p, mgt_refclk_gth_mgt226_rc0_n => mgt_refclk_gth_mgt226_rc0_n, mgt_refclk_gth_mgt227_rc0_p => mgt_refclk_gth_mgt227_rc0_p, mgt_refclk_gth_mgt227_rc0_n => mgt_refclk_gth_mgt227_rc0_n, mgt_refclk_gth_mgt231_rc0_p => mgt_refclk_gth_mgt231_rc0_p, mgt_refclk_gth_mgt231_rc0_n => mgt_refclk_gth_mgt231_rc0_n, mgt_refclk_gth_mgt232_rc0_p => mgt_refclk_gth_mgt232_rc0_p, mgt_refclk_gth_mgt232_rc0_n => mgt_refclk_gth_mgt232_rc0_n, mgt_refclk_gth_mgt233_rc0_p => mgt_refclk_gth_mgt233_rc0_p, mgt_refclk_gth_mgt233_rc0_n => mgt_refclk_gth_mgt233_rc0_n, mgt_refclk_gth_mgt234_rc0_p => mgt_refclk_gth_mgt234_rc0_p, mgt_refclk_gth_mgt234_rc0_n => mgt_refclk_gth_mgt234_rc0_n, mgt_refclk_gty_mgt127_rc0_p => mgt_refclk_gty_mgt127_rc0_p, mgt_refclk_gty_mgt127_rc0_n => mgt_refclk_gty_mgt127_rc0_n, mgt_refclk_gty_mgt128_rc0_p => mgt_refclk_gty_mgt128_rc0_p, mgt_refclk_gty_mgt128_rc0_n => mgt_refclk_gty_mgt128_rc0_n, mgt_refclk_gty_mgt130_rc0_p => mgt_refclk_gty_mgt130_rc0_p, mgt_refclk_gty_mgt130_rc0_n => mgt_refclk_gty_mgt130_rc0_n, mgt_refclk_gty_mgt132_rc0_p => mgt_refclk_gty_mgt132_rc0_p, mgt_refclk_gty_mgt132_rc0_n => mgt_refclk_gty_mgt132_rc0_n, mgt_refclk_gty_mgt132_rc1_p => mgt_refclk_gty_mgt132_rc1_p, mgt_refclk_gty_mgt132_rc1_n => mgt_refclk_gty_mgt132_rc1_n, mgt_refclk_gty_mgt133_rc0_p => mgt_refclk_gty_mgt133_rc0_p, mgt_refclk_gty_mgt133_rc0_n => mgt_refclk_gty_mgt133_rc0_n, mgt_refclk_gty_mgt134_rc0_p => mgt_refclk_gty_mgt134_rc0_p, mgt_refclk_gty_mgt134_rc0_n => mgt_refclk_gty_mgt134_rc0_n, -- sel_recclk_out => sel_recclk_out, tcds_clk_40_out_pri_p => tcds_clk_40_out_pri_p, tcds_clk_40_out_pri_n => tcds_clk_40_out_pri_n, tcds_clk_40_out_sec_p => tcds_clk_40_out_sec_p, tcds_clk_40_out_sec_n => tcds_clk_40_out_sec_n, user_leds => user_leds, tcds_frontpanel_a_tx_p => tcds_frontpanel_a_tx_p, tcds_frontpanel_a_tx_n => tcds_frontpanel_a_tx_n, tcds_frontpanel_a_rx_p => tcds_frontpanel_a_rx_p, tcds_frontpanel_a_rx_n => tcds_frontpanel_a_rx_n, -- tcds_frontpanel_b_tx_p => tcds_frontpanel_b_tx_p, tcds_frontpanel_b_tx_n => tcds_frontpanel_b_tx_n, tcds_frontpanel_b_rx_p => tcds_frontpanel_b_rx_p, tcds_frontpanel_b_rx_n => tcds_frontpanel_b_rx_n, tcds_daq_fpga_tx_p => tcds_daq_fpga_tx_p, tcds_daq_fpga_tx_n => tcds_daq_fpga_tx_n, tcds_daq_fpga_rx_p => tcds_daq_fpga_rx_p, tcds_daq_fpga_rx_n => tcds_daq_fpga_rx_n, tcds_backplane_slot2_tx_p => tcds_backplane_slot2_tx_p, tcds_backplane_slot2_tx_n => tcds_backplane_slot2_tx_n, tcds_backplane_slot2_rx_p => tcds_backplane_slot2_rx_p, tcds_backplane_slot2_rx_n => tcds_backplane_slot2_rx_n, -- tcds_backplane_slot3_tx_p => tcds_backplane_slot3_tx_p, tcds_backplane_slot3_tx_n => tcds_backplane_slot3_tx_n, tcds_backplane_slot3_rx_p => tcds_backplane_slot3_rx_p, tcds_backplane_slot3_rx_n => tcds_backplane_slot3_rx_n, -- tcds_backplane_slot4_tx_p => tcds_backplane_slot4_tx_p, tcds_backplane_slot4_tx_n => tcds_backplane_slot4_tx_n, tcds_backplane_slot4_rx_p => tcds_backplane_slot4_rx_p, tcds_backplane_slot4_rx_n => tcds_backplane_slot4_rx_n, -- tcds_backplane_slot5_tx_p => tcds_backplane_slot5_tx_p, tcds_backplane_slot5_tx_n => tcds_backplane_slot5_tx_n, tcds_backplane_slot5_rx_p => tcds_backplane_slot5_rx_p, tcds_backplane_slot5_rx_n => tcds_backplane_slot5_rx_n, -- tcds_backplane_slot6_tx_p => tcds_backplane_slot6_tx_p, tcds_backplane_slot6_tx_n => tcds_backplane_slot6_tx_n, tcds_backplane_slot6_rx_p => tcds_backplane_slot6_rx_p, tcds_backplane_slot6_rx_n => tcds_backplane_slot6_rx_n, -- tcds_backplane_slot7_tx_p => tcds_backplane_slot7_tx_p, tcds_backplane_slot7_tx_n => tcds_backplane_slot7_tx_n, tcds_backplane_slot7_rx_p => tcds_backplane_slot7_rx_p, tcds_backplane_slot7_rx_n => tcds_backplane_slot7_rx_n, -- tcds_backplane_slot8_tx_p => tcds_backplane_slot8_tx_p, tcds_backplane_slot8_tx_n => tcds_backplane_slot8_tx_n, tcds_backplane_slot8_rx_p => tcds_backplane_slot8_rx_p, tcds_backplane_slot8_rx_n => tcds_backplane_slot8_rx_n, -- tcds_backplane_slot9_tx_p => tcds_backplane_slot9_tx_p, tcds_backplane_slot9_tx_n => tcds_backplane_slot9_tx_n, tcds_backplane_slot9_rx_p => tcds_backplane_slot9_rx_p, tcds_backplane_slot9_rx_n => tcds_backplane_slot9_rx_n, -- tcds_backplane_slot10_tx_p => tcds_backplane_slot10_tx_p, tcds_backplane_slot10_tx_n => tcds_backplane_slot10_tx_n, tcds_backplane_slot10_rx_p => tcds_backplane_slot10_rx_p, tcds_backplane_slot10_rx_n => tcds_backplane_slot10_rx_n, -- tcds_backplane_slot11_tx_p => tcds_backplane_slot11_tx_p, tcds_backplane_slot11_tx_n => tcds_backplane_slot11_tx_n, tcds_backplane_slot11_rx_p => tcds_backplane_slot11_rx_p, tcds_backplane_slot11_rx_n => tcds_backplane_slot11_rx_n, -- tcds_backplane_slot12_tx_p => tcds_backplane_slot12_tx_p, tcds_backplane_slot12_tx_n => tcds_backplane_slot12_tx_n, tcds_backplane_slot12_rx_p => tcds_backplane_slot12_rx_p, tcds_backplane_slot12_rx_n => tcds_backplane_slot12_rx_n, -- tcds_backplane_slot13_tx_p => tcds_backplane_slot13_tx_p, tcds_backplane_slot13_tx_n => tcds_backplane_slot13_tx_n, tcds_backplane_slot13_rx_p => tcds_backplane_slot13_rx_p, tcds_backplane_slot13_rx_n => tcds_backplane_slot13_rx_n, -- tcds_backplane_slot14_tx_p => tcds_backplane_slot14_tx_p, tcds_backplane_slot14_tx_n => tcds_backplane_slot14_tx_n, tcds_backplane_slot14_rx_p => tcds_backplane_slot14_rx_p, tcds_backplane_slot14_rx_n => tcds_backplane_slot14_rx_n ); end rtl; --======================================================================