--======================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.ipbus.all;
use work.ipbus_reg_types.all;

use work.dth_tcds_infra_status.all;
use work.ipbus_decode_dth_tcds_sys_main.all;

--==================================================

entity dth_tcds_sys_main is
  port (
    clk_ipb : in std_logic;
    rst_ipb : in std_logic;
    ipb_in : in ipb_wbus;
    ipb_out : out ipb_rbus;
    clk_aux : in std_logic;
    rst_aux : in std_logic;
    nuke : out std_logic;
    soft_rst : out std_logic;

    -- Status summary from the board infrastructure.
    infra_status : in dth_tcds_infra_status;

    -- Xilinx SysMon I2C interface.
    -- NOTE: This is a slave.
    i2c_sysmon_scl : in std_logic;
    i2c_sysmon_sda : in std_logic;

    -- All I2C buses (i.e., masters).
    i2c_eeprom_scl : out std_logic;
    i2c_eeprom_sda : inout std_logic;
    i2c_clks_scl : out std_logic;
    i2c_clks_sda : inout std_logic;
    i2c_optics_scl : out std_logic;
    i2c_optics_sda : inout std_logic;

    -- Flash interface.
    -- NOTE: This is a 16-bit interface, but the bottom four bits are
    -- governed under the hood by the STARTUPE3 primitive (which rules
    -- the FPGA configuration) pins.
    flash_data : inout std_logic_vector(15 downto 4);
    flash_add : out std_logic_vector(25 downto 0);
    flash_oen : out std_logic;
    flash_wen : out std_logic;

    -- General purpose clock generator (IC51) reset and status lines.
    clkgen_gp_reset_b : out std_logic;
    clkgen_gp_intr_b : in std_logic;
    clkgen_gp_lol_b : in std_logic;
    clkgen_gp_los_b : in std_logic;

    -- Master clock generator (IC50) reset, control, and status lines.
    clkgen_master_reset_b : out std_logic;
    clkgen_master_in_sel : out std_logic_vector(1 downto 0);
    clkgen_master_intr_b : in std_logic;
    clkgen_master_lol_b : in std_logic;

    -- Secondary clock generator (IC40) reset, control, and status lines.
    clkgen_secondary_reset_b : out std_logic;
    clkgen_secondary_in_sel : out std_logic_vector(1 downto 0);
    clkgen_secondary_intr_b : in std_logic;
    clkgen_secondary_lol_b : in std_logic;

    -- Backplane clock generators (IC55 and IC53) reset and control lines.
    clkgen_backplane_lo_reset_b : out std_logic;
    clkgen_backplane_lo_in_sel : out std_logic_vector(1 downto 0);
    clkgen_backplane_lo_intr_b : in std_logic;
    clkgen_backplane_lo_lol_b : in std_logic;
    clkgen_backplane_hi_reset_b : out std_logic;
    clkgen_backplane_hi_in_sel : out std_logic_vector(1 downto 0);
    clkgen_backplane_hi_intr_b : in std_logic;
    clkgen_backplane_hi_lol_b : in std_logic;

    -- MGT reference clocks generator (IC41) reset and control lines.
    clkgen_mgt_refs_reset_b : out std_logic;
    clkgen_mgt_refs_in_sel : out std_logic_vector(1 downto 0);
    clkgen_mgt_refs_intr_b : in std_logic;
    clkgen_mgt_refs_lol_b : in std_logic;

    -- Front-panel clock input SFP control and monitoring.
    sfp_clk_frontpanel_modabs : in std_logic;
    sfp_clk_frontpanel_los : in std_logic;
    sfp_clk_frontpanel_txfault : in std_logic;
    sfp_clk_frontpanel_disable : out std_logic;

    -- Front-panel TCDS SFPs.
    sfp_tcds_frontpanel_a_modabs : in std_logic;
    sfp_tcds_frontpanel_a_los : in std_logic;
    sfp_tcds_frontpanel_a_txfault : in std_logic;
    sfp_tcds_frontpanel_a_disable : out std_logic;
    --
    sfp_tcds_frontpanel_b_modabs : in std_logic;
    sfp_tcds_frontpanel_b_los : in std_logic;
    sfp_tcds_frontpanel_b_txfault : in std_logic;
    sfp_tcds_frontpanel_b_disable : out std_logic
  );

end dth_tcds_sys_main;

--==================================================

architecture rtl of dth_tcds_sys_main is

  -- IPBus read/write buses.
  signal ipbw : ipb_wbus_array(N_SLAVES - 1 downto 0);
  signal ipbr : ipb_rbus_array(N_SLAVES - 1 downto 0);

  -- Resets etc.
  signal nuke_i : std_logic;
  signal soft_rst_i : std_logic;

  -- Some helper signals to tri-state the I2C SDA lines.
  signal i2c_eeprom_sda_o : std_logic;
  signal i2c_clks_sda_o : std_logic;
  signal i2c_optics_sda_o : std_logic;

  signal ctrl_general : ipb_reg_v(0 downto 0);
  signal stat_general : ipb_reg_v(0 downto 0);
  signal ctrl_clocks : ipb_reg_v(5 downto 0);
  --signal stat_clocks : ipb_reg_v(0 downto 0);
  signal ctrl_sfps : ipb_reg_v(0 downto 0);
  signal stat_sfps : ipb_reg_v(0 downto 0);

  -- Clock generator reset lines.
  signal reset_all_clock_generators : std_logic;
  signal clkgen_gp_reset_i : std_logic;
  signal clkgen_master_reset_i : std_logic;
  signal clkgen_secondary_reset_i : std_logic;
  signal clkgen_backplane_lo_reset_i : std_logic;
  signal clkgen_backplane_hi_reset_i : std_logic;
  signal clkgen_mgt_refs_reset_i : std_logic;

  -- We need a dummy signal to 'mask' some of the flash access
  -- lines. Those lines are governed by the STARTUPE3 primitive
  -- directly.
  signal flash_dummy : std_logic_vector(31 downto 0);

begin

  ------------------------------------------
  -- IPBus address decoder.
  ------------------------------------------

  fabric : entity work.ipbus_fabric_sel
    generic map (
      NSLV      => N_SLAVES,
      SEL_WIDTH => IPBUS_SEL_WIDTH
    )
    port map (
      ipb_in          => ipb_in,
      ipb_out         => ipb_out,
      sel             => ipbus_sel_dth_tcds_sys_main(ipb_in.ipb_addr),
      ipb_to_slaves   => ipbw,
      ipb_from_slaves => ipbr
    );

  ------------------------------------------
  -- Board, system, and firmware identifiers, and build date.
  ------------------------------------------

  identifier : entity work.board_and_fw_id
    port map (
      ipb_in  => ipbw(N_SLV_ID),
      ipb_out => ipbr(N_SLV_ID)
    );

  ------------------------------------------
  -- Device/FPGA DNA/identifier.
  ------------------------------------------

  dna : entity work.ipbus_device_dna_us_usp
    port map (
      clk => clk_ipb,
      rst => rst_ipb,
      ipb_in  => ipbw(N_SLV_DNA),
      ipb_out => ipbr(N_SLV_DNA)
    );

  ------------------------------------------
  -- Programmatic FPGA reconfiguration access (ICAP interface).
  ------------------------------------------

  icap : entity work.ipbus_icap_us_usp
    port map (
      clk => clk_ipb,
      rst => rst_ipb,
      ipb_in => ipbw(N_SLV_ICAP),
      ipb_out => ipbr(N_SLV_ICAP)
    );

  ------------------------------------------
  -- Flash/PROM access.
  ------------------------------------------

  flash_interface : entity work.dth_flash_interface
    port map (
      clk => clk_ipb,
      rst => rst_ipb,
      ipb_in => ipbw(N_SLV_FLASH_INTERFACE),
      ipb_out => ipbr(N_SLV_FLASH_INTERFACE),

      axi_aclk => clk_ipb,

      flash_data => flash_data,
      flash_add(0) => flash_dummy(0),
      flash_add(26 downto 1) => flash_add,
      flash_add(31 downto 27) => flash_dummy(31 downto 27),
      flash_oen => flash_oen,
      flash_wen => flash_wen
    );

  ------------------------------------------
  -- Xilinx system monitor (I2C slave).
  ------------------------------------------

  sysmon : entity work.ipbus_sysmon_usp
    port map (
      clk     => clk_ipb,
      rst     => rst_ipb,
      ipb_in  => ipbw(N_SLV_SYSMON),
      ipb_out => ipbr(N_SLV_SYSMON),
      i2c_scl => i2c_sysmon_scl,
      i2c_sda => i2c_sysmon_sda
    );

  ------------------------------------------
  -- Several I2C masters.
  ------------------------------------------

  i2c_eeprom : entity work.ipbus_i2c_master
    port map (
      clk => clk_ipb,
      rst => rst_ipb,
      ipb_in => ipbw(N_SLV_I2C_EEPROM),
      ipb_out => ipbr(N_SLV_I2C_EEPROM),
      scl => i2c_eeprom_scl,
      sda_i => i2c_eeprom_sda,
      sda_o => i2c_eeprom_sda_o
    );

  i2c_eeprom_sda <= '0' when i2c_eeprom_sda_o = '0' else 'Z';

  i2c_clks : entity work.ipbus_i2c_master
    port map (
      clk => clk_ipb,
      rst => rst_ipb,
      ipb_in => ipbw(N_SLV_I2C_CLKS),
      ipb_out => ipbr(N_SLV_I2C_CLKS),
      scl => i2c_clks_scl,
      sda_i => i2c_clks_sda,
      sda_o => i2c_clks_sda_o
    );

  i2c_clks_sda <= '0' when i2c_clks_sda_o = '0' else 'Z';

  i2c_optics : entity work.ipbus_i2c_master
    port map (
      clk => clk_ipb,
      rst => rst_ipb,
      ipb_in => ipbw(N_SLV_I2C_OPTICS),
      ipb_out => ipbr(N_SLV_I2C_OPTICS),
      scl => i2c_optics_scl,
      sda_i => i2c_optics_sda,
      sda_o => i2c_optics_sda_o
    );

  i2c_optics_sda <= '0' when i2c_optics_sda_o = '0' else 'Z';

  ------------------------------------------
  -- General-purpose control and status registers.
  ------------------------------------------

  csr_general : entity work.ipbus_ctrlreg_v
    generic map (
      N_CTRL => 1,
      N_STAT => 1
    )
    port map (
      clk       => clk_ipb,
      reset     => rst_ipb,
      ipbus_in  => ipbw(N_SLV_CSR_GENERAL),
      ipbus_out => ipbr(N_SLV_CSR_GENERAL),
      q         => ctrl_general,
      d         => stat_general
    );

  soft_rst_i <= ctrl_general(0)(0);
  nuke_i <= ctrl_general(0)(1);

  ------------------------------------------
  -- Clocking control and status registers.
  ------------------------------------------

  csr_clocks : entity work.ipbus_ctrlreg_v
    generic map (
      N_CTRL => 6,
      N_STAT => 1
    )
    port map (
      clk       => clk_ipb,
      reset     => rst_ipb,
      ipbus_in  => ipbw(N_SLV_CSR_CLOCKS),
      ipbus_out => ipbr(N_SLV_CSR_CLOCKS),
      q         => ctrl_clocks,
      d         => open --stat_clocks,
    );

  clkgen_gp_reset_i <= ctrl_clocks(0)(0);

  clkgen_master_reset_i <= ctrl_clocks(1)(0);
  clkgen_master_in_sel  <= ctrl_clocks(1)(3 downto 2);

  clkgen_secondary_reset_i <= ctrl_clocks(2)(0);
  clkgen_secondary_in_sel  <= ctrl_clocks(2)(3 downto 2);

  clkgen_backplane_lo_reset_i <= ctrl_clocks(3)(0);
  clkgen_backplane_lo_in_sel  <= ctrl_clocks(3)(3 downto 2);

  clkgen_backplane_hi_reset_i <= ctrl_clocks(4)(0);
  clkgen_backplane_hi_in_sel  <= ctrl_clocks(4)(3 downto 2);

  clkgen_mgt_refs_reset_i <= ctrl_clocks(5)(0);
  clkgen_mgt_refs_in_sel  <= ctrl_clocks(5)(3 downto 2);

  ------------------------------------------
  -- Control and status of front-panel SFPs.
  ------------------------------------------

  csr_sfps : entity work.ipbus_ctrlreg_v
    generic map (
      N_CTRL => 1,
      N_STAT => 1
    )
    port map (
      clk       => clk_ipb,
      reset     => rst_ipb,
      ipbus_in  => ipbw(N_SLV_CSR_SFPS),
      ipbus_out => ipbr(N_SLV_CSR_SFPS),
      q         => ctrl_sfps,
      d         => stat_sfps
    );

  -- NOTE: The SFPs are enabled when these signals are pulled low. So
  -- we'll invert these here and call the registers 'enable'.
  sfp_clk_frontpanel_disable <= not ctrl_sfps(0)(0);
  sfp_tcds_frontpanel_a_disable <= not ctrl_sfps(0)(1);
  sfp_tcds_frontpanel_b_disable <= not ctrl_sfps(0)(2);

  stat_sfps(0)(0) <= sfp_clk_frontpanel_modabs;
  stat_sfps(0)(1) <= sfp_clk_frontpanel_los;
  stat_sfps(0)(2) <= sfp_clk_frontpanel_txfault;

  stat_sfps(0)(4) <= sfp_tcds_frontpanel_a_modabs;
  stat_sfps(0)(5) <= sfp_tcds_frontpanel_a_los;
  stat_sfps(0)(6) <= sfp_tcds_frontpanel_a_txfault;

  stat_sfps(0)(8) <= sfp_tcds_frontpanel_b_modabs;
  stat_sfps(0)(9) <= sfp_tcds_frontpanel_b_los;
  stat_sfps(0)(10) <= sfp_tcds_frontpanel_b_txfault;

  ------------------------------------------

  -- A nuke resets all clock generators to their default settings.
  reset_all_clock_generators <= nuke_i;

  clkgen_gp_reset_b <= not (reset_all_clock_generators or clkgen_gp_reset_i);
  clkgen_master_reset_b <= not (reset_all_clock_generators or clkgen_master_reset_i);
  clkgen_secondary_reset_b <= not (reset_all_clock_generators or clkgen_secondary_reset_i);
  clkgen_backplane_lo_reset_b <= not (reset_all_clock_generators or clkgen_backplane_lo_reset_i);
  clkgen_backplane_hi_reset_b <= not (reset_all_clock_generators or clkgen_backplane_hi_reset_i);
  clkgen_mgt_refs_reset_b <= not (reset_all_clock_generators or clkgen_mgt_refs_reset_i);

  ------------------------------------------

  nuke <= nuke_i;
  soft_rst <= soft_rst_i;

end rtl;

--======================================================================