Altium

Design Rule Verification Report

Date: 1/24/2021
Time: 10:11:58 AM
Elapsed Time: 00:00:01
Filename: D:\projects\ETL_RB_adapter\adapter.PcbDoc
Warnings: 0
Rule Violations: 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=0.2mm) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=0.152mm) (Max=0.254mm) (Preferred=0.152mm) (All) 0
SMD Entry (Side = Not Allowed) (Corner = Not Allowed) (Any Angle = Not Allowed) (Ignore First Corner = Allowed) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.381mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Hole Size Constraint (Min=0.025mm) (Max=5.08mm) (All) 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.12mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.04mm) (IsPad),(IsVia) 0
Silk To Solder Mask (Clearance=0.15mm) (IsPad),(All) 0
Silk to Silk (Clearance=0.254mm) (All),(All) 0
Net Antennae (Tolerance=0mm) (All) 0
Room emu_adapter (Bounding Region = (47.2mm, 40.25mm, 95.6mm, 152.25mm) (InComponentClass('emu_adapter')) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Total 0