Answers to Nimal's email on Oct.1st are as following:

Few things I like to share on DFM,

 

    1.You are looking for 1 Oz Cu for the Outer Layers, now we have min of 3 mil spacing we cannot improve because of BGA, for this Cu thickness will be 0.5 Oz + Plating, please update in your stack-up.
changed to 1/2 Ox
    2.In the inner Plane layer (Negative) can you increase split from 6 mil to 10 mil. (your recommendation is 1 Oz for plane layer)(DUT – BGA area you can have it 6 mil)
Done
    3.Example for IC6 and IC5 you have thermal pad and Via, can you increase the distance to 10 mil between drill – it should be drill wall to drill wall 10 mil.
Done
    4.For any Via do you need plugging? If so please specify in fab note.
None
    5.Try to maintain mask to mask spacing (that is mask dam) as 5 mil – min of 4 mil recommended for Green mask.
minimum is 4mil now. For P5-P10 and IC5-7 the solder mask expansion has to be reduced to 1.5mil
    6.If you have any standard fab note please add it.
The fab note is ETL_RB_v1.5.GM14
    7.We need IPC file in the package for net compare.
Included
    8.Add particular detail for impedance in fab note.
Done. Please give us the final trace width used for those controlled impedance traces. Impedance requirement
only applies to trace width of 0.12mm part of the signal. Keep trace width other than 0.12mm unchanged.
    9.Any drill to copper please improve it more than 6 mil – inner layers.
It is 6mil now, can't increase further.