| Rule Violations |
Count |
| Clearance Constraint (Gap=0.076mm) (All),(All) |
0 |
| Short-Circuit Constraint (Allowed=No) (All),(All) |
0 |
| Un-Routed Net Constraint ( (All) ) |
0 |
| Modified Polygon (Allow modified: No), (Allow shelved: No) |
0 |
| Width Constraint (Min=0.076mm) (Max=2.54mm) (Preferred=0.12mm) (All) |
0 |
| Width Constraint (Min=0.076mm) (Max=0.13mm) (Preferred=0.12mm) (InNetClass('HS')) |
0 |
| Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) |
0 |
| Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) |
0 |
| Hole To Hole Clearance (Gap=0.254mm) (All),(All) |
0 |
| Hole To Hole Clearance (Gap=0.15mm) (InNet('GND') or InNet('LV_RB') or InNet('1V5A') or InNet('1V5D') or InNet('1V2A') or InNet('1V2B') or InNet('1V2C') or InNet('1V2D')),(InNet('GND') or InNet('LV_RB') or InNet('1V5A') or InNet('1V5D') or InNet('1V2A') or InNet('1V2B') or InNet('1V2C') or InNet('1V2D')) |
0 |
| Minimum Solder Mask Sliver (Gap=0.102mm) (All),(All) |
0 |
| Silk To Solder Mask (Clearance=0.025mm) (IsPad),(All) |
0 |
| Silk to Silk (Clearance=0.025mm) (All),(All) |
0 |
| Net Antennae (Tolerance=0mm) (All) |
0 |
| Room lpGBT (Bounding Region = (222mm, 21.5mm, 1077mm, 56.5mm) (Disabled)(InComponentClass('lpGBT')) |
0 |
| Room WP7B (Bounding Region = (222.75mm, 75.05mm, 643.75mm, 105.05mm) (Disabled)(InComponentClass('WP7B')) |
0 |
| Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (Disabled)(All) |
0 |
| Total |
0 |
