| Device Utilization Summary | [-] |
| Slice Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Registers |
6,154 |
54,576 |
11% |
|
| Number used as Flip Flops |
6,150 |
|
|
|
| Number used as Latches |
4 |
|
|
|
| Number used as Latch-thrus |
0 |
|
|
|
| Number used as AND/OR logics |
0 |
|
|
|
| Number of Slice LUTs |
5,346 |
27,288 |
19% |
|
| Number used as logic |
4,818 |
27,288 |
17% |
|
| Number using O6 output only |
2,957 |
|
|
|
| Number using O5 output only |
524 |
|
|
|
| Number using O5 and O6 |
1,337 |
|
|
|
| Number used as ROM |
0 |
|
|
|
| Number used as Memory |
167 |
6,408 |
2% |
|
| Number used as Dual Port RAM |
18 |
|
|
|
| Number using O6 output only |
2 |
|
|
|
| Number using O5 output only |
0 |
|
|
|
| Number using O5 and O6 |
16 |
|
|
|
| Number used as Single Port RAM |
0 |
|
|
|
| Number used as Shift Register |
149 |
|
|
|
| Number using O6 output only |
141 |
|
|
|
| Number using O5 output only |
0 |
|
|
|
| Number using O5 and O6 |
8 |
|
|
|
| Number used exclusively as route-thrus |
361 |
|
|
|
| Number with same-slice register load |
320 |
|
|
|
| Number with same-slice carry load |
41 |
|
|
|
| Number with other load |
0 |
|
|
|
| Number of occupied Slices |
2,064 |
6,822 |
30% |
|
| Number of MUXCYs used |
1,000 |
13,644 |
7% |
|
| Number of LUT Flip Flop pairs used |
6,508 |
|
|
|
| Number with an unused Flip Flop |
1,428 |
6,508 |
21% |
|
| Number with an unused LUT |
1,162 |
6,508 |
17% |
|
| Number of fully used LUT-FF pairs |
3,918 |
6,508 |
60% |
|
| Number of unique control sets |
212 |
|
|
|
Number of slice register sites lost
to control set restrictions |
535 |
54,576 |
1% |
|
| Number of bonded IOBs |
113 |
296 |
38% |
|
| Number of LOCed IOBs |
83 |
113 |
73% |
|
| IOB Flip Flops |
32 |
|
|
|
| IOB Master Pads |
13 |
|
|
|
| IOB Slave Pads |
13 |
|
|
|
| Number of bonded IPADs |
6 |
16 |
37% |
|
| Number of LOCed IPADs |
6 |
6 |
100% |
|
| Number of bonded OPADs |
4 |
8 |
50% |
|
| Number of LOCed OPADs |
4 |
4 |
100% |
|
| Number of RAMB16BWERs |
41 |
116 |
35% |
|
| Number of RAMB8BWERs |
1 |
232 |
1% |
|
| Number of BUFIO2/BUFIO2_2CLKs |
6 |
32 |
18% |
|
| Number used as BUFIO2s |
6 |
|
|
|
| Number used as BUFIO2_2CLKs |
0 |
|
|
|
| Number of BUFIO2FB/BUFIO2FB_2CLKs |
5 |
32 |
15% |
|
| Number used as BUFIO2FBs |
5 |
|
|
|
| Number used as BUFIO2FB_2CLKs |
0 |
|
|
|
| Number of BUFG/BUFGMUXs |
14 |
16 |
87% |
|
| Number used as BUFGs |
12 |
|
|
|
| Number used as BUFGMUX |
2 |
|
|
|
| Number of DCM/DCM_CLKGENs |
5 |
8 |
62% |
|
| Number used as DCMs |
5 |
|
|
|
| Number used as DCM_CLKGENs |
0 |
|
|
|
| Number of ILOGIC2/ISERDES2s |
4 |
376 |
1% |
|
| Number used as ILOGIC2s |
4 |
|
|
|
| Number used as ISERDES2s |
0 |
|
|
|
| Number of IODELAY2/IODRP2/IODRP2_MCBs |
0 |
376 |
0% |
|
| Number of OLOGIC2/OSERDES2s |
16 |
376 |
4% |
|
| Number used as OLOGIC2s |
16 |
|
|
|
| Number used as OSERDES2s |
0 |
|
|
|
| Number of BSCANs |
0 |
4 |
0% |
|
| Number of BUFHs |
0 |
256 |
0% |
|
| Number of BUFPLLs |
0 |
8 |
0% |
|
| Number of BUFPLL_MCBs |
0 |
4 |
0% |
|
| Number of DSP48A1s |
0 |
58 |
0% |
|
| Number of GTPA1_DUALs |
1 |
2 |
50% |
|
| Number of ICAPs |
1 |
1 |
100% |
|
| Number of MCBs |
0 |
2 |
0% |
|
| Number of PCIE_A1s |
0 |
1 |
0% |
|
| Number of PCILOGICSEs |
0 |
2 |
0% |
|
| Number of PLL_ADVs |
1 |
4 |
25% |
|
| Number of PMVs |
0 |
1 |
0% |
|
| Number of STARTUPs |
0 |
1 |
0% |
|
| Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
| Number of RPM macros |
1 |
|
|
|
| Average Fanout of Non-Clock Nets |
3.09 |
|
|
|