AMC13_T2 Project Status (12/05/2020 - 04:05:28)
Project File: T2New.xise Parser Errors: No Errors
Module Name: AMC13_T2 Implementation State: Programming File Generated
Target Device: xc6slx45t-2fgg484
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
1288 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [+]
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat Dec 5 19:23:41 202001025 Warnings (0 new)49 Infos (0 new)
Translation ReportCurrentSat Dec 5 19:24:23 20200242 Warnings (0 new)7 Infos (0 new)
Map ReportCurrentSat Dec 5 19:34:28 202008 Warnings (0 new)315 Infos (0 new)
Place and Route ReportCurrentSat Dec 5 19:39:29 202006 Warnings (0 new)0
Power Report     
Post-PAR Static Timing ReportCurrentSat Dec 5 19:40:18 2020003 Infos (0 new)
Bitgen ReportCurrentSat Dec 5 19:41:48 202007 Warnings (0 new)2 Infos (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateSat Dec 5 01:02:28 2020
Physical Synthesis ReportCurrentSat Dec 5 19:34:28 2020
WebTalk Log FileCurrentSat Dec 5 19:41:53 2020

Date Generated: 04/16/2021 - 14:13:01