##############################################################
#
# Vivado 2015.1
# Date: Tue Jun 23 13:46:55 2015
#
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#
#  This file contains the customisation parameters for a
#  Xilinx IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
# BEGIN Project Options
SET addpads=false
SET asysymbol=true
SET busformat=BusFormatAngleBracketNotRipped
SET createndf=false
SET designentry=VHDL
SET device=xc7k325t
SET devicefamily=kintex7
SET flowvendor=Other
SET formalverification=false
SET foundationsym=false
SET implementationfiletype=Ngc
SET package=ffg900
SET removerpms=false
SET simulationfiles=Behavioral
SET speedgrade=-2
SET verilogsim=false
SET vhdlsim=true
# END Project Options
# BEGIN Select
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET asynchronous_input_port_width=192
CSET asynchronous_output_port_width=16
CSET component_name=vio_i192_o16
CSET constraint_type=external
CSET enable_asynchronous_input_port=true
CSET enable_asynchronous_output_port=true
CSET enable_synchronous_input_port=false
CSET enable_synchronous_output_port=false
CSET example_design=false
CSET invert_clock_input=false
CSET synchronous_input_port_width=8
CSET synchronous_output_port_width=8
# END Parameters
GENERATE