----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:01:22 10/08/2013 
-- Design Name: 
-- Module Name:    FIFO72x8192 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
Library UNIMACRO;
use UNIMACRO.vcomponents.all;

entity FIFO66x2048 is
		generic(ALMOSTFULL_OFFSET : bit_vector(15 downto 0) := x"0080";ALMOSTEMPTY_OFFSET : bit_vector(15 downto 0) := x"0080");
    Port ( wclk : in  STD_LOGIC;
           rclk : in  STD_LOGIC;
           fifo_rst : in  STD_LOGIC;
           fifo_en : in  STD_LOGIC;
           di : in  STD_LOGIC_VECTOR (65 downto 0);
           we : in  STD_LOGIC;
           re : in  STD_LOGIC;
           do : out  STD_LOGIC_VECTOR (65 downto 0);
           full : out  STD_LOGIC;
           empty : out  STD_LOGIC;
           data_avl : out  STD_LOGIC);
end FIFO66x2048;

architecture Behavioral of FIFO66x2048 is
signal fifo_re : std_logic := '0';
signal fifo_we : std_logic := '0';
signal wait_time : std_logic_vector(3 downto 0) := (others => '0');
signal dip : std_logic_vector(71 downto 0) := (others => '0');
signal dop : std_logic_vector(71 downto 0) := (others => '0');
signal fifo_empty : std_logic_vector(7 downto 0) := (others => '0');
signal fifo_Almostempty : std_logic_vector(7 downto 0) := (others => '0');
signal fifo_full : std_logic_vector(7 downto 0) := (others => '0');
type array8X12 is array (0 to 7) of std_logic_vector(11 downto 0);
signal rdcount : array8X12 := (others => (others => '0'));
signal wrcount : array8X12 := (others => (others => '0'));

begin
dip(65 downto 0) <= di;
do <= dop(65 downto 0);
g_FIFO: for i in 0 to 7 generate
   i_FIFO : FIFO_DUALCLOCK_MACRO
   generic map (
      DEVICE => "7SERIES",            -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES" 
      ALMOST_FULL_OFFSET => ALMOSTFULL_OFFSET,  -- Sets almost full threshold
      ALMOST_EMPTY_OFFSET => ALMOSTEMPTY_OFFSET, -- Sets the almost empty threshold
      DATA_WIDTH => 9,   -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
      FIFO_SIZE => "36Kb",            -- Target BRAM, "18Kb" or "36Kb" 
      FIRST_WORD_FALL_THROUGH => TRUE) -- Sets the FIFO FWFT to TRUE or FALSE
   port map (
      ALMOSTEMPTY => fifo_Almostempty(i),   -- 1-bit output almost empty
      ALMOSTFULL => FIFO_full(i),     -- 1-bit output almost full
      DO => dop(i*9+8 downto i*9),                     -- Output data, width defined by DATA_WIDTH parameter
      EMPTY => fifo_empty(i),               -- 1-bit output empty
      FULL => open,                 -- 1-bit output full
      RDCOUNT => rdcount(i),           -- Output read count, width determined by FIFO depth
      RDERR => open,               -- 1-bit output read error
      WRCOUNT => wrcount(i),           -- Output write count, width determined by FIFO depth
      WRERR => open,               -- 1-bit output write error
      DI => dip(i*9+8 downto i*9),                     -- Input data, width defined by DATA_WIDTH parameter
      RDCLK => rclk,               -- 1-bit input read clock
      RDEN => FIFO_re,                 -- 1-bit input read enable
      RST => fifo_rst,                   -- 1-bit input reset
      WRCLK => wclk,               -- 1-bit input write clock
      WREN => FIFO_we                  -- 1-bit input write enable
   );
end generate;
FIFO_we <= FIFO_en and we;
FIFO_re <= FIFO_en and re;
full <= FIFO_full(0);
empty <= FIFO_empty(0);
data_avl <= not fifo_Almostempty(0);
--process(rclk)
--begin
--	if(rclk'event and rclk = '1')then
--		if(FIFO_empty(0) = '1' or wait_time(3) = '1')then
--			data_avl <= '0';
--		else
--			data_avl <= '1';
--		end if;
--		if(fifo_Almostempty(0) = '1' and wait_time(3) = '0')then
--			wait_time <= "1111";
--		else
--			wait_time <= wait_time(2 downto 0) & '0';
--		end if;
--	end if;
--end process;
--data_avl <= not FIFO_empty(0);
end Behavioral;