----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:26:45 09/25/2013 
-- Design Name: 
-- Module Name:    chipscope - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_misc.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
Library UNIMACRO;
use UNIMACRO.vcomponents.all;

entity chipscope is
		generic (N : integer := 5);
    Port ( clka : in  STD_LOGIC;
           clkb : in  STD_LOGIC;
           ina : in  STD_LOGIC_VECTOR (135 downto 0);
           inb : in  STD_LOGIC_VECTOR (135 downto 0));
end chipscope;

architecture Behavioral of chipscope is
component ila128x1024
  PORT (
    CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
    CLK : IN STD_LOGIC;
    DATA : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
    TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));

end component;
component ila128x4096
  PORT (
    CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
    CLK : IN STD_LOGIC;
    DATA : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
    TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));

end component;
component icon2
  PORT (
    CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
    CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));

end component;
signal DATAa : std_logic_vector(127 downto 0);
signal DATAb : std_logic_vector(127 downto 0);
signal TRIG0 : std_logic_vector(7 downto 0);
signal TRIG1 : std_logic_vector(7 downto 0);
signal RDADDRa : std_logic_vector(8 downto 0) := (others => '0');
signal RDADDRb : std_logic_vector(8 downto 0) := (others => '0');
signal WRADDRa : std_logic_vector(8 downto 0);
signal WRADDRb : std_logic_vector(8 downto 0);
signal CONTROL0 : std_logic_vector(35 downto 0);
signal CONTROL1 : std_logic_vector(35 downto 0);
signal DIa : std_logic_vector(135 downto 0);
signal DIb : std_logic_vector(135 downto 0);
begin
TRIG0 <= ina(135 downto 128);
TRIG1 <= inb(135 downto 128);
i_icon : icon2
  port map (
    CONTROL0 => CONTROL0,
    CONTROL1 => CONTROL1);
--i_ilaa : ila128x1024
i_ilaa : ila128x4096
  port map (
    CONTROL => CONTROL0,
    CLK => CLKa,
    DATA => DATAa,
    TRIG0 => TRIG0);
--i_ilab : ila128x1024
i_ilab : ila128x4096
  port map (
    CONTROL => CONTROL1,
    CLK => CLKb,
    DATA => DATAb,
    TRIG0 => TRIG1);
g_delaya : for i in 0 to 1 generate
i_delaya : BRAM_SDP_MACRO
   generic map (
      BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb" 
      DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "VIRTEX6, "SPARTAN6" 
      WRITE_WIDTH => 64,   -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
      READ_WIDTH => 64)   -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
   port map (
      DO => DATAa(64*i+63 downto 64*i),         -- Output read data port, width defined by READ_WIDTH parameter
      DI => DIa(64*i+63 downto 64*i),         -- Input write data port, width defined by WRITE_WIDTH parameter
      RDADDR => RDADDRa, -- Input read address, width defined by read port depth
      RDCLK => clka,   -- 1-bit input read clock
      RDEN => '1',     -- 1-bit input read port enable
      REGCE => '1',   -- 1-bit input read output register enable
      RST => '0',       -- 1-bit input reset 
      WE => x"ff",         -- Input write enable, width defined by write port depth
      WRADDR => WRADDRa, -- Input write address, width defined by write port depth
      WRCLK => clka,   -- 1-bit input write clock
      WREN => '1'      -- 1-bit input write port enable
   );
end generate;
g_delayb : for i in 0 to 1 generate
i_delayb : BRAM_SDP_MACRO
   generic map (
      BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb" 
      DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "VIRTEX6, "SPARTAN6" 
      WRITE_WIDTH => 64,   -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
      READ_WIDTH => 64)   -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
   port map (
      DO => DATAb(64*i+63 downto 64*i),         -- Output read data port, width defined by READ_WIDTH parameter
      DI => DIb(64*i+63 downto 64*i),         -- Input write data port, width defined by WRITE_WIDTH parameter
      RDADDR => RDADDRb, -- Input read address, width defined by read port depth
      RDCLK => clkb,   -- 1-bit input read clock
      RDEN => '1',     -- 1-bit input read port enable
      REGCE => '1',   -- 1-bit input read output register enable
      RST => '0',       -- 1-bit input reset 
      WE => x"ff",         -- Input write enable, width defined by write port depth
      WRADDR => WRADDRb, -- Input write address, width defined by write port depth
      WRCLK => clkb,   -- 1-bit input write clock
      WREN => '1'      -- 1-bit input write port enable
   );
end generate;
process(clka)
begin
	if(clka'event and clka = '1')then
		RDADDRa(N downto 0) <= RDADDRa(N downto 0) + 1;
		WRADDRa <= RDADDRa;
		DIa <= ina;
	end if;
end process;
process(clkb)
begin
	if(clkb'event and clkb = '1')then
		RDADDRb(N downto 0) <= RDADDRb(N downto 0) + 1;
		WRADDRb <= RDADDRb;
		DIb <= inb;
	end if;
end process;

end Behavioral;