DTC memory map in bytes 0x1 read only always reads 0x32 0x3 read only FPGA version 0x1 now 0x7 T2 status bit 7 T2 FPGA lock to TTC clock bit 6-4 T2 FPGA DCM status bits 2-0 bit 3-2 always reads 0 bit 1 T3 FPGA INIT_B status bit 0 T3 FPGA DONE status 0x8 command register bit 0 start DTC FPGA reconfiguration bit 1 reconfigure T3 FPGA (must write a 0 back to this bit) bit 2 reset T2 counters bit 7-3 not used 0x9 T2 AMC enable register low (read only) bit 0 enables AMC1 bit 1 enables AMC2 bit 2 enables AMC3 bit 3 enables AMC4 bit 4 enables AMC5 bit 5 enables AMC6 bit 6 enables AMC7 bit 7 enables AMC8 0xa T2 AMC enable register high (read only) bit 0 enables AMC9 bit 1 enables AMC10 bit 2 enables AMC11 bit 3 enables AMC12 0xb T2 serail number 0xc should read 35, reads 25 if T3 FPGA not configured 0xd T3 configuration data CRC[7:0] 0xe T3 configuration data CRC[15:8] 0xf T3 configuration data CRC[23:16] 0x12 T2 last received broadcast command, bit 1-0 always 0 0x13 T2 Bcnt error count 0x14 T2 SingleBit hamming error count 0x15 T2 DoubleBit hamming error count 0x16 T2 event number[7:0] 0x17 T2 event number[15:8] 0x18 T2 last received event number[7:0] 0x19 T2 last received event number[15:8] 0x1a T2 Bcnt[7:0] 0x1b T2 bit 3-0 Bcnt[11:8] 0x1c T2 orbit count[7:0] of last L1A 0x1d T2 orbit count[15:8] of last L1A 0x1e T2 Bcnt[7:0] of last L1A 0x1f T2 bit 3-0 Bcnt[11:8] of last L1A 0x20 T3 read/write test register 0x21 T3 serail number 0x22 T3 FPGA version 0x23 T3 status bit 7 T3 FPGA lock to TTC clock bit 6 clock divider reset signal bit 5-4 always reads 0 bit 3 SFP1 TxFault bit 2 SFP0 TxFault bit 1 TTC signal lost bit 0 TTC clock lock lost 0x24 T3 Bcnt error count 0x25 T3 SingleBit hamming error count 0x26 T3 DoubleBit hamming error count 0x27 T3 last received broadcast command, bit 1-0 always 0 0x28 T3 event number[7:0] 0x29 T3 event number[15:8] 0x2a T3 last received event number[7:0] 0x2b T3 last received event number[15:8] 0x2c T3 Bcnt[7:0] of last L1A 0x2d T3 bit 3-0 Bcnt[11:8] of last L1A 0x2e T3 orbit count[7:0] of last L1A 0x2f T3 orbit count[15:8] of last L1A 0x30 DTC AMC enable register low read/write bit 0 enables AMC1 bit 1 enables AMC2 bit 2 enables AMC3 bit 3 enables AMC4 bit 4 enables AMC5 bit 5 enables AMC6 bit 6 enables AMC7 bit 7 enables AMC8 0x31 DTC AMC enable register high read/write bit 0 enables AMC9 bit 1 enables AMC10 bit 2 enables AMC11 bit 3 enables AMC12 0x32 T3 orbit count[7:0] 0x33 T3 orbit count[15:8] 0x34 debugging only 0x35 T3 Bcnt[7:0] 0x36 T3 bit 3-0 Bcnt[11:8]