U1 ip address fixed as 192.168.1.155(SN = 0x32)
SPI signals are only place holders. If SPI is needed, protocol
needs be defined first. F and D signal outputs require SYNC_CLK which is
output from a coax connector on DSS board and not available on DOSI board. 

0x0	control and status register
	write
	bit 31-7	not used
	bit 6		DSS6_MASTER_RESET
	bit 5		DSS5_MASTER_RESET
	bit 4		DSS4_MASTER_RESET
	bit 3		DSS3_MASTER_RESET
	bit 2		DSS2_MASTER_RESET
	bit 1		DSS1_MASTER_RESET
	bit 0		general reset
	read
	bit 31-16	always 0
	bit 15-0	firmware version

0x1	DSS1 status register Read only
	bit 31-6	not used
	bit 5		SDO
	bit 4		SYNC_SMP_ERR
	bit 3		PLL_LOCK
	bit 2		CIC_OVRFLW
	bit 1		RAM_SWP_OVR
	bit 0		DROVR

0x2	DSS2 status register Read only

0x3	DSS3 status register Read only

0x4	DSS4 status register Read only

0x5	DSS5 status register Read only

0x6	DSS6 status register Read only

0x7	DSS1 output register R/W
	bit 31-29	profile
	bit 28		TX_ENABLE_A
	bit 27		OSK
	bit 26		DRCTL
	bit 25		DRHOLD
	bit 24		SDIO
	bit 23		SCLK
	bit 22		CSB
	bit 21		IO_RESET
	bit 20		EXT_PWR_DWN
	bit 19		LDB
	bit 18		not used
	bit 17-16	F
	bit 15-0	D

0x8	DSS2 output register R/W

0x9	DSS3 output register R/W

0xa	DSS4 output register R/W

0xb	DSS5 output register R/W

0xc	DSS6 output register R/W

0xd	test register R/W
	bit 31-8	not used
	bit 7-0		test signal outputs

U2 ip address fixed as 192.168.1.154
0x0	control and status register
	write
	bit 31-14	not used
	bit 13		start sample ADC
	bit 12		get ready for test pattern
	bit 11-9	not used
	bit 8		reconfigure both U1 and U2
	bit 4		reconfigure both U1
	bit 3		reset ADC input deserializer
	bit 2		reset ADC buffer
	bit 1		not used
	bit 0		general reset
	read
	bit 31-16	firmware version
	bit 15-3	always 0	
	bit 2		SFP TXFault
	bit 1		SFP Loss of Signal
	bit 0		SFP Absent

0x1	FLASH control register R/W
	read 	
	bit 0	FLASH busy
	write	sends data stored in FLASH wbuf to FLASH memory chip
	bit 8-0 specifies number of (clocks/8 -1) to be sent to the FLASH memory
		(depends on the type of the FLASH command and number of bytes to be
		 read or written)

0x3	status register Read only
	read
 	bit 31		U1 INIT_B pin status
	bit 30		U1 DONE pin inverted
	bit 31-0	Don't care

0x8	test register R/W
	bit 13-8	LEDs
	bit 7-0		test pins

0x10	ADC input data delay setting register R/W
	bit 31-24	not used
	bit 23-20	DI(5) delay
	bit 19-16	DI(4) delay
	bit 15-12	DI(3) delay
	bit 11-8	DI(2) delay
	bit 7-4		DI(1) delay
	bit 3-0		DI(0) delay

0x11	ADC input data delay setting register R/W
	bit 31-24	not used
	bit 23-20	DI(11) delay
	bit 19-16	DI(10) delay
	bit 15-12	DI(9) delay
	bit 11-8	DI(8) delay
	bit 7-4		DI(7) delay
	bit 3-0		DI(6) delay

0x12	ADC input data delay setting register R/W
	bit 31-24	not used
	bit 23-20	DID(5) delay
	bit 19-16	DID(4) delay
	bit 15-12	DID(3) delay
	bit 11-8	DID(2) delay
	bit 7-4		DID(1) delay
	bit 3-0		DID(0) delay

0x13	ADC input data delay setting register R/W
	bit 31-24	not used
	bit 23-20	DID(11) delay
	bit 19-16	DID(10) delay
	bit 15-12	DID(9) delay
	bit 11-8	DID(8) delay
	bit 7-4		DID(7) delay
	bit 3-0		DID(6) delay

0x14	ADC input data delay setting register R/W
	bit 31-24	not used
	bit 23-20	DQ(5) delay
	bit 19-16	DQ(4) delay
	bit 15-12	DQ(3) delay
	bit 11-8	DQ(2) delay
	bit 7-4		DQ(1) delay
	bit 3-0		DQ(0) delay

0x15	ADC input data delay setting register R/W
	bit 31-24	not used
	bit 23-20	DQ(11) delay
	bit 19-16	DQ(10) delay
	bit 15-12	DQ(9) delay
	bit 11-8	DQ(8) delay
	bit 7-4		DQ(7) delay
	bit 3-0		DQ(6) delay

0x16	ADC input data delay setting register R/W
	bit 31-24	not used
	bit 23-20	DQD(5) delay
	bit 19-16	DQD(4) delay
	bit 15-12	DQD(3) delay
	bit 11-8	DQD(2) delay
	bit 7-4		DQD(1) delay
	bit 3-0		DQD(0) delay

0x17	ADC input data delay setting register R/W
	bit 31-24	not used
	bit 23-20	DQD(11) delay
	bit 19-16	DQD(10) delay
	bit 15-12	DQD(9) delay
	bit 11-8	DQD(8) delay
	bit 7-4		DQD(7) delay
	bit 3-0		DQD(6) delay

0x18	ADC input data course delay command register write only
	bit 31-4	not used
	bit 3		increase DQD delay
	bit 2		increase DQ delay
	bit 1		increase DID delay
	bit 0		increase DI delay

0x19	pattern status register read only
	bit 31-17	not used
	bit 16		pattern data ready
	bit 15-0	pattern data end pointer in ADC buffer

0x1000 thru 0x107f	read/write	FLASH write buffer
	always write FLASH command(including FLASH address if any) to address 0x1000
	for page write command, attach the write data starting at address 0x1001
	you can read back what you have writen to the write buffer.

0x1080 thru 0x10ff read only	FLASH read buffer
	you read whatever data are returned from the FLASH memory here