Project Statistics |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_Simulator=ISE Simulator (VHDL/Verilog) |
PROP_Top_Level_Module_Type=HDL |
PROP_PreferredLanguage=VHDL |
PROP_Enable_Message_Filtering=false |
PROP_Enable_Incremental_Messaging=false |
PROP_UseSmartGuide=false |
Partitions count=1 |
FILE_UCF=1 |
FILE_VERILOG=1 |
FILE_VHDL=23 |
PROP_xilxMapTimingDrivenPacking=true |
PROPEXT_xilxSynthMaxFanout_virtex2=100 |
PROP_DevDevice=xc3s4000 |
PROP_DevFamily=Spartan3 |
PROP_DevSpeed=-4 |
PROP_FitterReportFormat=HTML |
PROP_ImpactProjectFile=changed |
PROP_MapEffortLevel=High |
PROP_MapLogicOptimization=true |
PROP_MapPowerReduction=true |
PROP_MapRegDuplication=true |
PROP_PreferredLanguage=VHDL |
PROP_SynthOptEffort=High |
PROP_SynthShiftRegExtract=false |
PROP_UserConstraintEditorPreference=Constraints Editor |
PROP_parGenAsyDlyRpt=true |
PROP_parPowerReduction=true |
PROP_xilxBitgStart_Clk_DriveDone=true |
PROP_xilxMapAllowLogicOpt=true |
PROP_xilxMapCoverMode=Speed |
PROP_xilxMapPackRegInto=For Inputs and Outputs |
PROP_xilxMapReportDetail=true |
PROP_xilxNgdbldIOPads=true |
PROP_xilxPAReffortLevel=High |
PROP_xilxPARextraEffortLevel=Normal |
PROP_xilxSynthKeepHierarchy=Yes |
PROP_xstEquivRegRemoval=false |
PROP_xstGenerateRTLNetlist=No |
PROP_xstOptimizeInsPrimtives=true |
Project duration(days)=394 |