dcol Project Status (10/06/2009 - 15:10:17)
Project File: dcol.ise Current State: Programming File Generated
Module Name: DCOL
  • Errors:
No Errors
Target Device: xc3s4000-4fg676
  • Warnings:
477 Warnings
Product Version: ISE 10.1.03 - Foundation Simulator
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
dcol Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 2,230 55,296 4%  
Number of 4 input LUTs 3,133 55,296 5%  
Logic Distribution     
Number of occupied Slices 2,492 27,648 9%  
    Number of Slices containing only related logic 2,492 2,492 100%  
    Number of Slices containing unrelated logic 0 2,492 0%  
Total Number of 4 input LUTs 3,448 55,296 6%  
    Number used as logic 2,891      
    Number used as a route-thru 315      
    Number used as 16x1 RAMs 19      
    Number used for Dual Port RAMs 128      
    Number used as Shift registers 95      
Number of bonded IOBs
Number of bonded 228 489 46%  
    IOB Flip Flops 212      
    IOB Latches 38      
    IOB Master Pads 27      
    IOB Slave Pads 27      
Number of RAMB16s 17 96 17%  
Number of BUFGMUXs 8 8 100%  
Number of DCMs 3 4 75%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Oct 6 15:05:50 20090252 Warnings39 Infos
Translation ReportCurrentTue Oct 6 15:05:57 2009085 Warnings6 Infos
Map ReportCurrentTue Oct 6 15:07:31 20090135 Warnings44 Infos
Place and Route ReportCurrentTue Oct 6 15:09:39 200905 Warnings5 Infos
Static Timing ReportCurrentTue Oct 6 15:09:55 2009003 Infos
Bitgen ReportCurrentTue Oct 6 15:10:16 2009015 Warnings1 Info

Date Generated: 10/06/2009 - 15:10:17