Device Usage Page (device_usage_statistics.html)

This HTML page displays the device usage statistics that will be sent to Xilinx. The file also contains predefined XML tags used to simplify processing.
 
Please verify the contents are okay to send to Xilinx!
 

 
Software Version and Target Device
Product Version: ISE:10.1.03 (Foundation Simulator) Target Family: spartan3
OS Platform: NT Target Device: xc3s4000
Project ID (random number) 26951.25496.6 Target Package: fg676
Registration ID 182TANLZJHKZXTUAMZ450J4DT Target Speed: -4
Date Generated Tue Oct 6 15:10:16 2009
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Comparators=81
  • 11-bit comparator equal=1
  • 2-bit comparator equal=15
  • 2-bit comparator not equal=3
  • 3-bit comparator equal=24
  • 3-bit comparator not equal=24
  • 32-bit comparator equal=1
  • 4-bit comparator equal=2
  • 4-bit comparator not equal=2
  • 5-bit comparator equal=3
  • 5-bit comparator not equal=3
  • 7-bit comparator not equal=1
  • 8-bit comparator not equal=1
  • 9-bit comparator not equal=1
Accumulators=2
  • 8-bit up accumulator=1
  • 8-bit up loadable accumulator=1
Xors=25
  • 1-bit xor2=23
  • 1-bit xor4=2
Latches=3
  • 1-bit latch=1
  • 32-bit latch=1
  • 6-bit latch=1
Multiplexers=49
  • 1-bit 12-to-1 multiplexer=4
  • 1-bit 16-to-1 multiplexer=33
  • 1-bit 4-to-1 multiplexer=10
  • 32-bit 4-to-1 multiplexer=1
  • 32-bit 8-to-1 multiplexer=1
Registers=1972
  • Flip-Flops=1972
Adders/Subtractors=63
  • 11-bit adder=2
  • 11-bit subtractor=1
  • 12-bit adder=2
  • 13-bit adder=1
  • 15-bit adder=1
  • 19-bit adder=2
  • 2-bit adder=11
  • 2-bit subtractor=1
  • 21-bit adder=1
  • 32-bit adder=1
  • 4-bit adder=12
  • 4-bit subtractor=12
  • 5-bit adder=9
  • 6-bit adder=1
  • 8-bit adder=4
  • 9-bit adder=2
Counters=98
  • 10-bit up counter=1
  • 16-bit up counter=1
  • 2-bit up counter=41
  • 24-bit up counter=1
  • 32-bit up counter=4
  • 33-bit up counter=1
  • 4-bit up counter=4
  • 4-bit updown counter=32
  • 5-bit up counter=3
  • 7-bit up counter=1
  • 8-bit up counter=6
  • 8-bit updown counter=1
  • 9-bit up counter=2
MiscellaneousStatistics
  • AGG_BONDED_IO=228
  • AGG_IO=228
  • AGG_SLICE=2492
  • NUM_4_INPUT_LUT=3448
  • NUM_BONDED_DIFFM=27
  • NUM_BONDED_DIFFS=27
  • NUM_BONDED_IOB=174
  • NUM_BUFGMUX=8
  • NUM_CYMUX=401
  • NUM_DCM=3
  • NUM_DP_RAM=128
  • NUM_IOB_FF=212
  • NUM_IOB_LATCH=38
  • NUM_LUT_RT=315
  • NUM_MULTAND=1
  • NUM_RAM16=19
  • NUM_RAMB16=17
  • NUM_SHIFT=95
  • NUM_SLICEL=2339
  • NUM_SLICEM=153
  • NUM_SLICE_FF=2230
  • NUM_XOR=377
NetStatistics
  • NumNets_Active=5069
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=317
  • NumNodesOfType_Active_BRAMDUMMY=357
  • NumNodesOfType_Active_CLKPIN=2082
  • NumNodesOfType_Active_CNTRLPIN=2528
  • NumNodesOfType_Active_DOUBLE=10716
  • NumNodesOfType_Active_DUMMY=10124
  • NumNodesOfType_Active_DUMMYBANK=197
  • NumNodesOfType_Active_DUMMYESC=104
  • NumNodesOfType_Active_GLOBAL=479
  • NumNodesOfType_Active_HFULLHEX=273
  • NumNodesOfType_Active_HLONG=33
  • NumNodesOfType_Active_HUNIHEX=2010
  • NumNodesOfType_Active_INPUT=12243
  • NumNodesOfType_Active_IOBOUTPUT=179
  • NumNodesOfType_Active_OMUX=5248
  • NumNodesOfType_Active_OUTPUT=4663
  • NumNodesOfType_Active_PREBXBY=2284
  • NumNodesOfType_Active_VFULLHEX=1218
  • NumNodesOfType_Active_VLONG=45
  • NumNodesOfType_Active_VUNIHEX=1261
  • NumNodesOfType_Gnd_BRAMADDR=42
  • NumNodesOfType_Gnd_BRAMDUMMY=60
  • NumNodesOfType_Gnd_CLKPIN=2
  • NumNodesOfType_Gnd_CNTRLPIN=97
  • NumNodesOfType_Gnd_DOUBLE=100
  • NumNodesOfType_Gnd_DUMMY=57
  • NumNodesOfType_Gnd_DUMMYBANK=27
  • NumNodesOfType_Gnd_HUNIHEX=1
  • NumNodesOfType_Gnd_INPUT=178
  • NumNodesOfType_Gnd_OMUX=115
  • NumNodesOfType_Gnd_OUTPUT=78
  • NumNodesOfType_Gnd_PREBXBY=59
  • NumNodesOfType_Gnd_VFULLHEX=9
  • NumNodesOfType_Vcc_CNTRLPIN=35
  • NumNodesOfType_Vcc_DUMMY=181
  • NumNodesOfType_Vcc_INPUT=237
  • NumNodesOfType_Vcc_PREBXBY=46
  • NumNodesOfType_Vcc_VCCOUT=108
SiteSummary
  • BUFGMUX=8
  • BUFGMUX_GCLKMUX=8
  • BUFGMUX_GCLK_BUFFER=8
  • DCM=3
  • DCM_DCM=3
  • DIFFM=27
  • DIFFM_IFF1=1
  • DIFFM_INBUF=2
  • DIFFM_OFF1=25
  • DIFFM_OUTBUF=25
  • DIFFM_PAD=27
  • DIFFS=27
  • DIFFS_DIFFO_IN_USED=25
  • DIFFS_OUTBUF=25
  • DIFFS_PAD=27
  • DIFFS_PADOUT_USED=2
  • IOB=174
  • IOB_IFF1=58
  • IOB_IFF2=17
  • IOB_INBUF=130
  • IOB_OFF1=109
  • IOB_OFF2=22
  • IOB_OFFDDRBLACKBOX=22
  • IOB_OUTBUF=125
  • IOB_PAD=174
  • IOB_TFF1=18
  • RAMB16=17
  • RAMB16_RAMB16=17
  • RAMB16_RAMB16A=17
  • RAMB16_RAMB16B=17
  • SLICEL=2339
  • SLICEL_C1VDD=23
  • SLICEL_C2VDD=2
  • SLICEL_CYMUXF=211
  • SLICEL_CYMUXG=190
  • SLICEL_F=1401
  • SLICEL_F5MUX=327
  • SLICEL_F6MUX=46
  • SLICEL_FFX=822
  • SLICEL_FFY=1307
  • SLICEL_G=1781
  • SLICEL_GAND=1
  • SLICEL_GNDF=169
  • SLICEL_GNDG=174
  • SLICEL_XORF=193
  • SLICEL_XORG=184
  • SLICEM=153
  • SLICEM_F=113
  • SLICEM_F5MUX=12
  • SLICEM_F6MUX=12
  • SLICEM_FFX=37
  • SLICEM_FFY=64
  • SLICEM_G=153
  • SLICEM_WSGEN=141
 
Configuration Data
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:8]
DCM_DCM
  • CLKDV_DIVIDE=[2:3]
  • CLKOUT_PHASE_SHIFT=[NONE:2] [VARIABLE:1]
  • CLK_FEEDBACK=[1X:2] [2X:1]
  • DESKEW_ADJUST=[8:3]
  • DFS_FREQUENCY_MODE=[LOW:3]
  • DLL_FREQUENCY_MODE=[LOW:3]
  • DUTY_CYCLE_CORRECTION=[TRUE:3]
  • FACTORY_JF1=[0XC0:3]
  • FACTORY_JF2=[0X80:3]
DIFFM_IFF1
  • IFF1_INIT_ATTR=[INIT0:1]
  • LATCH_OR_FF=[FF:1]
DIFFM_OFF1
  • LATCH_OR_FF=[FF:25]
  • OFF1_INIT_ATTR=[INIT0:25]
  • OFF1_SR_ATTR=[SRLOW:12]
  • OFFATTRBOX=[SYNC:12]
DIFFM_PAD
  • IOATTRBOX=[LVDS_25:27]
DIFFS_PAD
  • IOATTRBOX=[LVDS_25:27]
IOB_IFF1
  • IFF1_INIT_ATTR=[INIT0:57] [INIT1:1]
  • LATCH_OR_FF=[FF:20] [LATCH:38]
IOB_IFF2
  • IFF2_INIT_ATTR=[INIT0:17]
  • LATCH_OR_FF=[FF:17]
IOB_OFF1
  • LATCH_OR_FF=[FF:109]
  • OFF1_INIT_ATTR=[INIT0:106] [INIT1:3]
  • OFF1_SR_ATTR=[SRLOW:1] [SRHIGH:4]
  • OFFATTRBOX=[ASYNC:2] [SYNC:3]
IOB_OFF2
  • LATCH_OR_FF=[FF:22]
  • OFF2_INIT_ATTR=[INIT0:22]
  • OFF2_SR_ATTR=[SRHIGH:2]
  • OFFATTRBOX=[SYNC:2]
IOB_PAD
  • DRIVEATTRBOX=[8:83]
  • IOATTRBOX=[SSTL2_I:42] [LVTTL:128] [LVCMOS25:4]
  • PULL=[PULLUP:14]
  • SLEW=[SLOW:83]
IOB_TFF1
  • LATCH_OR_FF=[FF:18]
  • TFF1_INIT_ATTR=[INIT0:18]
RAMB16_RAMB16A
  • PORTA_ATTR=[16384X1:5] [512X36:4] [2048X9:8]
  • WRITEMODEA=[WRITE_FIRST:17]
RAMB16_RAMB16B
  • PORTB_ATTR=[512X36:11] [2048X9:6]
  • WRITEMODEB=[WRITE_FIRST:17]
SLICEL_FFX
  • FFX_INIT_ATTR=[INIT0:792] [INIT1:30]
  • FFX_SR_ATTR=[SRLOW:801] [SRHIGH:21]
  • LATCH_OR_FF=[FF:822]
  • SYNC_ATTR=[ASYNC:656] [SYNC:166]
SLICEL_FFY
  • FFY_INIT_ATTR=[INIT0:1251] [INIT1:56]
  • FFY_SR_ATTR=[SRLOW:1274] [SRHIGH:33]
  • LATCH_OR_FF=[FF:1307]
  • SYNC_ATTR=[ASYNC:1047] [SYNC:260]
SLICEM_F
  • F_ATTR=[DUAL_PORT:64] [SHIFT_REG:29]
  • LUT_OR_MEM=[LUT:12] [RAM:101]
SLICEM_FFX
  • FFX_INIT_ATTR=[INIT0:37]
  • FFX_SR_ATTR=[SRLOW:37]
  • LATCH_OR_FF=[FF:37]
  • SYNC_ATTR=[ASYNC:37]
SLICEM_FFY
  • FFY_INIT_ATTR=[INIT0:64]
  • FFY_SR_ATTR=[SRLOW:64]
  • LATCH_OR_FF=[FF:64]
  • SYNC_ATTR=[ASYNC:64]
SLICEM_G
  • G_ATTR=[DUAL_PORT:64] [SHIFT_REG:66]
  • LUT_OR_MEM=[LUT:12] [RAM:141]
SLICEM_WSGEN
  • SYNC_ATTR=[ASYNC:69]
 
Pin Data
BUFGMUX
  • I0=8
  • I1=1
  • O=8
  • S=8
BUFGMUX_GCLKMUX
  • I0=8
  • I1=1
  • OUT=8
  • S=8
BUFGMUX_GCLK_BUFFER
  • IN=8
  • OUT=8
DCM
  • CLK0=2
  • CLK270=1
  • CLK2X=1
  • CLK90=2
  • CLKFB=3
  • CLKIN=3
  • LOCKED=2
  • PSCLK=3
  • PSDONE=1
  • PSEN=3
  • PSINCDEC=3
  • RST=3
DCM_DCM
  • CLK0=2
  • CLK270=1
  • CLK2X=1
  • CLK90=2
  • CLKFB=3
  • CLKIN=3
  • LOCKED=2
  • PSCLK=3
  • PSDONE=1
  • PSEN=3
  • PSINCDEC=3
  • RST=3
DIFFM
  • DIFFI_IN=2
  • DIFFO_OUT=25
  • I=1
  • ICLK1=1
  • IQ1=1
  • O1=25
  • OCE=1
  • OTCLK1=25
  • PAD=27
  • SR=12
DIFFM_IFF1
  • CK=1
  • D=1
  • Q=1
DIFFM_INBUF
  • DIFFI_IN=2
  • OUT=2
  • PAD=2
DIFFM_OFF1
  • CE=1
  • CK=25
  • D=25
  • Q=25
  • SR=12
DIFFM_OUTBUF
  • IN=25
  • OUTN=25
  • OUTP=25
DIFFM_PAD
  • PAD=27
DIFFS
  • DIFFO_IN=25
  • PAD=27
  • PADOUT=2
DIFFS_DIFFO_IN_USED
  • 0=25
  • OUT=25
DIFFS_OUTBUF
  • DIFFO_IN=25
  • OUTP=25
DIFFS_PAD
  • PAD=27
DIFFS_PADOUT_USED
  • 0=2
  • OUT=2
IOB
  • I=104
  • ICE=1
  • ICLK1=58
  • ICLK2=17
  • IQ1=58
  • IQ2=17
  • O1=125
  • O2=22
  • OCE=67
  • OTCLK1=109
  • OTCLK2=22
  • PAD=174
  • SR=5
  • T1=82
IOB_IFF1
  • CE=1
  • CK=58
  • D=58
  • Q=58
IOB_IFF2
  • CK=17
  • D=17
  • Q=17
IOB_INBUF
  • IN=130
  • OUT=130
IOB_OFF1
  • CE=67
  • CK=109
  • D=109
  • Q=109
  • SR=5
IOB_OFF2
  • CK=22
  • D=22
  • Q=22
  • SR=2
IOB_OFFDDRBLACKBOX
  • OFF1=22
  • OFF2=22
  • OFFDDR=22
IOB_OUTBUF
  • IN=125
  • OUT=125
  • TRI=82
IOB_PAD
  • PAD=174
IOB_TFF1
  • CK=18
  • D=18
  • Q=18
RAMB16
  • ADDRA0=5
  • ADDRA1=5
  • ADDRA10=17
  • ADDRA11=17
  • ADDRA12=17
  • ADDRA13=17
  • ADDRA2=5
  • ADDRA3=13
  • ADDRA4=13
  • ADDRA5=17
  • ADDRA6=17
  • ADDRA7=17
  • ADDRA8=17
  • ADDRA9=17
  • ADDRB10=17
  • ADDRB11=17
  • ADDRB12=17
  • ADDRB13=17
  • ADDRB3=6
  • ADDRB4=6
  • ADDRB5=17
  • ADDRB6=17
  • ADDRB7=17
  • ADDRB8=17
  • ADDRB9=17
  • CLKA=17
  • CLKB=17
  • DIA0=12
  • DIA1=9
  • DIA10=3
  • DIA11=3
  • DIA12=3
  • DIA13=3
  • DIA14=3
  • DIA15=3
  • DIA16=3
  • DIA17=3
  • DIA18=3
  • DIA19=3
  • DIA2=9
  • DIA20=3
  • DIA21=3
  • DIA22=3
  • DIA23=3
  • DIA24=3
  • DIA25=3
  • DIA26=3
  • DIA27=3
  • DIA28=3
  • DIA29=3
  • DIA3=9
  • DIA30=3
  • DIA31=3
  • DIA4=9
  • DIA5=9
  • DIA6=9
  • DIA7=9
  • DIA8=3
  • DIA9=3
  • DIB0=7
  • DIB1=7
  • DIB10=7
  • DIB11=7
  • DIB12=7
  • DIB13=7
  • DIB14=7
  • DIB15=7
  • DIB16=7
  • DIB17=7
  • DIB18=7
  • DIB19=7
  • DIB2=7
  • DIB20=7
  • DIB21=7
  • DIB22=7
  • DIB23=7
  • DIB24=7
  • DIB25=7
  • DIB26=7
  • DIB27=7
  • DIB28=7
  • DIB29=7
  • DIB3=7
  • DIB30=7
  • DIB31=7
  • DIB4=7
  • DIB5=7
  • DIB6=7
  • DIB7=7
  • DIB8=7
  • DIB9=7
  • DIPA0=9
  • DIPA1=3
  • DIPA2=3
  • DIPA3=3
  • DIPB0=7
  • DIPB1=7
  • DIPB2=7
  • DIPB3=7
  • DOA0=6
  • DOA1=4
  • DOA10=2
  • DOA11=2
  • DOA12=2
  • DOA13=2
  • DOA14=2
  • DOA15=2
  • DOA16=2
  • DOA17=2
  • DOA18=2
  • DOA19=2
  • DOA2=4
  • DOA20=2
  • DOA21=2
  • DOA22=2
  • DOA23=2
  • DOA24=2
  • DOA25=2
  • DOA26=2
  • DOA27=2
  • DOA28=2
  • DOA29=2
  • DOA3=4
  • DOA30=2
  • DOA31=2
  • DOA4=4
  • DOA5=4
  • DOA6=4
  • DOA7=4
  • DOA8=2
  • DOA9=2
  • DOB0=14
  • DOB1=14
  • DOB10=8
  • DOB11=8
  • DOB12=8
  • DOB13=8
  • DOB14=8
  • DOB15=8
  • DOB16=8
  • DOB17=8
  • DOB18=8
  • DOB19=8
  • DOB2=14
  • DOB20=8
  • DOB21=8
  • DOB22=8
  • DOB23=7
  • DOB24=7
  • DOB25=7
  • DOB26=7
  • DOB27=7
  • DOB28=7
  • DOB29=7
  • DOB3=14
  • DOB30=7
  • DOB31=7
  • DOB4=14
  • DOB5=14
  • DOB6=14
  • DOB7=14
  • DOB8=8
  • DOB9=8
  • DOPB0=2
  • DOPB1=2
  • DOPB2=2
  • DOPB3=2
  • ENA=17
  • ENB=17
  • SSRA=17
  • SSRB=17
  • WEA=17
  • WEB=17
RAMB16_RAMB16
  • ADDRA=17
  • ADDRB=17
  • DIA=17
  • DIB=17
  • DOA=17
  • DOB=17
RAMB16_RAMB16A
  • ADDRA=17
  • ADDRA0=5
  • ADDRA1=5
  • ADDRA10=17
  • ADDRA11=17
  • ADDRA12=17
  • ADDRA13=17
  • ADDRA2=5
  • ADDRA3=13
  • ADDRA4=13
  • ADDRA5=17
  • ADDRA6=17
  • ADDRA7=17
  • ADDRA8=17
  • ADDRA9=17
  • CLKA=17
  • DIA=17
  • DIA0=12
  • DIA1=9
  • DIA10=3
  • DIA11=3
  • DIA12=3
  • DIA13=3
  • DIA14=3
  • DIA15=3
  • DIA16=3
  • DIA17=3
  • DIA18=3
  • DIA19=3
  • DIA2=9
  • DIA20=3
  • DIA21=3
  • DIA22=3
  • DIA23=3
  • DIA24=3
  • DIA25=3
  • DIA26=3
  • DIA27=3
  • DIA28=3
  • DIA29=3
  • DIA3=9
  • DIA30=3
  • DIA31=3
  • DIA4=9
  • DIA5=9
  • DIA6=9
  • DIA7=9
  • DIA8=3
  • DIA9=3
  • DIPA0=9
  • DIPA1=3
  • DIPA2=3
  • DIPA3=3
  • DOA=17
  • DOA0=6
  • DOA1=4
  • DOA10=2
  • DOA11=2
  • DOA12=2
  • DOA13=2
  • DOA14=2
  • DOA15=2
  • DOA16=2
  • DOA17=2
  • DOA18=2
  • DOA19=2
  • DOA2=4
  • DOA20=2
  • DOA21=2
  • DOA22=2
  • DOA23=2
  • DOA24=2
  • DOA25=2
  • DOA26=2
  • DOA27=2
  • DOA28=2
  • DOA29=2
  • DOA3=4
  • DOA30=2
  • DOA31=2
  • DOA4=4
  • DOA5=4
  • DOA6=4
  • DOA7=4
  • DOA8=2
  • DOA9=2
  • ENA=17
  • SSRA=17
  • WEA=17
RAMB16_RAMB16B
  • ADDRB=17
  • ADDRB10=17
  • ADDRB11=17
  • ADDRB12=17
  • ADDRB13=17
  • ADDRB3=6
  • ADDRB4=6
  • ADDRB5=17
  • ADDRB6=17
  • ADDRB7=17
  • ADDRB8=17
  • ADDRB9=17
  • CLKB=17
  • DIB=17
  • DIB0=7
  • DIB1=7
  • DIB10=7
  • DIB11=7
  • DIB12=7
  • DIB13=7
  • DIB14=7
  • DIB15=7
  • DIB16=7
  • DIB17=7
  • DIB18=7
  • DIB19=7
  • DIB2=7
  • DIB20=7
  • DIB21=7
  • DIB22=7
  • DIB23=7
  • DIB24=7
  • DIB25=7
  • DIB26=7
  • DIB27=7
  • DIB28=7
  • DIB29=7
  • DIB3=7
  • DIB30=7
  • DIB31=7
  • DIB4=7
  • DIB5=7
  • DIB6=7
  • DIB7=7
  • DIB8=7
  • DIB9=7
  • DIPB0=7
  • DIPB1=7
  • DIPB2=7
  • DIPB3=7
  • DOB=17
  • DOB0=14
  • DOB1=14
  • DOB10=8
  • DOB11=8
  • DOB12=8
  • DOB13=8
  • DOB14=8
  • DOB15=8
  • DOB16=8
  • DOB17=8
  • DOB18=8
  • DOB19=8
  • DOB2=14
  • DOB20=8
  • DOB21=8
  • DOB22=8
  • DOB23=7
  • DOB24=7
  • DOB25=7
  • DOB26=7
  • DOB27=7
  • DOB28=7
  • DOB29=7
  • DOB3=14
  • DOB30=7
  • DOB31=7
  • DOB4=14
  • DOB5=14
  • DOB6=14
  • DOB7=14
  • DOB8=8
  • DOB9=8
  • DOPB0=2
  • DOPB1=2
  • DOPB2=2
  • DOPB3=2
  • ENB=17
  • SSRB=17
  • WEB=17
SLICEL
  • BX=563
  • BY=782
  • CE=1280
  • CIN=187
  • CLK=1668
  • COUT=190
  • F1=1398
  • F2=1195
  • F3=938
  • F4=572
  • F5=92
  • FX=6
  • FXINA=46
  • FXINB=46
  • G1=1751
  • G2=1557
  • G3=1153
  • G4=582
  • SR=536
  • X=677
  • XB=4
  • XQ=822
  • Y=881
  • YQ=1307
SLICEL_C1VDD
  • 1=23
SLICEL_C2VDD
  • 1=2
SLICEL_CYMUXF
  • 0=211
  • 1=211
  • OUT=211
  • S0=211
SLICEL_CYMUXG
  • 0=190
  • 1=190
  • OUT=190
  • S0=190
SLICEL_F
  • A1=1395
  • A2=1195
  • A3=938
  • A4=572
  • D=1401
SLICEL_F5MUX
  • F=327
  • G=327
  • OUT=327
  • S0=327
SLICEL_F6MUX
  • 0=46
  • 1=46
  • OUT=46
  • S0=46
SLICEL_FFX
  • CE=703
  • CK=822
  • D=822
  • Q=822
  • REV=42
  • SR=278
SLICEL_FFY
  • CE=953
  • CK=1307
  • D=1307
  • Q=1307
  • SR=422
SLICEL_G
  • A1=1748
  • A2=1557
  • A3=1153
  • A4=582
  • D=1781
SLICEL_GAND
  • 0=1
  • 1=1
  • O=1
SLICEL_GNDF
  • 0=169
SLICEL_GNDG
  • 0=174
SLICEL_XORF
  • 0=193
  • 1=193
  • O=193
SLICEL_XORG
  • 0=184
  • 1=184
  • O=184
SLICEM
  • BX=52
  • BY=153
  • CE=57
  • CLK=141
  • F1=113
  • F2=113
  • F3=113
  • F4=101
  • F5=12
  • FX=6
  • FXINA=12
  • FXINB=12
  • G1=153
  • G2=153
  • G3=147
  • G4=141
  • SR=141
  • X=67
  • XQ=37
  • Y=66
  • YQ=64
SLICEM_F
  • A1=113
  • A2=113
  • A3=113
  • A4=101
  • D=113
  • DI=101
  • WF1=72
  • WF2=72
  • WF3=72
  • WF4=72
  • WS=101
SLICEM_F5MUX
  • F=12
  • G=12
  • OUT=12
  • S0=12
SLICEM_F6MUX
  • 0=12
  • 1=12
  • OUT=12
  • S0=12
SLICEM_FFX
  • CE=32
  • CK=37
  • D=37
  • Q=37
SLICEM_FFY
  • CE=57
  • CK=64
  • D=64
  • Q=64
SLICEM_G
  • A1=153
  • A2=153
  • A3=147
  • A4=141
  • D=124
  • DI=141
  • WG1=75
  • WG2=75
  • WG3=75
  • WG4=75
  • WS=141
SLICEM_WSGEN
  • CK=141
  • WE=141
  • WSF=101
  • WSG=141
 
Tool Usage
Command Line History
  • xst -ise <ise_file> -intstyle ise -ifn <fname>.xst -ofn <fname>.syr
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s4000-fg676-4 -timing -logic_opt on -ol high -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s4000-fg676-4 -timing -logic_opt on -ol high -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe n -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s4000-fg676-4 -timing -logic_opt on -ol high -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe n -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • xst -ise <ise_file>
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s4000-fg676-4 -timing -logic_opt on -ol high -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe n -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s4000-fg676-4 -timing -logic_opt on -ol high -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe n -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -v 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
 
>
Software Quality
Run Statistics
ProgramRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
XSLTProcess 96 96 0 0 0 0 0
_impact 8 7 0 0 0 0 0
arwz 5 5 0 0 0 0 0
bitgen 874 874 0 0 0 0 0
cpldfit 96 96 0 0 0 0 0
edif2ngd 12 12 0 0 0 0 0
hprep6 96 96 0 0 0 0 0
map 1710 1440 0 0 0 0 0
netgen 100 99 0 0 0 0 0
ngdbuild 1867 1856 0 0 0 0 0
par 1364 1337 14 0 0 0 0
reportgen 1414 1414 0 0 0 0 0
taengine 96 96 0 0 0 0 0
trce 1338 1338 0 0 0 0 0
tsim 96 96 0 0 0 0 0
xst 2675 2650 0 0 0 0 0
 
Help Statistics
Unsuccessful Search words
dcm clock wizard ( 1 )
Help files
/doc/usenglish/books/docs/dev/dev.pdf ( 2 ) /doc/usenglish/isehelp/ite_c_overview.htm ( 1 )
/doc/usenglish/isehelp/pim_db_usbsetupdlg.htm ( 1 ) /doc/usenglish/isehelp/pim_p_connectingtocables.htm ( 1 )
/doc/usenglish/isehelp/pp_db_map_properties.htm ( 1 ) /doc/usenglish/isehelp/pp_db_place_and_route_properties.htm ( 1 )
/doc/usenglish/isehelp/pp_n_process_check_syntax.htm ( 1 ) /doc/usenglish/isehelp/pta_c_ttc-path-end-points-tab.htm ( 1 )
/doc/usenglish/isehelp/pta_db_analyze_against_user_specified_paths_button.htm ( 1 ) /doc/usenglish/isehelp/pta_p_using_path_tracing.htm ( 1 )
/doc/usenglish/wizards/arwz/awz_db_dcmgen.htm ( 1 )
 
Project Statistics
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_Simulator=ISE Simulator (VHDL/Verilog)
PROP_Top_Level_Module_Type=HDL PROP_PreferredLanguage=VHDL
PROP_Enable_Message_Filtering=false PROP_Enable_Incremental_Messaging=false
PROP_UseSmartGuide=false Partitions count=1
FILE_UCF=1 FILE_VERILOG=1
FILE_VHDL=23 PROP_xilxMapTimingDrivenPacking=true
PROPEXT_xilxSynthMaxFanout_virtex2=100 PROP_DevDevice=xc3s4000
PROP_DevFamily=Spartan3 PROP_DevSpeed=-4
PROP_FitterReportFormat=HTML PROP_ImpactProjectFile=changed
PROP_MapEffortLevel=High PROP_MapLogicOptimization=true
PROP_MapPowerReduction=true PROP_MapRegDuplication=true
PROP_PreferredLanguage=VHDL PROP_SynthOptEffort=High
PROP_SynthShiftRegExtract=false PROP_UserConstraintEditorPreference=Constraints Editor
PROP_parGenAsyDlyRpt=true PROP_parPowerReduction=true
PROP_xilxBitgStart_Clk_DriveDone=true PROP_xilxMapAllowLogicOpt=true
PROP_xilxMapCoverMode=Speed PROP_xilxMapPackRegInto=For Inputs and Outputs
PROP_xilxMapReportDetail=true PROP_xilxNgdbldIOPads=true
PROP_xilxPAReffortLevel=High PROP_xilxPARextraEffortLevel=Normal
PROP_xilxSynthKeepHierarchy=Yes PROP_xstEquivRegRemoval=false
PROP_xstGenerateRTLNetlist=No PROP_xstOptimizeInsPrimtives=true
Project duration(days)=371