DCOL test procedure
0. assign serial number to the board
1. power up with current limited power supplies and check 5V,3.3V and 2.5V
2. install module in slot 12 and plug in JTAG cable.
3. program CPLD and then FPGA with impact from bul3x1(log in as daq, impact project DCOL_conf.ipf can be found in c:\iseproj\DCOL)
4. on a higgs terminal run ./dcol 12 (program and mcs files can be found in ~wusx/dcol_test)
5. p dcolv19.mcs 0 (write default FLASH file) 
6. p dcol_test.mcs 1 (write test FLASH file)
7. w 0x18 0xabcdef01 (configure the module to IO test configuration)
8. connect test cable:
     connect the end with dangling wires to the module top trigger connector.
     connect the dangling wires to a voltage meter in DC range > 5V 
     connect the other end to input N, start with N = 1
9. w 8 0(to reset electronic circuit breaker) followed by w 8 (0x1000 + (1 << (N-1))), make sure voltage meter shows about 5V
10. w 0 1 (reset the module)
11. w 0 0x80 (start test)
12. r 0xc ( read test pattern, do it several times and make sure it is changing all the time)
repeat 8 thru 12 until all twelve inputs are tested.
13. w 4 0x8(select spare input for test)
14. replace the cable with the second test cable. Pay attention to connect the labeled end to the trigger connector
    and the other end to connector 12
15. w 0 1
16. w 0 0x80 (start test)
17. r 0xc ( read test pattern, do it several times and make sure it is changing all the time)
18. r 4 (make sure bits 23-16 represents the board Serial Number and bits 15-8 are all 0)
19. w 0x18 0xabcdef00 (configure the module to default configuration)
20. w 0x4000 0xa5a5a5a5
21. w 0x4004 0xa5a5a5a5
22. w 0x4008 0x5a5a5a5a
23. w 0x400c 0x5a5a5a5a
24. br 0x4000 4 (check that data read back are the same as written)
25. w 0 1
26. w 0 0x80 ( start memory test )
27. r 0x38 ( read test pattern, do it several times and make sure it is changing all the time)
28. p dcolv19.mcs 1 (write spare sector with default FLASH file)