version v19 released on nov-23-2009 A bug in DCON_if of DCON_addr_i fixed version v18 released on nov-19-2009 A bug in checksum output fixed. version v16 released on nov-17-2009 time spec for mclk0, mclk90 and mclk270 added to ucf. TS_clk does not seem to have been propagated to mclkxx as expected version v15 released on nov-5-2009 A bug in test signal output fixed version v14 released on oct-29-2009 reenabled 10 byte slow-control Tx upon request version v13 released on oct-13-2009 New version adopted new data format. The DCOL VME address in the data equals slot# - 4 as requested. DCOL supports AM code 08-0F, MBLT and D32 A31-A27 are decided by GAn pins if available, or set by switches on the board. DCOL memory map 0x0 CMD r/w board level command register w bit 0 resets everything bit 1 resets DCON receiving decoding circuits bit 2 resets counters bit 7 starts memory test r bit 4-0 unused bit 5 if '1', power to DCON not ready bit 6 if '1', memory test failed bit 7 if '1', memory test onging bit 30-16 unused bit 31 if '1', FPGA is configured from backup configuration file. 0x4 CSR r/w board level control and status register, this is a set/reset register write '1' to bit i in range 15-0 sets bit i to '1' write '1' to bit i in range 31-16 resets bit i-16 to '0' write '0' to any bit has no effect. bit 0 if '1', run mode bit 1 if '1', use circular event buffer bit 2 if '1', standalone mode(when no TTM is available) bit 3 if '1', disables timestamp sorting bit 14-4 unused bit 15 if '1', put DCOL in standalone mode and TTM inputs are ignored r bit 23-16 board SN r bit 31-24 firmware version 0x8 DCON_enable r/w DCON interface enable register bit 0 if '1', enable DCON IO_1 ..... bit 11 if '1', enable DCON IO_12 bit 12 if '1', enable power to DCON bit 15-13 unused r bit 16 if '1', DCON IO_1 receiving locked to input stream ..... r bit 27 if '1', DCON IO_12 receiving locked to input stream bit 31-28 unused 0xc Event_size r size of the event in current event data buffer(0x4000-0x7fff) 0x10 DDRRAM status r for debugging only 0x14 Event_wp r circular event buffer write pointer. Valid values are between 0x800000 thru 0x1ffffff 0x18 FPGA_prg w write 0xabcdef00 will reconfigure the FPGA with default file write 0xabcdef01 will reconfigure the FPGA with backup file r counts reset pulse count(temporary) 0x1c FLASH_CSR r/w FLASH control and status register (FLASH programming program will be provided) 0x20 MEM_PAGE r/w memory page register. bit 10-0 defines memory window to be accessed. While not in run mode, this register can be set to access any memory window. During data taking, write anything to this register increments it. In circular mode, this moves the read pointer by one page. For non-circular mode, this moves the memory window to next event. bit 31-11 not used 0x24 test pulse counter r Counts test pulse count when not in standalone mode.(temporary) 0x28 SLOW_CTRL_Tx r/w SLOW control Tx control and status register w bit 1-0 DCON channel 1 slow control data send length "00" nothing to send "01" length = 2 bytes "10" length = 3 bytes "11" length = 10 bytes (was 10 bytes till dcolv11) bit 3-2 DCON channel 2 slow control data send length bit 5-4 DCON channel 3 slow control data send length bit 7-6 DCON channel 4 slow control data send length bit 9-8 DCON channel 5 slow control data send length bit 11-10 DCON channel 6 slow control data send length bit 13-12 DCON channel 7 slow control data send length bit 15-14 DCON channel 8 slow control data send length bit 17-16 DCON channel 9 slow control data send length bit 19-18 DCON channel 10 slow control data send length bit 21-20 DCON channel 11 slow control data send length bit 23-22 DCON channel 12 slow control data send length bit 28-24 not used bit 31-29 specifies slow control command set to be sent r if bit 23-0 are all '0', all data are sent. bit 28-24 not used bit 31-29 specifies slow control command set to be sent 0x2c SLOW_CTRL_Rx r SLOW control Rx control and status register. This register is cleared when writing to SLOW_CTRL_Tx. bit 0 if '1', DCON input1 has valid slow control data ...... bit 11 if '1', DCON input12 has valid slow control data bit 31-12 unused 0x30 trigger counter r Counts trigger count(temporary) 0x1000 - 0x1103 r/w FLASH write buffer (FLASH programming program will be provided) 0x1200 - 0x12ff r FLASH read buffer (FLASH programming program will be provided) 0x1800 - 0x19ff r monitor counters (TBD) 0x2000 - 0x25ff r/w slow control Tx buffer 0x2000-0x207f for DCON input 1,...... 0x2580-0x25ff for DCON input 12 each command occupies 16bytes of space, so eight sets of command can be saved in the buffer and no need to load them if the needed slow control data are already in the buffer. First byte of slow control data should be stored at address with four LSBs equal 0, and following bytes stored in locations of ascending addresses. 0x2800 - 0x282f r slow control Rx buffer each DCON input has four bytes of space, so read them out before requesting new data. 0x2800-0x2803 for DCON input 1,...... 0x282c-0x282f for DCON input 12 First byte of slow control data is stored at address with two LSBs equal 0, and following bytes stored in locations of ascending addresses. 0x4000 - 0x7fff r/w memory page buffer Used to access a memory window defined by MEM_PAGE register. If DCOL is set to build event with the same time stamp, event data are read from this area. Event_size register indicates the event size in bytes. If event size is 0, no event data is available. To move to next event, write anything to MEM_PAGE register. 0x0800000 - 0x1ffffff r circular event buffer event data are stored in order of time stamp. No gaps between data with different time stamps. After reset, both write and read pointers are reset to 0x8000000 and they wrap around at 0x1ffffff. DCOL moves the write pointer as event data fill the buffer. DCOL will stop filling data if the write pointer catches the read pointer. DAQ readout should move the write pointer to free buffer space after reading out the data.