Design Name | DCOL_conf |
Fitting Status | Successful |
Software Version | J.33 |
Device Used | XC9572XL-10-VQ44 |
Date | 4-10-2007, 1:57PM |
Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
---|---|---|---|---|
39/72 (55%) | 178/360 (50%) | 36/72 (50%) | 16/34 (48%) | 79/216 (37%) |
|
|
Signal mapped onto global clock net (GCK3) | clk |
Signal mapped onto global output enable net (GSR) | reset_b |
Macrocells in high performance mode (MCHP) | 0 |
Macrocells in low power mode (MCLP) | 39 |
Total macrocells used (MC) | 39 |