Equations

********** Mapped Logic **********
FDCPE_CCLK: FDCPE port map (CCLK,CCLK_D,clk,'0',NOT reset_b,clkdv(0));
     CCLK_D <= (clkdv(2) AND en_CCLK);
FTCPE_FPGA_ctrl1: FTCPE port map (FPGA_ctrl(1),cntr(13).EXP,clk,NOT reset_b,'0');
FTCPE_FPGA_ctrl4: FTCPE port map (FPGA_ctrl(4),clkdv(0),clk,NOT reset_b,'0');
FDCPE_MCLK: FDCPE port map (MCLK,MCLK_D,clk,NOT reset_b,'0',clkdv(0));
     MCLK_D <= (cntr(25) AND cntr(24) AND NOT clkdv(2) AND NOT MS_n);
FDCPE_MD: FDCPE port map (MD,MD_D,clk,NOT reset_b,'0');
     MD_D <= ((MW_n_OBUF$BUF0.EXP)
      OR (MD AND NOT clkdv(0))
      OR (NOT clkdv(2) AND MD AND NOT DONE)
      OR (MD AND NOT FPGA_ctrl(4) AND DONE)
      OR (FPGA_ctrl(4) AND clkdv(0) AND DONE AND FPGA_ctrl(0)));
MH_n <= '1';
FDCPE_MS_n: FDCPE port map (MS_n,NOT INIT_b,clk,'0',NOT reset_b,MS_n_CE);
     MS_n_CE <= (FPGA_ctrl(4) AND clkdv(0));
MW_n <= FPGA_ctrl(3);
PROG_b_I <= '0';
     PROG_b <= PROG_b_I when PROG_b_OE = '1' else 'Z';
     PROG_b_OE <= NOT cntr(25);
FTCPE_clkdv0: FTCPE port map (clkdv(0),'1',clk,NOT reset_b,'0');
FDCPE_clkdv2: FDCPE port map (clkdv(2),clkdv_D(2),clk,NOT reset_b,'0',clkdv(0));
     clkdv_D(2) <= ((FPGA_ctrl(4))
      OR (NOT en_CCLK AND FPGA_ctrl(2) AND DONE AND MS_n));
FTCPE_cntr0: FTCPE port map (cntr(0),cntr_T(0),clk,NOT reset_b,'0');
     cntr_T(0) <= ((NOT clkdv(2))
      OR (NOT clkdv(0))
      OR (FPGA_ctrl(1) AND cntr(25) AND cntr(24) AND cntr(22) AND
      cntr(23) AND FPGA_ctrl(2))
      OR (cntr(25) AND cntr(24) AND cntr(22) AND cntr(23) AND
      was_done AND FPGA_ctrl(2))
      OR (cntr(25) AND cntr(24) AND cntr(22) AND cntr(23) AND
      FPGA_ctrl(2) AND DONE));
FTCPE_cntr1: FTCPE port map (cntr(1),cntr_T(1),clk,NOT reset_b,'0');
     cntr_T(1) <= ((NOT clkdv(2))
      OR (NOT cntr(0))
      OR (NOT clkdv(0))
      OR (clkdv(2).EXP)
      OR (FPGA_ctrl(1) AND cntr(25) AND cntr(24) AND cntr(22) AND
      cntr(23) AND FPGA_ctrl(2))
      OR (cntr(25) AND cntr(24) AND cntr(22) AND cntr(23) AND
      FPGA_ctrl(2) AND DONE));
FTCPE_cntr2: FTCPE port map (cntr(2),cntr_T(2),clk,NOT reset_b,'0');
     cntr_T(2) <= ((cntr(12).EXP)
      OR (NOT cntr(25) AND clkdv(2) AND cntr(0) AND cntr(1) AND
      clkdv(0))
      OR (NOT cntr(24) AND clkdv(2) AND cntr(0) AND cntr(1) AND
      clkdv(0))
      OR (clkdv(2) AND cntr(0) AND cntr(1) AND NOT cntr(22) AND
      clkdv(0))
      OR (clkdv(2) AND cntr(0) AND cntr(1) AND NOT cntr(23) AND
      clkdv(0))
      OR (clkdv(2) AND cntr(0) AND cntr(1) AND NOT FPGA_ctrl(2) AND
      clkdv(0)));
FTCPE_cntr3: FTCPE port map (cntr(3),cntr_T(3),clk,NOT reset_b,'0');
     cntr_T(3) <= ((MS_n_OBUF.EXP)
      OR (NOT cntr(25) AND cntr(2) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND clkdv(0))
      OR (cntr(2) AND clkdv(2) AND cntr(0) AND cntr(1) AND
      NOT cntr(22) AND clkdv(0)));
FTCPE_cntr4: FTCPE port map (cntr(4),cntr_T(4),clk,NOT reset_b,'0');
     cntr_T(4) <= ((cntr(3).EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(22) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(23) AND clkdv(0)));
FTCPE_cntr5: FTCPE port map (cntr(5),cntr_T(5),clk,NOT reset_b,'0');
     cntr_T(5) <= ((cntr(4).EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(22) AND cntr(4) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(23) AND cntr(4) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND cntr(4) AND NOT FPGA_ctrl(2) AND clkdv(0)));
FTCPE_cntr6: FTCPE port map (cntr(6),cntr_T(6),clk,NOT reset_b,'0');
     cntr_T(6) <= ((cntr(7).EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(5) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(5) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND cntr(4) AND cntr(5) AND NOT FPGA_ctrl(2) AND clkdv(0)));
FTCPE_cntr7: FTCPE port map (cntr(7),cntr_T(7),clk,NOT reset_b,'0');
     cntr_T(7) <= ((cntr(8).EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND
      clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND
      clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(5) AND cntr(6) AND
      clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(5) AND cntr(6) AND
      clkdv(0)));
FTCPE_cntr8: FTCPE port map (cntr(8),cntr_T(8),clk,NOT reset_b,'0');
     cntr_T(8) <= ((cntr(9).EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND
      cntr(7) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND
      cntr(7) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(5) AND cntr(6) AND
      cntr(7) AND clkdv(0)));
FTCPE_cntr9: FTCPE port map (cntr(9),cntr_T(9),clk,NOT reset_b,'0');
     cntr_T(9) <= ((EXP12_.EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND
      cntr(7) AND cntr(8) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND
      cntr(7) AND cntr(8) AND clkdv(0)));
FTCPE_cntr10: FTCPE port map (cntr(10),cntr_T(10),clk,NOT reset_b,'0');
     cntr_T(10) <= ((EXP11_.EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND
      cntr(7) AND cntr(8) AND cntr(9) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND
      cntr(7) AND cntr(8) AND cntr(9) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(5) AND cntr(6) AND
      cntr(7) AND cntr(8) AND cntr(9) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(5) AND cntr(6) AND
      cntr(7) AND cntr(8) AND cntr(9) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND cntr(7) AND
      cntr(8) AND cntr(9) AND NOT FPGA_ctrl(2) AND clkdv(0)));
FTCPE_cntr11: FTCPE port map (cntr(11),cntr_T(11),clk,NOT reset_b,'0');
     cntr_T(11) <= ((MD_OBUF.EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(5) AND
      cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(5) AND
      cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(5) AND
      cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(10) AND cntr(5) AND
      cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND cntr(4) AND cntr(10) AND cntr(5) AND cntr(6) AND
      cntr(7) AND cntr(8) AND cntr(9) AND NOT FPGA_ctrl(2) AND clkdv(0)));
FTCPE_cntr12: FTCPE port map (cntr(12),cntr_T(12),clk,NOT reset_b,'0');
     cntr_T(12) <= ((MH_n_OBUF.EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(5) AND
      cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND
      clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(5) AND
      cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND
      clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(5) AND
      cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND
      clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(10) AND cntr(5) AND
      cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND
      clkdv(0)));
FTCPE_cntr13: FTCPE port map (cntr(13),cntr_T(13),clk,NOT reset_b,'0');
     cntr_T(13) <= ((EXP10_.EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND clkdv(0)));
FTCPE_cntr14: FTCPE port map (cntr(14),cntr_T(14),clk,NOT reset_b,'0');
     cntr_T(14) <= ((cntr(26).EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND clkdv(0)));
FTCPE_cntr15: FTCPE port map (cntr(15),cntr_T(15),clk,NOT reset_b,'0');
     cntr_T(15) <= ((cntr(14).EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND clkdv(0)));
FTCPE_cntr16: FTCPE port map (cntr(16),cntr_T(16),clk,NOT reset_b,'0');
     cntr_T(16) <= ((cntr(15).EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND clkdv(0)));
FTCPE_cntr17: FTCPE port map (cntr(17),cntr_T(17),clk,NOT reset_b,'0');
     cntr_T(17) <= ((cntr(16).EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      clkdv(0)));
FTCPE_cntr18: FTCPE port map (cntr(18),cntr_T(18),clk,NOT reset_b,'0');
     cntr_T(18) <= ((cntr(17).EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND cntr(5) AND
      cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND
      cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND cntr(17) AND
      NOT FPGA_ctrl(2) AND clkdv(0)));
FTCPE_cntr19: FTCPE port map (cntr(19),cntr_T(19),clk,NOT reset_b,'0');
     cntr_T(19) <= ((PROG_b_OBUFE.EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND cntr(18) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND cntr(18) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND cntr(18) AND clkdv(0)));
FTCPE_cntr20: FTCPE port map (cntr(20),cntr_T(20),clk,NOT reset_b,'0');
     cntr_T(20) <= ((cntr(19).EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND cntr(18) AND cntr(19) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND cntr(18) AND cntr(19) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND cntr(18) AND cntr(19) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND cntr(18) AND cntr(19) AND clkdv(0)));
FTCPE_cntr21: FTCPE port map (cntr(21),cntr_T(21),clk,NOT reset_b,'0');
     cntr_T(21) <= ((cntr(20).EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND cntr(5) AND
      cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND
      cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND cntr(17) AND
      cntr(18) AND cntr(19) AND cntr(20) AND NOT FPGA_ctrl(2) AND clkdv(0)));
FTCPE_cntr22: FTCPE port map (cntr(22),cntr_T(22),clk,NOT reset_b,'0');
     cntr_T(22) <= ((cntr(23).EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND cntr(21) AND
      clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND cntr(21) AND
      clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND cntr(21) AND
      clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND cntr(21) AND
      clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND cntr(5) AND
      cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND
      cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND cntr(17) AND
      cntr(18) AND cntr(19) AND cntr(20) AND cntr(21) AND NOT FPGA_ctrl(2) AND
      clkdv(0)));
FTCPE_cntr23: FTCPE port map (cntr(23),cntr_T(23),clk,NOT reset_b,'0');
     cntr_T(23) <= ((en_CCLK.EXP)
      OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(22) AND cntr(4) AND cntr(10) AND
      cntr(12) AND cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND
      cntr(9) AND cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND
      cntr(16) AND cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND
      cntr(21) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(22) AND cntr(4) AND cntr(10) AND
      cntr(12) AND cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND
      cntr(9) AND cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND
      cntr(16) AND cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND
      cntr(21) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND cntr(22) AND NOT cntr(23) AND cntr(4) AND cntr(10) AND
      cntr(12) AND cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND
      cntr(9) AND cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND
      cntr(16) AND cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND
      cntr(21) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND cntr(22) AND cntr(4) AND cntr(10) AND cntr(12) AND
      cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND
      cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND
      cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND cntr(21) AND
      NOT FPGA_ctrl(2) AND clkdv(0)));
FTCPE_cntr24: FTCPE port map (cntr(24),cntr_T(24),clk,NOT reset_b,'0');
     cntr_T(24) <= ((NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(22) AND cntr(23) AND cntr(4) AND
      cntr(10) AND cntr(12) AND cntr(5) AND cntr(6) AND cntr(7) AND
      cntr(8) AND cntr(9) AND cntr(11) AND cntr(13) AND cntr(14) AND
      cntr(15) AND cntr(16) AND cntr(17) AND cntr(18) AND cntr(19) AND
      cntr(20) AND cntr(21) AND clkdv(0))
      OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(22) AND cntr(23) AND cntr(4) AND
      cntr(10) AND cntr(12) AND cntr(5) AND cntr(6) AND cntr(7) AND
      cntr(8) AND cntr(9) AND cntr(11) AND cntr(13) AND cntr(14) AND
      cntr(15) AND cntr(16) AND cntr(17) AND cntr(18) AND cntr(19) AND
      cntr(20) AND cntr(21) AND clkdv(0))
      OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND
      cntr(1) AND cntr(22) AND cntr(23) AND cntr(4) AND cntr(10) AND
      cntr(12) AND cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND
      cntr(9) AND cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND
      cntr(16) AND cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND
      cntr(21) AND NOT FPGA_ctrl(2) AND clkdv(0))
      OR (NOT FPGA_ctrl(1) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(22) AND cntr(23) AND cntr(4) AND
      cntr(10) AND cntr(12) AND cntr(5) AND cntr(6) AND cntr(7) AND
      cntr(8) AND cntr(9) AND cntr(11) AND cntr(13) AND cntr(14) AND
      cntr(15) AND cntr(16) AND cntr(17) AND cntr(18) AND cntr(19) AND
      cntr(20) AND cntr(21) AND NOT was_done AND clkdv(0) AND NOT DONE));
FTCPE_cntr25: FTCPE port map (cntr(25),cntr_T(25),clk,NOT reset_b,'0');
     cntr_T(25) <= ((NOT cntr(25) AND cntr(24) AND cntr(2) AND cntr(3) AND
      clkdv(2) AND cntr(0) AND cntr(1) AND cntr(22) AND cntr(23) AND
      cntr(4) AND cntr(10) AND cntr(12) AND cntr(5) AND cntr(6) AND
      cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND cntr(13) AND
      cntr(14) AND cntr(15) AND cntr(16) AND cntr(17) AND cntr(18) AND
      cntr(19) AND cntr(20) AND cntr(21) AND clkdv(0))
      OR (cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND
      cntr(0) AND cntr(1) AND cntr(22) AND cntr(23) AND cntr(4) AND
      cntr(10) AND cntr(12) AND cntr(5) AND cntr(6) AND cntr(7) AND
      cntr(8) AND cntr(9) AND cntr(11) AND cntr(13) AND cntr(14) AND
      cntr(15) AND cntr(16) AND cntr(17) AND cntr(18) AND cntr(19) AND
      cntr(20) AND cntr(21) AND NOT FPGA_ctrl(2) AND clkdv(0))
      OR (NOT FPGA_ctrl(1) AND cntr(24) AND cntr(2) AND cntr(3) AND
      clkdv(2) AND cntr(0) AND cntr(1) AND cntr(22) AND cntr(23) AND
      cntr(4) AND cntr(10) AND cntr(12) AND cntr(5) AND cntr(6) AND
      cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND cntr(13) AND
      cntr(14) AND cntr(15) AND cntr(16) AND cntr(17) AND cntr(18) AND
      cntr(19) AND cntr(20) AND cntr(21) AND NOT was_done AND clkdv(0) AND
      NOT DONE));
FTCPE_en_CCLK: FTCPE port map (en_CCLK,en_CCLK_T,clk,NOT reset_b,'0');
     en_CCLK_T <= ((cntr(24).EXP)
      OR (NOT cntr(25) AND clkdv(2) AND en_CCLK AND clkdv(0))
      OR (NOT cntr(24) AND clkdv(2) AND en_CCLK AND clkdv(0))
      OR (clkdv(2) AND cntr(22) AND cntr(23) AND en_CCLK AND
      clkdv(0))
      OR (cntr(25) AND cntr(24) AND cntr(2) AND cntr(3) AND
      clkdv(2) AND cntr(1) AND NOT cntr(22) AND cntr(4) AND NOT en_CCLK AND
      clkdv(0)));
FTCPE_was_done: FTCPE port map (was_done,was_done_T,clk,NOT reset_b,'0');
     was_done_T <= ((NOT cntr(25) AND was_done AND clkdv(0))
      OR (cntr(25) AND NOT was_done AND clkdv(0) AND DONE));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);