Logic

Signal Name Total Pterms Total Inputs Function Block Macrocell Power Mode Slew Rate Pin Number Pin Type Pin Use Reg Init State
FPGA_ctrl<4> 1 1 FB1 MC6 LOW SLOW 41 I/O O RESET
CCLK 2 3 FB1 MC15 LOW SLOW 2 I/O O RESET
cntr<25> 3 32 FB2 MC3 LOW     (b) (b) RESET
cntr<24> 4 32 FB2 MC4 LOW     (b) (b) RESET
en_CCLK 5 11 FB2 MC5 LOW   30 I/O (b) RESET
cntr<23> 5 32 FB2 MC6 LOW   31 I/O (b) RESET
cntr<22> 6 32 FB2 MC7 LOW     (b) (b) RESET
cntr<21> 6 31 FB2 MC8 LOW   32 I/O (b) RESET
cntr<20> 6 30 FB2 MC9 LOW   33 I/O/GSR GSR RESET
cntr<19> 6 29 FB2 MC10 LOW     (b) (b) RESET
PROG_b 1 1 FB2 MC11 LOW SLOW 34 I/O/GTS2 O  
cntr<18> 6 28 FB2 MC12 LOW     (b) (b) RESET
cntr<17> 6 27 FB2 MC13 LOW     (b) (b) RESET
cntr<16> 6 26 FB2 MC14 LOW   36 I/O/GTS1 (b) RESET
cntr<15> 6 25 FB2 MC15 LOW   37 I/O I RESET
cntr<14> 6 24 FB2 MC16 LOW     (b) (b) RESET
FPGA_ctrl<1> 3 33 FB2 MC17 LOW SLOW 38 I/O O RESET
cntr<13> 6 23 FB2 MC18 LOW     (b) (b) RESET
cntr<0> 5 10 FB3 MC2 LOW   5 I/O (b) RESET
cntr<9> 6 19 FB3 MC4 LOW     (b) (b) RESET
cntr<8> 6 18 FB3 MC5 LOW   6 I/O (b) RESET
cntr<7> 6 17 FB3 MC6 LOW     (b) (b) RESET
cntr<6> 6 16 FB3 MC7 LOW     (b) (b) RESET
cntr<5> 6 15 FB3 MC8 LOW   7 I/O (b) RESET
cntr<4> 6 14 FB3 MC9 LOW   8 I/O (b) RESET
cntr<3> 6 13 FB3 MC10 LOW     (b) (b) RESET
MS_n 2 3 FB3 MC11 LOW SLOW 12 I/O O SET
cntr<2> 6 12 FB3 MC12 LOW     (b) (b) RESET
cntr<12> 6 22 FB3 MC13 LOW     (b) (b) RESET
MH_n 0 0 FB3 MC14 LOW SLOW 13 I/O O  
MW_n 1 1 FB3 MC15 LOW SLOW 14 I/O O  
MD 7 15 FB3 MC16 LOW SLOW 18 I/O O RESET
cntr<11> 6 21 FB3 MC17 LOW   16 I/O (b) RESET
cntr<10> 6 20 FB3 MC18 LOW     (b) (b) RESET
MCLK 2 5 FB4 MC2 LOW SLOW 19 I/O O RESET
clkdv<0> 0 0 FB4 MC15 LOW   27 I/O (b) RESET
was_done 2 4 FB4 MC16 LOW     (b) (b) RESET
clkdv<2> 3 6 FB4 MC17 LOW   28 I/O (b) RESET
cntr<1> 6 11 FB4 MC18 LOW     (b) (b) RESET