cpldfit:  version J.33                              Xilinx Inc.
                                  Fitter Report
Design Name: DCOL_conf                           Date:  4-10-2007,  1:57PM
Device Used: XC9572XL-10-VQ44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
39 /72  ( 54%) 178 /360  ( 49%) 79 /216 ( 37%)   36 /72  ( 50%) 16 /34  ( 47%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1           2/18        3/54        3/90       2/ 9
FB2          16/18       34/54       81/90       2/ 9
FB3          16/18       28/54       81/90       4/ 9
FB4           5/18       14/54       13/90       1/ 7
             -----       -----       -----      -----    
             39/72       79/216     178/360      9/34 

* - Resource is exhausted

** Global Control Resources **

Signal 'clk' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Signal 'reset_b' mapped onto global set/reset net GSR.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    5           5    |  I/O              :    12      28
Output        :    9           9    |  GCK/IO           :     2       3
Bidirectional :    0           0    |  GTS/IO           :     1       2
GCK           :    1           1    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    1           1    |
                 ----        ----
        Total     16          16

** Power Data **

There are 0 macrocells in high performance mode (MCHP).
There are 39 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 9 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
FPGA_ctrl<4>        1     1     FB1_6   41   I/O     O       LOW  SLOW RESET
CCLK                2     3     FB1_15  2    I/O     O       LOW  SLOW RESET
PROG_b              1     1     FB2_11  34   GTS/I/O O       LOW  SLOW 
FPGA_ctrl<1>        3     33    FB2_17  38   I/O     O       LOW  SLOW RESET
MS_n                2     3     FB3_11  12   I/O     O       LOW  SLOW SET
MH_n                0     0     FB3_14  13   I/O     O       LOW  SLOW 
MW_n                1     1     FB3_15  14   I/O     O       LOW  SLOW 
MD                  7     15    FB3_16  18   I/O     O       LOW  SLOW RESET
MCLK                2     5     FB4_2   19   I/O     O       LOW  SLOW RESET

** 30 Buried Nodes **

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
cntr<25>            3     32    FB2_3   LOW  RESET
cntr<24>            4     32    FB2_4   LOW  RESET
en_CCLK             5     11    FB2_5   LOW  RESET
cntr<23>            5     32    FB2_6   LOW  RESET
cntr<22>            6     32    FB2_7   LOW  RESET
cntr<21>            6     31    FB2_8   LOW  RESET
cntr<20>            6     30    FB2_9   LOW  RESET
cntr<19>            6     29    FB2_10  LOW  RESET
cntr<18>            6     28    FB2_12  LOW  RESET
cntr<17>            6     27    FB2_13  LOW  RESET
cntr<16>            6     26    FB2_14  LOW  RESET
cntr<15>            6     25    FB2_15  LOW  RESET
cntr<14>            6     24    FB2_16  LOW  RESET
cntr<13>            6     23    FB2_18  LOW  RESET
cntr<0>             5     10    FB3_2   LOW  RESET
cntr<9>             6     19    FB3_4   LOW  RESET
cntr<8>             6     18    FB3_5   LOW  RESET
cntr<7>             6     17    FB3_6   LOW  RESET
cntr<6>             6     16    FB3_7   LOW  RESET
cntr<5>             6     15    FB3_8   LOW  RESET
cntr<4>             6     14    FB3_9   LOW  RESET
cntr<3>             6     13    FB3_10  LOW  RESET
cntr<2>             6     12    FB3_12  LOW  RESET
cntr<12>            6     22    FB3_13  LOW  RESET
cntr<11>            6     21    FB3_17  LOW  RESET
cntr<10>            6     20    FB3_18  LOW  RESET
clkdv<0>            0     0     FB4_15  LOW  RESET
was_done            2     4     FB4_16  LOW  RESET
clkdv<2>            3     6     FB4_17  LOW  RESET
cntr<1>             6     11    FB4_18  LOW  RESET

** 7 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
FPGA_ctrl<2>        FB1_2   39   I/O     I
FPGA_ctrl<3>        FB1_5   40   I/O     I
INIT_b              FB1_8   42   I/O     I
DONE                FB1_11  44   GCK/I/O I
clk                 FB1_14  1    GCK/I/O GCK
reset_b             FB2_9   33   GSR/I/O GSR
FPGA_ctrl<0>        FB2_15  37   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               3/51
Number of signals used by logic mapping into function block:  3
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
(unused)              0       0     0   5     FB1_2   39    I/O     I
(unused)              0       0     0   5     FB1_3         (b)     
(unused)              0       0     0   5     FB1_4         (b)     
(unused)              0       0     0   5     FB1_5   40    I/O     I
FPGA_ctrl<4>          1       0     0   4     FB1_6   41    I/O     O
(unused)              0       0     0   5     FB1_7         (b)     
(unused)              0       0     0   5     FB1_8   42    I/O     I
(unused)              0       0     0   5     FB1_9   43    GCK/I/O 
(unused)              0       0     0   5     FB1_10        (b)     
(unused)              0       0     0   5     FB1_11  44    GCK/I/O I
(unused)              0       0     0   5     FB1_12        (b)     
(unused)              0       0     0   5     FB1_13        (b)     
(unused)              0       0     0   5     FB1_14  1     GCK/I/O GCK
CCLK                  2       0     0   3     FB1_15  2     I/O     O
(unused)              0       0     0   5     FB1_16        (b)     
(unused)              0       0     0   5     FB1_17  3     I/O     
(unused)              0       0     0   5     FB1_18        (b)     

Signals Used by Logic in Function Block
  1: clkdv<0>           2: clkdv<2>           3: en_CCLK 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
FPGA_ctrl<4>         X....................................... 1
CCLK                 XXX..................................... 3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               34/20
Number of signals used by logic mapping into function block:  34
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\4   1     FB2_1         (b)     (b)
(unused)              0       0     0   5     FB2_2   29    I/O     
cntr<25>              3       0     0   2     FB2_3         (b)     (b)
cntr<24>              4       0   \/1   0     FB2_4         (b)     (b)
en_CCLK               5       1<- \/1   0     FB2_5   30    I/O     (b)
cntr<23>              5       1<- \/1   0     FB2_6   31    I/O     (b)
cntr<22>              6       1<-   0   0     FB2_7         (b)     (b)
cntr<21>              6       1<-   0   0     FB2_8   32    I/O     (b)
cntr<20>              6       2<- /\1   0     FB2_9   33    GSR/I/O GSR
cntr<19>              6       3<- /\2   0     FB2_10        (b)     (b)
PROG_b                1       0   /\3   1     FB2_11  34    GTS/I/O O
cntr<18>              6       1<-   0   0     FB2_12        (b)     (b)
cntr<17>              6       2<- /\1   0     FB2_13        (b)     (b)
cntr<16>              6       3<- /\2   0     FB2_14  36    GTS/I/O (b)
cntr<15>              6       4<- /\3   0     FB2_15  37    I/O     I
cntr<14>              6       5<- /\4   0     FB2_16        (b)     (b)
FPGA_ctrl<1>          3       3<- /\5   0     FB2_17  38    I/O     O
cntr<13>              6       4<- /\3   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: DONE              13: cntr<15>          24: cntr<25> 
  2: FPGA_ctrl<1>      14: cntr<16>          25: cntr<2> 
  3: FPGA_ctrl<0>      15: cntr<17>          26: cntr<3> 
  4: FPGA_ctrl<2>      16: cntr<18>          27: cntr<4> 
  5: clkdv<0>          17: cntr<19>          28: cntr<5> 
  6: clkdv<2>          18: cntr<1>           29: cntr<6> 
  7: cntr<0>           19: cntr<20>          30: cntr<7> 
  8: cntr<10>          20: cntr<21>          31: cntr<8> 
  9: cntr<11>          21: cntr<22>          32: cntr<9> 
 10: cntr<12>          22: cntr<23>          33: en_CCLK 
 11: cntr<13>          23: cntr<24>          34: was_done 
 12: cntr<14>         

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
cntr<25>             XX.XXXXXXXXXXXXXXXXXXXXXXXXXXXXX.X...... 32
cntr<24>             XX.XXXXXXXXXXXXXXXXXXXXXXXXXXXXX.X...... 32
en_CCLK              ....XX...........X..XXXXXXX.....X....... 11
cntr<23>             XX.XXXXXXXXXXXXXXXXXXXXXXXXXXXXX.X...... 32
cntr<22>             XX.XXXXXXXXXXXXXXXXXXXXXXXXXXXXX.X...... 32
cntr<21>             XX.XXXXXXXXXXXXXXXX.XXXXXXXXXXXX.X...... 31
cntr<20>             XX.XXXXXXXXXXXXXXX..XXXXXXXXXXXX.X...... 30
cntr<19>             XX.XXXXXXXXXXXXX.X..XXXXXXXXXXXX.X...... 29
PROG_b               .......................X................ 1
cntr<18>             XX.XXXXXXXXXXXX..X..XXXXXXXXXXXX.X...... 28
cntr<17>             XX.XXXXXXXXXXX...X..XXXXXXXXXXXX.X...... 27
cntr<16>             XX.XXXXXXXXXX....X..XXXXXXXXXXXX.X...... 26
cntr<15>             XX.XXXXXXXXX.....X..XXXXXXXXXXXX.X...... 25
cntr<14>             XX.XXXXXXXX......X..XXXXXXXXXXXX.X...... 24
FPGA_ctrl<1>         XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX.X...... 33
cntr<13>             XX.XXXXXXX.......X..XXXXXXXXXXXX.X...... 23
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               28/26
Number of signals used by logic mapping into function block:  28
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\1   4     FB3_1         (b)     (b)
cntr<0>               5       0     0   0     FB3_2   5     I/O     (b)
(unused)              0       0   \/4   1     FB3_3         (b)     (b)
cntr<9>               6       4<- \/3   0     FB3_4         (b)     (b)
cntr<8>               6       3<- \/2   0     FB3_5   6     I/O     (b)
cntr<7>               6       2<- \/1   0     FB3_6         (b)     (b)
cntr<6>               6       1<-   0   0     FB3_7         (b)     (b)
cntr<5>               6       1<-   0   0     FB3_8   7     I/O     (b)
cntr<4>               6       2<- /\1   0     FB3_9   8     I/O     (b)
cntr<3>               6       3<- /\2   0     FB3_10        (b)     (b)
MS_n                  2       0   /\3   0     FB3_11  12    I/O     O
cntr<2>               6       1<-   0   0     FB3_12        (b)     (b)
cntr<12>              6       2<- /\1   0     FB3_13        (b)     (b)
MH_n                  0       0   /\2   3     FB3_14  13    I/O     O
MW_n                  1       0   \/3   1     FB3_15  14    I/O     O
MD                    7       3<- \/1   0     FB3_16  18    I/O     O
cntr<11>              6       1<-   0   0     FB3_17  16    I/O     (b)
cntr<10>              6       1<-   0   0     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: DONE              11: cntr<0>           20: cntr<3> 
  2: FPGA_ctrl<1>      12: cntr<10>          21: cntr<4> 
  3: FPGA_ctrl<4>      13: cntr<11>          22: cntr<5> 
  4: FPGA_ctrl<0>      14: cntr<1>           23: cntr<6> 
  5: FPGA_ctrl<2>      15: cntr<22>          24: cntr<7> 
  6: INIT_b            16: cntr<23>          25: cntr<8> 
  7: MD                17: cntr<24>          26: cntr<9> 
  8: FPGA_ctrl<3>      18: cntr<25>          27: en_CCLK 
  9: clkdv<0>          19: cntr<2>           28: was_done 
 10: clkdv<2>         

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
cntr<0>              XX..X...XX....XXXX.........X............ 10
cntr<9>              XX..X...XXX..XXXXXXXXXXXX..X............ 19
cntr<8>              XX..X...XXX..XXXXXXXXXXX...X............ 18
cntr<7>              XX..X...XXX..XXXXXXXXXX....X............ 17
cntr<6>              XX..X...XXX..XXXXXXXXX.....X............ 16
cntr<5>              XX..X...XXX..XXXXXXXX......X............ 15
cntr<4>              XX..X...XXX..XXXXXXX.......X............ 14
cntr<3>              XX..X...XXX..XXXXXX........X............ 13
MS_n                 ..X..X..X............................... 3
cntr<2>              XX..X...XXX..XXXXX.........X............ 12
cntr<12>             XX..X...XXXXXXXXXXXXXXXXXX.X............ 22
MH_n                 ........................................ 0
MW_n                 .......X................................ 1
MD                   XXXX..X.XXX..X..XXXXX.....X............. 15
cntr<11>             XX..X...XXXX.XXXXXXXXXXXXX.X............ 21
cntr<10>             XX..X...XXX..XXXXXXXXXXXXX.X............ 20
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               14/40
Number of signals used by logic mapping into function block:  14
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
MCLK                  2       0     0   3     FB4_2   19    I/O     O
(unused)              0       0     0   5     FB4_3         (b)     
(unused)              0       0     0   5     FB4_4         (b)     
(unused)              0       0     0   5     FB4_5   20    I/O     
(unused)              0       0     0   5     FB4_6         (b)     
(unused)              0       0     0   5     FB4_7         (b)     
(unused)              0       0     0   5     FB4_8   21    I/O     
(unused)              0       0     0   5     FB4_9         (b)     
(unused)              0       0     0   5     FB4_10        (b)     
(unused)              0       0     0   5     FB4_11  22    I/O     
(unused)              0       0     0   5     FB4_12        (b)     
(unused)              0       0     0   5     FB4_13        (b)     
(unused)              0       0     0   5     FB4_14  23    I/O     
clkdv<0>              0       0     0   5     FB4_15  27    I/O     (b)
was_done              2       0     0   3     FB4_16        (b)     (b)
clkdv<2>              3       0   \/1   1     FB4_17  28    I/O     (b)
cntr<1>               6       1<-   0   0     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: DONE               6: clkdv<0>          11: cntr<24> 
  2: FPGA_ctrl<1>       7: clkdv<2>          12: cntr<25> 
  3: FPGA_ctrl<4>       8: cntr<0>           13: en_CCLK 
  4: FPGA_ctrl<2>       9: cntr<22>          14: was_done 
  5: MS_n              10: cntr<23>         

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
MCLK                 ....XXX...XX............................ 5
clkdv<0>             ........................................ 0
was_done             X....X.....X.X.......................... 4
clkdv<2>             X.XXXX......X........................... 6
cntr<1>              XX.X.XXXXXXX.X.......................... 11
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********

FDCPE_CCLK: FDCPE port map (CCLK,CCLK_D,clk,'0',NOT reset_b,clkdv(0));
CCLK_D <= (clkdv(2) AND en_CCLK);







FTCPE_FPGA_ctrl1: FTCPE port map (FPGA_ctrl(1),cntr(13).EXP,clk,NOT reset_b,'0');

FTCPE_FPGA_ctrl4: FTCPE port map (FPGA_ctrl(4),clkdv(0),clk,NOT reset_b,'0');

FDCPE_MCLK: FDCPE port map (MCLK,MCLK_D,clk,NOT reset_b,'0',clkdv(0));
MCLK_D <= (cntr(25) AND cntr(24) AND NOT clkdv(2) AND NOT MS_n);

FDCPE_MD: FDCPE port map (MD,MD_D,clk,NOT reset_b,'0');
MD_D <= ((MW_n_OBUF$BUF0.EXP)
	OR (MD AND NOT clkdv(0))
	OR (NOT clkdv(2) AND MD AND NOT DONE)
	OR (MD AND NOT FPGA_ctrl(4) AND DONE)
	OR (FPGA_ctrl(4) AND clkdv(0) AND DONE AND FPGA_ctrl(0)));


MH_n <= '1';

FDCPE_MS_n: FDCPE port map (MS_n,NOT INIT_b,clk,'0',NOT reset_b,MS_n_CE);
MS_n_CE <= (FPGA_ctrl(4) AND clkdv(0));


MW_n <= FPGA_ctrl(3);


PROG_b_I <= '0';
PROG_b <= PROG_b_I when PROG_b_OE = '1' else 'Z';
PROG_b_OE <= NOT cntr(25);

FTCPE_clkdv0: FTCPE port map (clkdv(0),'1',clk,NOT reset_b,'0');

FDCPE_clkdv2: FDCPE port map (clkdv(2),clkdv_D(2),clk,NOT reset_b,'0',clkdv(0));
clkdv_D(2) <= ((FPGA_ctrl(4))
	OR (NOT en_CCLK AND FPGA_ctrl(2) AND DONE AND MS_n));

FTCPE_cntr0: FTCPE port map (cntr(0),cntr_T(0),clk,NOT reset_b,'0');
cntr_T(0) <= ((NOT clkdv(2))
	OR (NOT clkdv(0))
	OR (FPGA_ctrl(1) AND cntr(25) AND cntr(24) AND cntr(22) AND 
	cntr(23) AND FPGA_ctrl(2))
	OR (cntr(25) AND cntr(24) AND cntr(22) AND cntr(23) AND 
	was_done AND FPGA_ctrl(2))
	OR (cntr(25) AND cntr(24) AND cntr(22) AND cntr(23) AND 
	FPGA_ctrl(2) AND DONE));

FTCPE_cntr1: FTCPE port map (cntr(1),cntr_T(1),clk,NOT reset_b,'0');
cntr_T(1) <= ((NOT clkdv(2))
	OR (NOT cntr(0))
	OR (NOT clkdv(0))
	OR (clkdv(2).EXP)
	OR (FPGA_ctrl(1) AND cntr(25) AND cntr(24) AND cntr(22) AND 
	cntr(23) AND FPGA_ctrl(2))
	OR (cntr(25) AND cntr(24) AND cntr(22) AND cntr(23) AND 
	FPGA_ctrl(2) AND DONE));

FTCPE_cntr2: FTCPE port map (cntr(2),cntr_T(2),clk,NOT reset_b,'0');
cntr_T(2) <= ((cntr(12).EXP)
	OR (NOT cntr(25) AND clkdv(2) AND cntr(0) AND cntr(1) AND 
	clkdv(0))
	OR (NOT cntr(24) AND clkdv(2) AND cntr(0) AND cntr(1) AND 
	clkdv(0))
	OR (clkdv(2) AND cntr(0) AND cntr(1) AND NOT cntr(22) AND 
	clkdv(0))
	OR (clkdv(2) AND cntr(0) AND cntr(1) AND NOT cntr(23) AND 
	clkdv(0))
	OR (clkdv(2) AND cntr(0) AND cntr(1) AND NOT FPGA_ctrl(2) AND 
	clkdv(0)));

FTCPE_cntr3: FTCPE port map (cntr(3),cntr_T(3),clk,NOT reset_b,'0');
cntr_T(3) <= ((MS_n_OBUF.EXP)
	OR (NOT cntr(25) AND cntr(2) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND clkdv(0))
	OR (cntr(2) AND clkdv(2) AND cntr(0) AND cntr(1) AND 
	NOT cntr(22) AND clkdv(0)));

FTCPE_cntr4: FTCPE port map (cntr(4),cntr_T(4),clk,NOT reset_b,'0');
cntr_T(4) <= ((cntr(3).EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(22) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(23) AND clkdv(0)));

FTCPE_cntr5: FTCPE port map (cntr(5),cntr_T(5),clk,NOT reset_b,'0');
cntr_T(5) <= ((cntr(4).EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(22) AND cntr(4) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(23) AND cntr(4) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND cntr(4) AND NOT FPGA_ctrl(2) AND clkdv(0)));

FTCPE_cntr6: FTCPE port map (cntr(6),cntr_T(6),clk,NOT reset_b,'0');
cntr_T(6) <= ((cntr(7).EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(5) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(5) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND cntr(4) AND cntr(5) AND NOT FPGA_ctrl(2) AND clkdv(0)));

FTCPE_cntr7: FTCPE port map (cntr(7),cntr_T(7),clk,NOT reset_b,'0');
cntr_T(7) <= ((cntr(8).EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND 
	clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND 
	clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(5) AND cntr(6) AND 
	clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(5) AND cntr(6) AND 
	clkdv(0)));

FTCPE_cntr8: FTCPE port map (cntr(8),cntr_T(8),clk,NOT reset_b,'0');
cntr_T(8) <= ((cntr(9).EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND 
	cntr(7) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND 
	cntr(7) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(5) AND cntr(6) AND 
	cntr(7) AND clkdv(0)));

FTCPE_cntr9: FTCPE port map (cntr(9),cntr_T(9),clk,NOT reset_b,'0');
cntr_T(9) <= ((EXP12_.EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND 
	cntr(7) AND cntr(8) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND 
	cntr(7) AND cntr(8) AND clkdv(0)));

FTCPE_cntr10: FTCPE port map (cntr(10),cntr_T(10),clk,NOT reset_b,'0');
cntr_T(10) <= ((EXP11_.EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND 
	cntr(7) AND cntr(8) AND cntr(9) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND 
	cntr(7) AND cntr(8) AND cntr(9) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(5) AND cntr(6) AND 
	cntr(7) AND cntr(8) AND cntr(9) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(5) AND cntr(6) AND 
	cntr(7) AND cntr(8) AND cntr(9) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND cntr(4) AND cntr(5) AND cntr(6) AND cntr(7) AND 
	cntr(8) AND cntr(9) AND NOT FPGA_ctrl(2) AND clkdv(0)));

FTCPE_cntr11: FTCPE port map (cntr(11),cntr_T(11),clk,NOT reset_b,'0');
cntr_T(11) <= ((MD_OBUF.EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(5) AND 
	cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(5) AND 
	cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(5) AND 
	cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(10) AND cntr(5) AND 
	cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND cntr(4) AND cntr(10) AND cntr(5) AND cntr(6) AND 
	cntr(7) AND cntr(8) AND cntr(9) AND NOT FPGA_ctrl(2) AND clkdv(0)));

FTCPE_cntr12: FTCPE port map (cntr(12),cntr_T(12),clk,NOT reset_b,'0');
cntr_T(12) <= ((MH_n_OBUF.EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(5) AND 
	cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND 
	clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(5) AND 
	cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND 
	clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(5) AND 
	cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND 
	clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(10) AND cntr(5) AND 
	cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND 
	clkdv(0)));

FTCPE_cntr13: FTCPE port map (cntr(13),cntr_T(13),clk,NOT reset_b,'0');
cntr_T(13) <= ((EXP10_.EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND clkdv(0)));

FTCPE_cntr14: FTCPE port map (cntr(14),cntr_T(14),clk,NOT reset_b,'0');
cntr_T(14) <= ((cntr(26).EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND clkdv(0)));

FTCPE_cntr15: FTCPE port map (cntr(15),cntr_T(15),clk,NOT reset_b,'0');
cntr_T(15) <= ((cntr(14).EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND clkdv(0)));

FTCPE_cntr16: FTCPE port map (cntr(16),cntr_T(16),clk,NOT reset_b,'0');
cntr_T(16) <= ((cntr(15).EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND clkdv(0)));

FTCPE_cntr17: FTCPE port map (cntr(17),cntr_T(17),clk,NOT reset_b,'0');
cntr_T(17) <= ((cntr(16).EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	clkdv(0)));

FTCPE_cntr18: FTCPE port map (cntr(18),cntr_T(18),clk,NOT reset_b,'0');
cntr_T(18) <= ((cntr(17).EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND cntr(5) AND 
	cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND 
	cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND cntr(17) AND 
	NOT FPGA_ctrl(2) AND clkdv(0)));

FTCPE_cntr19: FTCPE port map (cntr(19),cntr_T(19),clk,NOT reset_b,'0');
cntr_T(19) <= ((PROG_b_OBUFE.EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND cntr(18) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND cntr(18) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND cntr(18) AND clkdv(0)));

FTCPE_cntr20: FTCPE port map (cntr(20),cntr_T(20),clk,NOT reset_b,'0');
cntr_T(20) <= ((cntr(19).EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND cntr(18) AND cntr(19) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND cntr(18) AND cntr(19) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND cntr(18) AND cntr(19) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND cntr(18) AND cntr(19) AND clkdv(0)));

FTCPE_cntr21: FTCPE port map (cntr(21),cntr_T(21),clk,NOT reset_b,'0');
cntr_T(21) <= ((cntr(20).EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND cntr(5) AND 
	cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND 
	cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND cntr(17) AND 
	cntr(18) AND cntr(19) AND cntr(20) AND NOT FPGA_ctrl(2) AND clkdv(0)));

FTCPE_cntr22: FTCPE port map (cntr(22),cntr_T(22),clk,NOT reset_b,'0');
cntr_T(22) <= ((cntr(23).EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND cntr(21) AND 
	clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND cntr(21) AND 
	clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(22) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND cntr(21) AND 
	clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND NOT cntr(23) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND cntr(21) AND 
	clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND cntr(4) AND cntr(10) AND cntr(12) AND cntr(5) AND 
	cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND 
	cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND cntr(17) AND 
	cntr(18) AND cntr(19) AND cntr(20) AND cntr(21) AND NOT FPGA_ctrl(2) AND 
	clkdv(0)));

FTCPE_cntr23: FTCPE port map (cntr(23),cntr_T(23),clk,NOT reset_b,'0');
cntr_T(23) <= ((en_CCLK.EXP)
	OR (NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(22) AND cntr(4) AND cntr(10) AND 
	cntr(12) AND cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND 
	cntr(9) AND cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND 
	cntr(16) AND cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND 
	cntr(21) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(22) AND cntr(4) AND cntr(10) AND 
	cntr(12) AND cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND 
	cntr(9) AND cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND 
	cntr(16) AND cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND 
	cntr(21) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND cntr(22) AND NOT cntr(23) AND cntr(4) AND cntr(10) AND 
	cntr(12) AND cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND 
	cntr(9) AND cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND 
	cntr(16) AND cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND 
	cntr(21) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND cntr(22) AND cntr(4) AND cntr(10) AND cntr(12) AND 
	cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND cntr(9) AND 
	cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND cntr(16) AND 
	cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND cntr(21) AND 
	NOT FPGA_ctrl(2) AND clkdv(0)));

FTCPE_cntr24: FTCPE port map (cntr(24),cntr_T(24),clk,NOT reset_b,'0');
cntr_T(24) <= ((NOT cntr(25) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(22) AND cntr(23) AND cntr(4) AND 
	cntr(10) AND cntr(12) AND cntr(5) AND cntr(6) AND cntr(7) AND 
	cntr(8) AND cntr(9) AND cntr(11) AND cntr(13) AND cntr(14) AND 
	cntr(15) AND cntr(16) AND cntr(17) AND cntr(18) AND cntr(19) AND 
	cntr(20) AND cntr(21) AND clkdv(0))
	OR (NOT cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(22) AND cntr(23) AND cntr(4) AND 
	cntr(10) AND cntr(12) AND cntr(5) AND cntr(6) AND cntr(7) AND 
	cntr(8) AND cntr(9) AND cntr(11) AND cntr(13) AND cntr(14) AND 
	cntr(15) AND cntr(16) AND cntr(17) AND cntr(18) AND cntr(19) AND 
	cntr(20) AND cntr(21) AND clkdv(0))
	OR (cntr(2) AND cntr(3) AND clkdv(2) AND cntr(0) AND 
	cntr(1) AND cntr(22) AND cntr(23) AND cntr(4) AND cntr(10) AND 
	cntr(12) AND cntr(5) AND cntr(6) AND cntr(7) AND cntr(8) AND 
	cntr(9) AND cntr(11) AND cntr(13) AND cntr(14) AND cntr(15) AND 
	cntr(16) AND cntr(17) AND cntr(18) AND cntr(19) AND cntr(20) AND 
	cntr(21) AND NOT FPGA_ctrl(2) AND clkdv(0))
	OR (NOT FPGA_ctrl(1) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(22) AND cntr(23) AND cntr(4) AND 
	cntr(10) AND cntr(12) AND cntr(5) AND cntr(6) AND cntr(7) AND 
	cntr(8) AND cntr(9) AND cntr(11) AND cntr(13) AND cntr(14) AND 
	cntr(15) AND cntr(16) AND cntr(17) AND cntr(18) AND cntr(19) AND 
	cntr(20) AND cntr(21) AND NOT was_done AND clkdv(0) AND NOT DONE));

FTCPE_cntr25: FTCPE port map (cntr(25),cntr_T(25),clk,NOT reset_b,'0');
cntr_T(25) <= ((NOT cntr(25) AND cntr(24) AND cntr(2) AND cntr(3) AND 
	clkdv(2) AND cntr(0) AND cntr(1) AND cntr(22) AND cntr(23) AND 
	cntr(4) AND cntr(10) AND cntr(12) AND cntr(5) AND cntr(6) AND 
	cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND cntr(13) AND 
	cntr(14) AND cntr(15) AND cntr(16) AND cntr(17) AND cntr(18) AND 
	cntr(19) AND cntr(20) AND cntr(21) AND clkdv(0))
	OR (cntr(24) AND cntr(2) AND cntr(3) AND clkdv(2) AND 
	cntr(0) AND cntr(1) AND cntr(22) AND cntr(23) AND cntr(4) AND 
	cntr(10) AND cntr(12) AND cntr(5) AND cntr(6) AND cntr(7) AND 
	cntr(8) AND cntr(9) AND cntr(11) AND cntr(13) AND cntr(14) AND 
	cntr(15) AND cntr(16) AND cntr(17) AND cntr(18) AND cntr(19) AND 
	cntr(20) AND cntr(21) AND NOT FPGA_ctrl(2) AND clkdv(0))
	OR (NOT FPGA_ctrl(1) AND cntr(24) AND cntr(2) AND cntr(3) AND 
	clkdv(2) AND cntr(0) AND cntr(1) AND cntr(22) AND cntr(23) AND 
	cntr(4) AND cntr(10) AND cntr(12) AND cntr(5) AND cntr(6) AND 
	cntr(7) AND cntr(8) AND cntr(9) AND cntr(11) AND cntr(13) AND 
	cntr(14) AND cntr(15) AND cntr(16) AND cntr(17) AND cntr(18) AND 
	cntr(19) AND cntr(20) AND cntr(21) AND NOT was_done AND clkdv(0) AND 
	NOT DONE));

FTCPE_en_CCLK: FTCPE port map (en_CCLK,en_CCLK_T,clk,NOT reset_b,'0');
en_CCLK_T <= ((cntr(24).EXP)
	OR (NOT cntr(25) AND clkdv(2) AND en_CCLK AND clkdv(0))
	OR (NOT cntr(24) AND clkdv(2) AND en_CCLK AND clkdv(0))
	OR (clkdv(2) AND cntr(22) AND cntr(23) AND en_CCLK AND 
	clkdv(0))
	OR (cntr(25) AND cntr(24) AND cntr(2) AND cntr(3) AND 
	clkdv(2) AND cntr(1) AND NOT cntr(22) AND cntr(4) AND NOT en_CCLK AND 
	clkdv(0)));

FTCPE_was_done: FTCPE port map (was_done,was_done_T,clk,NOT reset_b,'0');
was_done_T <= ((NOT cntr(25) AND was_done AND clkdv(0))
	OR (cntr(25) AND NOT was_done AND clkdv(0) AND DONE));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572XL-10-VQ44


   --------------------------------  
  /44 43 42 41 40 39 38 37 36 35 34 \
 | 1                             33 | 
 | 2                             32 | 
 | 3                             31 | 
 | 4                             30 | 
 | 5        XC9572XL-10-VQ44     29 | 
 | 6                             28 | 
 | 7                             27 | 
 | 8                             26 | 
 | 9                             25 | 
 | 10                            24 | 
 | 11                            23 | 
 \ 12 13 14 15 16 17 18 19 20 21 22 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 clk                              23 PGND                          
  2 CCLK                             24 TDO                           
  3 PGND                             25 GND                           
  4 GND                              26 VCC                           
  5 PGND                             27 PGND                          
  6 PGND                             28 PGND                          
  7 PGND                             29 PGND                          
  8 PGND                             30 PGND                          
  9 TDI                              31 PGND                          
 10 TMS                              32 PGND                          
 11 TCK                              33 reset_b                       
 12 MS_n                             34 PROG_b                        
 13 MH_n                             35 VCC                           
 14 MW_n                             36 PGND                          
 15 VCC                              37 FPGA_ctrl<0>                  
 16 PGND                             38 FPGA_ctrl<1>                  
 17 GND                              39 FPGA_ctrl<2>                  
 18 MD                               40 FPGA_ctrl<3>                  
 19 MCLK                             41 FPGA_ctrl<4>                  
 20 PGND                             42 INIT_b                        
 21 PGND                             43 PGND                          
 22 PGND                             44 DONE                          


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-10-VQ44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : SLOW
Power Mode                                  : AUTO
Ground on Unused IOs                        : ON
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 50