Design Name | DCOL_conf |
Device, Speed (SpeedFile Version) | XC9572XL, -10 (3.0) |
Date Created | Tue Apr 10 13:57:11 2007 |
Created By | Timing Report Generator: version J.33 |
Copyright | Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. |
Performance Summary | |
---|---|
Min. Clock Period | 16.500 ns. |
Max. Clock Frequency (fSYSTEM) | 60.606 MHz. |
Limited by Cycle Time for clk | |
Clock to Setup (tCYC) | 16.500 ns. |
Pad to Pad Delay (tPD) | 20.000 ns. |
Setup to Clock at the Pad (tSU) | 13.000 ns. |
Clock Pad to Output Pad Delay (tCO) | 14.500 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS_clk | 16.6 | 16.5 | 599 | 0 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
FPGA_ctrl<1>.Q to FPGA_ctrl<1>.D | 16.600 | 16.500 | 0.100 |
FPGA_ctrl<1>.Q to MD.D | 16.600 | 16.500 | 0.100 |
FPGA_ctrl<1>.Q to cntr<10>.D | 16.600 | 16.500 | 0.100 |
Clock | fEXT (MHz) | Reason |
---|---|---|
clk | 60.606 | Limited by Cycle Time for clk |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
DONE | 13.000 | 0.000 |
FPGA_ctrl<0> | 13.000 | 0.000 |
FPGA_ctrl<2> | 13.000 | 0.000 |
INIT_b | 12.000 | 0.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
PROG_b | 14.500 |
CCLK | 10.300 |
FPGA_ctrl<1> | 10.300 |
FPGA_ctrl<4> | 10.300 |
MCLK | 10.300 |
MD | 10.300 |
MS_n | 10.300 |
Source | Destination | Delay |
---|---|---|
FPGA_ctrl<1>.Q | FPGA_ctrl<1>.D | 16.500 |
FPGA_ctrl<1>.Q | MD.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<10>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<11>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<12>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<13>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<14>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<15>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<16>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<17>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<18>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<19>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<20>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<21>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<22>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<23>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<2>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<3>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<4>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<5>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<6>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<7>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<8>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<9>.D | 16.500 |
clkdv<0>.Q | FPGA_ctrl<1>.D | 16.500 |
clkdv<0>.Q | MD.D | 16.500 |
clkdv<0>.Q | cntr<10>.D | 16.500 |
clkdv<0>.Q | cntr<11>.D | 16.500 |
clkdv<0>.Q | cntr<12>.D | 16.500 |
clkdv<0>.Q | cntr<13>.D | 16.500 |
clkdv<0>.Q | cntr<14>.D | 16.500 |
clkdv<0>.Q | cntr<15>.D | 16.500 |
clkdv<0>.Q | cntr<16>.D | 16.500 |
clkdv<0>.Q | cntr<17>.D | 16.500 |
clkdv<0>.Q | cntr<18>.D | 16.500 |
clkdv<0>.Q | cntr<19>.D | 16.500 |
clkdv<0>.Q | cntr<20>.D | 16.500 |
clkdv<0>.Q | cntr<21>.D | 16.500 |
clkdv<0>.Q | cntr<22>.D | 16.500 |
clkdv<0>.Q | cntr<23>.D | 16.500 |
clkdv<0>.Q | cntr<2>.D | 16.500 |
clkdv<0>.Q | cntr<3>.D | 16.500 |
clkdv<0>.Q | cntr<4>.D | 16.500 |
clkdv<0>.Q | cntr<5>.D | 16.500 |
clkdv<0>.Q | cntr<6>.D | 16.500 |
clkdv<0>.Q | cntr<7>.D | 16.500 |
clkdv<0>.Q | cntr<8>.D | 16.500 |
clkdv<0>.Q | cntr<9>.D | 16.500 |
clkdv<0>.Q | en_CCLK.D | 16.500 |
clkdv<2>.Q | FPGA_ctrl<1>.D | 16.500 |
clkdv<2>.Q | MD.D | 16.500 |
clkdv<2>.Q | cntr<10>.D | 16.500 |
clkdv<2>.Q | cntr<11>.D | 16.500 |
clkdv<2>.Q | cntr<12>.D | 16.500 |
clkdv<2>.Q | cntr<13>.D | 16.500 |
clkdv<2>.Q | cntr<14>.D | 16.500 |
clkdv<2>.Q | cntr<15>.D | 16.500 |
clkdv<2>.Q | cntr<16>.D | 16.500 |
clkdv<2>.Q | cntr<17>.D | 16.500 |
clkdv<2>.Q | cntr<18>.D | 16.500 |
clkdv<2>.Q | cntr<19>.D | 16.500 |
clkdv<2>.Q | cntr<20>.D | 16.500 |
clkdv<2>.Q | cntr<21>.D | 16.500 |
clkdv<2>.Q | cntr<22>.D | 16.500 |
clkdv<2>.Q | cntr<23>.D | 16.500 |
clkdv<2>.Q | cntr<2>.D | 16.500 |
clkdv<2>.Q | cntr<3>.D | 16.500 |
clkdv<2>.Q | cntr<4>.D | 16.500 |
clkdv<2>.Q | cntr<5>.D | 16.500 |
clkdv<2>.Q | cntr<6>.D | 16.500 |
clkdv<2>.Q | cntr<7>.D | 16.500 |
clkdv<2>.Q | cntr<8>.D | 16.500 |
clkdv<2>.Q | cntr<9>.D | 16.500 |
clkdv<2>.Q | en_CCLK.D | 16.500 |
cntr<0>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<0>.Q | MD.D | 16.500 |
cntr<0>.Q | cntr<10>.D | 16.500 |
cntr<0>.Q | cntr<11>.D | 16.500 |
cntr<0>.Q | cntr<12>.D | 16.500 |
cntr<0>.Q | cntr<13>.D | 16.500 |
cntr<0>.Q | cntr<14>.D | 16.500 |
cntr<0>.Q | cntr<15>.D | 16.500 |
cntr<0>.Q | cntr<16>.D | 16.500 |
cntr<0>.Q | cntr<17>.D | 16.500 |
cntr<0>.Q | cntr<18>.D | 16.500 |
cntr<0>.Q | cntr<19>.D | 16.500 |
cntr<0>.Q | cntr<20>.D | 16.500 |
cntr<0>.Q | cntr<21>.D | 16.500 |
cntr<0>.Q | cntr<22>.D | 16.500 |
cntr<0>.Q | cntr<23>.D | 16.500 |
cntr<0>.Q | cntr<2>.D | 16.500 |
cntr<0>.Q | cntr<3>.D | 16.500 |
cntr<0>.Q | cntr<4>.D | 16.500 |
cntr<0>.Q | cntr<5>.D | 16.500 |
cntr<0>.Q | cntr<6>.D | 16.500 |
cntr<0>.Q | cntr<7>.D | 16.500 |
cntr<0>.Q | cntr<8>.D | 16.500 |
cntr<0>.Q | cntr<9>.D | 16.500 |
cntr<10>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<10>.Q | cntr<11>.D | 16.500 |
cntr<10>.Q | cntr<12>.D | 16.500 |
cntr<10>.Q | cntr<13>.D | 16.500 |
cntr<10>.Q | cntr<14>.D | 16.500 |
cntr<10>.Q | cntr<15>.D | 16.500 |
cntr<10>.Q | cntr<16>.D | 16.500 |
cntr<10>.Q | cntr<17>.D | 16.500 |
cntr<10>.Q | cntr<18>.D | 16.500 |
cntr<10>.Q | cntr<19>.D | 16.500 |
cntr<10>.Q | cntr<20>.D | 16.500 |
cntr<10>.Q | cntr<21>.D | 16.500 |
cntr<10>.Q | cntr<22>.D | 16.500 |
cntr<10>.Q | cntr<23>.D | 16.500 |
cntr<11>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<11>.Q | cntr<12>.D | 16.500 |
cntr<11>.Q | cntr<13>.D | 16.500 |
cntr<11>.Q | cntr<14>.D | 16.500 |
cntr<11>.Q | cntr<15>.D | 16.500 |
cntr<11>.Q | cntr<16>.D | 16.500 |
cntr<11>.Q | cntr<17>.D | 16.500 |
cntr<11>.Q | cntr<18>.D | 16.500 |
cntr<11>.Q | cntr<19>.D | 16.500 |
cntr<11>.Q | cntr<20>.D | 16.500 |
cntr<11>.Q | cntr<21>.D | 16.500 |
cntr<11>.Q | cntr<22>.D | 16.500 |
cntr<11>.Q | cntr<23>.D | 16.500 |
cntr<12>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<12>.Q | cntr<13>.D | 16.500 |
cntr<12>.Q | cntr<14>.D | 16.500 |
cntr<12>.Q | cntr<15>.D | 16.500 |
cntr<12>.Q | cntr<16>.D | 16.500 |
cntr<12>.Q | cntr<17>.D | 16.500 |
cntr<12>.Q | cntr<18>.D | 16.500 |
cntr<12>.Q | cntr<19>.D | 16.500 |
cntr<12>.Q | cntr<20>.D | 16.500 |
cntr<12>.Q | cntr<21>.D | 16.500 |
cntr<12>.Q | cntr<22>.D | 16.500 |
cntr<12>.Q | cntr<23>.D | 16.500 |
cntr<13>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<13>.Q | cntr<14>.D | 16.500 |
cntr<13>.Q | cntr<15>.D | 16.500 |
cntr<13>.Q | cntr<16>.D | 16.500 |
cntr<13>.Q | cntr<17>.D | 16.500 |
cntr<13>.Q | cntr<18>.D | 16.500 |
cntr<13>.Q | cntr<19>.D | 16.500 |
cntr<13>.Q | cntr<20>.D | 16.500 |
cntr<13>.Q | cntr<21>.D | 16.500 |
cntr<13>.Q | cntr<22>.D | 16.500 |
cntr<13>.Q | cntr<23>.D | 16.500 |
cntr<14>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<14>.Q | cntr<15>.D | 16.500 |
cntr<14>.Q | cntr<16>.D | 16.500 |
cntr<14>.Q | cntr<17>.D | 16.500 |
cntr<14>.Q | cntr<18>.D | 16.500 |
cntr<14>.Q | cntr<19>.D | 16.500 |
cntr<14>.Q | cntr<20>.D | 16.500 |
cntr<14>.Q | cntr<21>.D | 16.500 |
cntr<14>.Q | cntr<22>.D | 16.500 |
cntr<14>.Q | cntr<23>.D | 16.500 |
cntr<15>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<15>.Q | cntr<16>.D | 16.500 |
cntr<15>.Q | cntr<17>.D | 16.500 |
cntr<15>.Q | cntr<18>.D | 16.500 |
cntr<15>.Q | cntr<19>.D | 16.500 |
cntr<15>.Q | cntr<20>.D | 16.500 |
cntr<15>.Q | cntr<21>.D | 16.500 |
cntr<15>.Q | cntr<22>.D | 16.500 |
cntr<15>.Q | cntr<23>.D | 16.500 |
cntr<16>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<16>.Q | cntr<17>.D | 16.500 |
cntr<16>.Q | cntr<18>.D | 16.500 |
cntr<16>.Q | cntr<19>.D | 16.500 |
cntr<16>.Q | cntr<20>.D | 16.500 |
cntr<16>.Q | cntr<21>.D | 16.500 |
cntr<16>.Q | cntr<22>.D | 16.500 |
cntr<16>.Q | cntr<23>.D | 16.500 |
cntr<17>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<17>.Q | cntr<18>.D | 16.500 |
cntr<17>.Q | cntr<19>.D | 16.500 |
cntr<17>.Q | cntr<20>.D | 16.500 |
cntr<17>.Q | cntr<21>.D | 16.500 |
cntr<17>.Q | cntr<22>.D | 16.500 |
cntr<17>.Q | cntr<23>.D | 16.500 |
cntr<18>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<18>.Q | cntr<19>.D | 16.500 |
cntr<18>.Q | cntr<20>.D | 16.500 |
cntr<18>.Q | cntr<21>.D | 16.500 |
cntr<18>.Q | cntr<22>.D | 16.500 |
cntr<18>.Q | cntr<23>.D | 16.500 |
cntr<19>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<19>.Q | cntr<20>.D | 16.500 |
cntr<19>.Q | cntr<21>.D | 16.500 |
cntr<19>.Q | cntr<22>.D | 16.500 |
cntr<19>.Q | cntr<23>.D | 16.500 |
cntr<1>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<1>.Q | MD.D | 16.500 |
cntr<1>.Q | cntr<10>.D | 16.500 |
cntr<1>.Q | cntr<11>.D | 16.500 |
cntr<1>.Q | cntr<12>.D | 16.500 |
cntr<1>.Q | cntr<13>.D | 16.500 |
cntr<1>.Q | cntr<14>.D | 16.500 |
cntr<1>.Q | cntr<15>.D | 16.500 |
cntr<1>.Q | cntr<16>.D | 16.500 |
cntr<1>.Q | cntr<17>.D | 16.500 |
cntr<1>.Q | cntr<18>.D | 16.500 |
cntr<1>.Q | cntr<19>.D | 16.500 |
cntr<1>.Q | cntr<20>.D | 16.500 |
cntr<1>.Q | cntr<21>.D | 16.500 |
cntr<1>.Q | cntr<22>.D | 16.500 |
cntr<1>.Q | cntr<23>.D | 16.500 |
cntr<1>.Q | cntr<2>.D | 16.500 |
cntr<1>.Q | cntr<3>.D | 16.500 |
cntr<1>.Q | cntr<4>.D | 16.500 |
cntr<1>.Q | cntr<5>.D | 16.500 |
cntr<1>.Q | cntr<6>.D | 16.500 |
cntr<1>.Q | cntr<7>.D | 16.500 |
cntr<1>.Q | cntr<8>.D | 16.500 |
cntr<1>.Q | cntr<9>.D | 16.500 |
cntr<1>.Q | en_CCLK.D | 16.500 |
cntr<20>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<20>.Q | cntr<21>.D | 16.500 |
cntr<20>.Q | cntr<22>.D | 16.500 |
cntr<20>.Q | cntr<23>.D | 16.500 |
cntr<21>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<21>.Q | cntr<22>.D | 16.500 |
cntr<21>.Q | cntr<23>.D | 16.500 |
cntr<22>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<22>.Q | cntr<13>.D | 16.500 |
cntr<22>.Q | cntr<14>.D | 16.500 |
cntr<22>.Q | cntr<15>.D | 16.500 |
cntr<22>.Q | cntr<1>.D | 16.500 |
cntr<22>.Q | cntr<23>.D | 16.500 |
cntr<22>.Q | cntr<9>.D | 16.500 |
cntr<23>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<23>.Q | cntr<13>.D | 16.500 |
cntr<23>.Q | cntr<14>.D | 16.500 |
cntr<23>.Q | cntr<15>.D | 16.500 |
cntr<23>.Q | cntr<16>.D | 16.500 |
cntr<23>.Q | cntr<19>.D | 16.500 |
cntr<23>.Q | cntr<1>.D | 16.500 |
cntr<23>.Q | cntr<3>.D | 16.500 |
cntr<23>.Q | cntr<8>.D | 16.500 |
cntr<23>.Q | cntr<9>.D | 16.500 |
cntr<23>.Q | en_CCLK.D | 16.500 |
cntr<24>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<24>.Q | MD.D | 16.500 |
cntr<24>.Q | cntr<14>.D | 16.500 |
cntr<24>.Q | cntr<1>.D | 16.500 |
cntr<24>.Q | en_CCLK.D | 16.500 |
cntr<25>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<25>.Q | MD.D | 16.500 |
cntr<25>.Q | cntr<1>.D | 16.500 |
cntr<25>.Q | en_CCLK.D | 16.500 |
cntr<2>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<2>.Q | MD.D | 16.500 |
cntr<2>.Q | cntr<10>.D | 16.500 |
cntr<2>.Q | cntr<11>.D | 16.500 |
cntr<2>.Q | cntr<12>.D | 16.500 |
cntr<2>.Q | cntr<13>.D | 16.500 |
cntr<2>.Q | cntr<14>.D | 16.500 |
cntr<2>.Q | cntr<15>.D | 16.500 |
cntr<2>.Q | cntr<16>.D | 16.500 |
cntr<2>.Q | cntr<17>.D | 16.500 |
cntr<2>.Q | cntr<18>.D | 16.500 |
cntr<2>.Q | cntr<19>.D | 16.500 |
cntr<2>.Q | cntr<20>.D | 16.500 |
cntr<2>.Q | cntr<21>.D | 16.500 |
cntr<2>.Q | cntr<22>.D | 16.500 |
cntr<2>.Q | cntr<23>.D | 16.500 |
cntr<2>.Q | cntr<3>.D | 16.500 |
cntr<2>.Q | cntr<4>.D | 16.500 |
cntr<2>.Q | cntr<5>.D | 16.500 |
cntr<2>.Q | cntr<6>.D | 16.500 |
cntr<2>.Q | cntr<7>.D | 16.500 |
cntr<2>.Q | cntr<8>.D | 16.500 |
cntr<2>.Q | cntr<9>.D | 16.500 |
cntr<2>.Q | en_CCLK.D | 16.500 |
cntr<3>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<3>.Q | MD.D | 16.500 |
cntr<3>.Q | cntr<10>.D | 16.500 |
cntr<3>.Q | cntr<11>.D | 16.500 |
cntr<3>.Q | cntr<12>.D | 16.500 |
cntr<3>.Q | cntr<13>.D | 16.500 |
cntr<3>.Q | cntr<14>.D | 16.500 |
cntr<3>.Q | cntr<15>.D | 16.500 |
cntr<3>.Q | cntr<16>.D | 16.500 |
cntr<3>.Q | cntr<17>.D | 16.500 |
cntr<3>.Q | cntr<18>.D | 16.500 |
cntr<3>.Q | cntr<19>.D | 16.500 |
cntr<3>.Q | cntr<20>.D | 16.500 |
cntr<3>.Q | cntr<21>.D | 16.500 |
cntr<3>.Q | cntr<22>.D | 16.500 |
cntr<3>.Q | cntr<23>.D | 16.500 |
cntr<3>.Q | cntr<4>.D | 16.500 |
cntr<3>.Q | cntr<5>.D | 16.500 |
cntr<3>.Q | cntr<6>.D | 16.500 |
cntr<3>.Q | cntr<7>.D | 16.500 |
cntr<3>.Q | cntr<8>.D | 16.500 |
cntr<3>.Q | cntr<9>.D | 16.500 |
cntr<3>.Q | en_CCLK.D | 16.500 |
cntr<4>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<4>.Q | MD.D | 16.500 |
cntr<4>.Q | cntr<10>.D | 16.500 |
cntr<4>.Q | cntr<11>.D | 16.500 |
cntr<4>.Q | cntr<12>.D | 16.500 |
cntr<4>.Q | cntr<13>.D | 16.500 |
cntr<4>.Q | cntr<14>.D | 16.500 |
cntr<4>.Q | cntr<15>.D | 16.500 |
cntr<4>.Q | cntr<16>.D | 16.500 |
cntr<4>.Q | cntr<17>.D | 16.500 |
cntr<4>.Q | cntr<18>.D | 16.500 |
cntr<4>.Q | cntr<19>.D | 16.500 |
cntr<4>.Q | cntr<20>.D | 16.500 |
cntr<4>.Q | cntr<21>.D | 16.500 |
cntr<4>.Q | cntr<22>.D | 16.500 |
cntr<4>.Q | cntr<23>.D | 16.500 |
cntr<4>.Q | cntr<5>.D | 16.500 |
cntr<4>.Q | cntr<6>.D | 16.500 |
cntr<4>.Q | cntr<7>.D | 16.500 |
cntr<4>.Q | cntr<8>.D | 16.500 |
cntr<4>.Q | cntr<9>.D | 16.500 |
cntr<4>.Q | en_CCLK.D | 16.500 |
cntr<5>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<5>.Q | cntr<10>.D | 16.500 |
cntr<5>.Q | cntr<11>.D | 16.500 |
cntr<5>.Q | cntr<12>.D | 16.500 |
cntr<5>.Q | cntr<13>.D | 16.500 |
cntr<5>.Q | cntr<14>.D | 16.500 |
cntr<5>.Q | cntr<15>.D | 16.500 |
cntr<5>.Q | cntr<16>.D | 16.500 |
cntr<5>.Q | cntr<17>.D | 16.500 |
cntr<5>.Q | cntr<18>.D | 16.500 |
cntr<5>.Q | cntr<19>.D | 16.500 |
cntr<5>.Q | cntr<20>.D | 16.500 |
cntr<5>.Q | cntr<21>.D | 16.500 |
cntr<5>.Q | cntr<22>.D | 16.500 |
cntr<5>.Q | cntr<23>.D | 16.500 |
cntr<5>.Q | cntr<6>.D | 16.500 |
cntr<5>.Q | cntr<7>.D | 16.500 |
cntr<5>.Q | cntr<8>.D | 16.500 |
cntr<5>.Q | cntr<9>.D | 16.500 |
cntr<6>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<6>.Q | cntr<10>.D | 16.500 |
cntr<6>.Q | cntr<11>.D | 16.500 |
cntr<6>.Q | cntr<12>.D | 16.500 |
cntr<6>.Q | cntr<13>.D | 16.500 |
cntr<6>.Q | cntr<14>.D | 16.500 |
cntr<6>.Q | cntr<15>.D | 16.500 |
cntr<6>.Q | cntr<16>.D | 16.500 |
cntr<6>.Q | cntr<17>.D | 16.500 |
cntr<6>.Q | cntr<18>.D | 16.500 |
cntr<6>.Q | cntr<19>.D | 16.500 |
cntr<6>.Q | cntr<20>.D | 16.500 |
cntr<6>.Q | cntr<21>.D | 16.500 |
cntr<6>.Q | cntr<22>.D | 16.500 |
cntr<6>.Q | cntr<23>.D | 16.500 |
cntr<6>.Q | cntr<7>.D | 16.500 |
cntr<6>.Q | cntr<8>.D | 16.500 |
cntr<6>.Q | cntr<9>.D | 16.500 |
cntr<7>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<7>.Q | cntr<10>.D | 16.500 |
cntr<7>.Q | cntr<11>.D | 16.500 |
cntr<7>.Q | cntr<12>.D | 16.500 |
cntr<7>.Q | cntr<13>.D | 16.500 |
cntr<7>.Q | cntr<14>.D | 16.500 |
cntr<7>.Q | cntr<15>.D | 16.500 |
cntr<7>.Q | cntr<16>.D | 16.500 |
cntr<7>.Q | cntr<17>.D | 16.500 |
cntr<7>.Q | cntr<18>.D | 16.500 |
cntr<7>.Q | cntr<19>.D | 16.500 |
cntr<7>.Q | cntr<20>.D | 16.500 |
cntr<7>.Q | cntr<21>.D | 16.500 |
cntr<7>.Q | cntr<22>.D | 16.500 |
cntr<7>.Q | cntr<23>.D | 16.500 |
cntr<7>.Q | cntr<8>.D | 16.500 |
cntr<7>.Q | cntr<9>.D | 16.500 |
cntr<8>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<8>.Q | cntr<10>.D | 16.500 |
cntr<8>.Q | cntr<11>.D | 16.500 |
cntr<8>.Q | cntr<12>.D | 16.500 |
cntr<8>.Q | cntr<13>.D | 16.500 |
cntr<8>.Q | cntr<14>.D | 16.500 |
cntr<8>.Q | cntr<15>.D | 16.500 |
cntr<8>.Q | cntr<16>.D | 16.500 |
cntr<8>.Q | cntr<17>.D | 16.500 |
cntr<8>.Q | cntr<18>.D | 16.500 |
cntr<8>.Q | cntr<19>.D | 16.500 |
cntr<8>.Q | cntr<20>.D | 16.500 |
cntr<8>.Q | cntr<21>.D | 16.500 |
cntr<8>.Q | cntr<22>.D | 16.500 |
cntr<8>.Q | cntr<23>.D | 16.500 |
cntr<8>.Q | cntr<9>.D | 16.500 |
cntr<9>.Q | FPGA_ctrl<1>.D | 16.500 |
cntr<9>.Q | cntr<10>.D | 16.500 |
cntr<9>.Q | cntr<11>.D | 16.500 |
cntr<9>.Q | cntr<12>.D | 16.500 |
cntr<9>.Q | cntr<13>.D | 16.500 |
cntr<9>.Q | cntr<14>.D | 16.500 |
cntr<9>.Q | cntr<15>.D | 16.500 |
cntr<9>.Q | cntr<16>.D | 16.500 |
cntr<9>.Q | cntr<17>.D | 16.500 |
cntr<9>.Q | cntr<18>.D | 16.500 |
cntr<9>.Q | cntr<19>.D | 16.500 |
cntr<9>.Q | cntr<20>.D | 16.500 |
cntr<9>.Q | cntr<21>.D | 16.500 |
cntr<9>.Q | cntr<22>.D | 16.500 |
cntr<9>.Q | cntr<23>.D | 16.500 |
en_CCLK.Q | MD.D | 16.500 |
en_CCLK.Q | en_CCLK.D | 16.500 |
was_done.Q | FPGA_ctrl<1>.D | 16.500 |
was_done.Q | cntr<10>.D | 16.500 |
was_done.Q | cntr<11>.D | 16.500 |
was_done.Q | cntr<12>.D | 16.500 |
was_done.Q | cntr<13>.D | 16.500 |
was_done.Q | cntr<14>.D | 16.500 |
was_done.Q | cntr<15>.D | 16.500 |
was_done.Q | cntr<16>.D | 16.500 |
was_done.Q | cntr<17>.D | 16.500 |
was_done.Q | cntr<18>.D | 16.500 |
was_done.Q | cntr<19>.D | 16.500 |
was_done.Q | cntr<1>.D | 16.500 |
was_done.Q | cntr<20>.D | 16.500 |
was_done.Q | cntr<21>.D | 16.500 |
was_done.Q | cntr<22>.D | 16.500 |
was_done.Q | cntr<23>.D | 16.500 |
was_done.Q | cntr<2>.D | 16.500 |
was_done.Q | cntr<3>.D | 16.500 |
was_done.Q | cntr<4>.D | 16.500 |
was_done.Q | cntr<5>.D | 16.500 |
was_done.Q | cntr<6>.D | 16.500 |
was_done.Q | cntr<7>.D | 16.500 |
was_done.Q | cntr<8>.D | 16.500 |
was_done.Q | cntr<9>.D | 16.500 |
FPGA_ctrl<1>.Q | cntr<0>.D | 15.500 |
FPGA_ctrl<1>.Q | cntr<1>.D | 15.500 |
FPGA_ctrl<1>.Q | cntr<24>.D | 15.500 |
FPGA_ctrl<1>.Q | cntr<25>.D | 15.500 |
FPGA_ctrl<4>.Q | MD.D | 15.500 |
FPGA_ctrl<4>.Q | clkdv<2>.D | 15.500 |
MD.Q | MD.D | 15.500 |
MS_n.Q | MCLK.D | 15.500 |
MS_n.Q | clkdv<2>.D | 15.500 |
clkdv<0>.Q | FPGA_ctrl<4>.D | 15.500 |
clkdv<0>.Q | cntr<0>.D | 15.500 |
clkdv<0>.Q | cntr<1>.D | 15.500 |
clkdv<0>.Q | cntr<24>.D | 15.500 |
clkdv<0>.Q | cntr<25>.D | 15.500 |
clkdv<0>.Q | was_done.D | 15.500 |
clkdv<2>.Q | CCLK.D | 15.500 |
clkdv<2>.Q | MCLK.D | 15.500 |
clkdv<2>.Q | cntr<0>.D | 15.500 |
clkdv<2>.Q | cntr<1>.D | 15.500 |
clkdv<2>.Q | cntr<24>.D | 15.500 |
clkdv<2>.Q | cntr<25>.D | 15.500 |
cntr<0>.Q | cntr<1>.D | 15.500 |
cntr<0>.Q | cntr<24>.D | 15.500 |
cntr<0>.Q | cntr<25>.D | 15.500 |
cntr<10>.Q | cntr<24>.D | 15.500 |
cntr<10>.Q | cntr<25>.D | 15.500 |
cntr<11>.Q | cntr<24>.D | 15.500 |
cntr<11>.Q | cntr<25>.D | 15.500 |
cntr<12>.Q | cntr<24>.D | 15.500 |
cntr<12>.Q | cntr<25>.D | 15.500 |
cntr<13>.Q | cntr<24>.D | 15.500 |
cntr<13>.Q | cntr<25>.D | 15.500 |
cntr<14>.Q | cntr<24>.D | 15.500 |
cntr<14>.Q | cntr<25>.D | 15.500 |
cntr<15>.Q | cntr<24>.D | 15.500 |
cntr<15>.Q | cntr<25>.D | 15.500 |
cntr<16>.Q | cntr<24>.D | 15.500 |
cntr<16>.Q | cntr<25>.D | 15.500 |
cntr<17>.Q | cntr<24>.D | 15.500 |
cntr<17>.Q | cntr<25>.D | 15.500 |
cntr<18>.Q | cntr<24>.D | 15.500 |
cntr<18>.Q | cntr<25>.D | 15.500 |
cntr<19>.Q | cntr<24>.D | 15.500 |
cntr<19>.Q | cntr<25>.D | 15.500 |
cntr<1>.Q | cntr<24>.D | 15.500 |
cntr<1>.Q | cntr<25>.D | 15.500 |
cntr<20>.Q | cntr<24>.D | 15.500 |
cntr<20>.Q | cntr<25>.D | 15.500 |
cntr<21>.Q | cntr<24>.D | 15.500 |
cntr<21>.Q | cntr<25>.D | 15.500 |
cntr<22>.Q | cntr<0>.D | 15.500 |
cntr<22>.Q | cntr<10>.D | 15.500 |
cntr<22>.Q | cntr<11>.D | 15.500 |
cntr<22>.Q | cntr<12>.D | 15.500 |
cntr<22>.Q | cntr<16>.D | 15.500 |
cntr<22>.Q | cntr<17>.D | 15.500 |
cntr<22>.Q | cntr<18>.D | 15.500 |
cntr<22>.Q | cntr<19>.D | 15.500 |
cntr<22>.Q | cntr<20>.D | 15.500 |
cntr<22>.Q | cntr<21>.D | 15.500 |
cntr<22>.Q | cntr<22>.D | 15.500 |
cntr<22>.Q | cntr<24>.D | 15.500 |
cntr<22>.Q | cntr<25>.D | 15.500 |
cntr<22>.Q | cntr<2>.D | 15.500 |
cntr<22>.Q | cntr<3>.D | 15.500 |
cntr<22>.Q | cntr<4>.D | 15.500 |
cntr<22>.Q | cntr<5>.D | 15.500 |
cntr<22>.Q | cntr<6>.D | 15.500 |
cntr<22>.Q | cntr<7>.D | 15.500 |
cntr<22>.Q | cntr<8>.D | 15.500 |
cntr<22>.Q | en_CCLK.D | 15.500 |
cntr<23>.Q | cntr<0>.D | 15.500 |
cntr<23>.Q | cntr<10>.D | 15.500 |
cntr<23>.Q | cntr<11>.D | 15.500 |
cntr<23>.Q | cntr<12>.D | 15.500 |
cntr<23>.Q | cntr<17>.D | 15.500 |
cntr<23>.Q | cntr<18>.D | 15.500 |
cntr<23>.Q | cntr<20>.D | 15.500 |
cntr<23>.Q | cntr<21>.D | 15.500 |
cntr<23>.Q | cntr<22>.D | 15.500 |
cntr<23>.Q | cntr<23>.D | 15.500 |
cntr<23>.Q | cntr<24>.D | 15.500 |
cntr<23>.Q | cntr<25>.D | 15.500 |
cntr<23>.Q | cntr<2>.D | 15.500 |
cntr<23>.Q | cntr<4>.D | 15.500 |
cntr<23>.Q | cntr<5>.D | 15.500 |
cntr<23>.Q | cntr<6>.D | 15.500 |
cntr<23>.Q | cntr<7>.D | 15.500 |
cntr<24>.Q | MCLK.D | 15.500 |
cntr<24>.Q | cntr<0>.D | 15.500 |
cntr<24>.Q | cntr<10>.D | 15.500 |
cntr<24>.Q | cntr<11>.D | 15.500 |
cntr<24>.Q | cntr<12>.D | 15.500 |
cntr<24>.Q | cntr<13>.D | 15.500 |
cntr<24>.Q | cntr<15>.D | 15.500 |
cntr<24>.Q | cntr<16>.D | 15.500 |
cntr<24>.Q | cntr<17>.D | 15.500 |
cntr<24>.Q | cntr<18>.D | 15.500 |
cntr<24>.Q | cntr<19>.D | 15.500 |
cntr<24>.Q | cntr<20>.D | 15.500 |
cntr<24>.Q | cntr<21>.D | 15.500 |
cntr<24>.Q | cntr<22>.D | 15.500 |
cntr<24>.Q | cntr<23>.D | 15.500 |
cntr<24>.Q | cntr<24>.D | 15.500 |
cntr<24>.Q | cntr<25>.D | 15.500 |
cntr<24>.Q | cntr<2>.D | 15.500 |
cntr<24>.Q | cntr<3>.D | 15.500 |
cntr<24>.Q | cntr<4>.D | 15.500 |
cntr<24>.Q | cntr<5>.D | 15.500 |
cntr<24>.Q | cntr<6>.D | 15.500 |
cntr<24>.Q | cntr<7>.D | 15.500 |
cntr<24>.Q | cntr<8>.D | 15.500 |
cntr<24>.Q | cntr<9>.D | 15.500 |
cntr<25>.Q | MCLK.D | 15.500 |
cntr<25>.Q | cntr<0>.D | 15.500 |
cntr<25>.Q | cntr<10>.D | 15.500 |
cntr<25>.Q | cntr<11>.D | 15.500 |
cntr<25>.Q | cntr<12>.D | 15.500 |
cntr<25>.Q | cntr<13>.D | 15.500 |
cntr<25>.Q | cntr<14>.D | 15.500 |
cntr<25>.Q | cntr<15>.D | 15.500 |
cntr<25>.Q | cntr<16>.D | 15.500 |
cntr<25>.Q | cntr<17>.D | 15.500 |
cntr<25>.Q | cntr<18>.D | 15.500 |
cntr<25>.Q | cntr<19>.D | 15.500 |
cntr<25>.Q | cntr<20>.D | 15.500 |
cntr<25>.Q | cntr<21>.D | 15.500 |
cntr<25>.Q | cntr<22>.D | 15.500 |
cntr<25>.Q | cntr<23>.D | 15.500 |
cntr<25>.Q | cntr<24>.D | 15.500 |
cntr<25>.Q | cntr<25>.D | 15.500 |
cntr<25>.Q | cntr<2>.D | 15.500 |
cntr<25>.Q | cntr<3>.D | 15.500 |
cntr<25>.Q | cntr<4>.D | 15.500 |
cntr<25>.Q | cntr<5>.D | 15.500 |
cntr<25>.Q | cntr<6>.D | 15.500 |
cntr<25>.Q | cntr<7>.D | 15.500 |
cntr<25>.Q | cntr<8>.D | 15.500 |
cntr<25>.Q | cntr<9>.D | 15.500 |
cntr<25>.Q | was_done.D | 15.500 |
cntr<2>.Q | cntr<24>.D | 15.500 |
cntr<2>.Q | cntr<25>.D | 15.500 |
cntr<3>.Q | cntr<24>.D | 15.500 |
cntr<3>.Q | cntr<25>.D | 15.500 |
cntr<4>.Q | cntr<24>.D | 15.500 |
cntr<4>.Q | cntr<25>.D | 15.500 |
cntr<5>.Q | cntr<24>.D | 15.500 |
cntr<5>.Q | cntr<25>.D | 15.500 |
cntr<6>.Q | cntr<24>.D | 15.500 |
cntr<6>.Q | cntr<25>.D | 15.500 |
cntr<7>.Q | cntr<24>.D | 15.500 |
cntr<7>.Q | cntr<25>.D | 15.500 |
cntr<8>.Q | cntr<24>.D | 15.500 |
cntr<8>.Q | cntr<25>.D | 15.500 |
cntr<9>.Q | cntr<24>.D | 15.500 |
cntr<9>.Q | cntr<25>.D | 15.500 |
en_CCLK.Q | CCLK.D | 15.500 |
en_CCLK.Q | clkdv<2>.D | 15.500 |
was_done.Q | cntr<0>.D | 15.500 |
was_done.Q | cntr<24>.D | 15.500 |
was_done.Q | cntr<25>.D | 15.500 |
was_done.Q | was_done.D | 15.500 |
FPGA_ctrl<4>.Q | MS_n.CE | 10.000 |
clkdv<0>.Q | CCLK.CE | 10.000 |
clkdv<0>.Q | MCLK.CE | 10.000 |
clkdv<0>.Q | MS_n.CE | 10.000 |
clkdv<0>.Q | clkdv<2>.CE | 10.000 |
Source Pad | Destination Pad | Delay |
---|---|---|
FPGA_ctrl<3> | MW_n | 20.000 |