v0b 2/23/19 amc13 version (amc13 T1 version 0xc001 with DCFEB version v0b) v0a 2/13/19 bit 8 and 9 added in status register for clock lock status of PLLs fabric_clk is generated from tx_wordclk when in standalone mode to ensure phase match v09 2/12/19 added bit 7 of control register to enable stand alone mode. v06 1/30/19 rx_buffer changed to writable v04 1/28/19 GBT mode change to GBTFRAME 0x40000007 is now send word count register added bit 6 to control register, if this bit is set to 1, send TX buffer continuously added bit 7 to control register, if this bit is set to 1, resets RX_RS_ERR_CNT and bit 7 of status register added send word count reg(0x40000007) to control number of TX buffer words to be sent. added RX RS ERROR count reg(0x4000000e). v03 1/25/19 split command register to command and control registers status register address moved to 0x40000002 v02 1/23/19 address table 0x10000 command register READ/WRITE bit 0 write 1 resets GBT, return to 0 by itself bit 1 write 1 resets RX_RS_ERR_CNT and bit 7 of status register, return to 0 by itself bit 7-2 not used bit 8 write 1 to start sending out data in TX buffer(512 of 116bit wide words). This bit returns to 0 by itself. bit 9 write 1 to enable RX buffer to be ready for receive data. When received data word(116 bit wide) matches the pattern register, received data will be written to the RX buffer starting from the pattern word, until 512 words are written(RX buffer full). This bit returns to 0 by itself. bit 31-10 not used 0x10001 control register READ/WRITE bit 0 not used bit 1 write 1 disables SFP TX bit 2 if 0, cdce controlled from ipbus.(default) bit 3 if 0, sel fabric_clk as cdce input clock(default) bit 4 if 0, power up cdce(default) bit 5 if 0, disable cdce sync mode(default) bit 6 if 0, send TX buffer once upon writing command bit 8. If 1, repeat without end bit 7 If 1, standalone mode, fabric_clk is generated from 125MHz clock. If 0, normal mode. bit 31-8 not used 0x10002 status register READ ONLY bit 0 if 1, rx_wordclk is locked. bit 1 if 1, rx_frameclk is locked. bit 2 if 1, GBT_TX is ready. bit 3 if 1, GBT_mgt is ready. bit 4 if 1, GBT_RX is ready. bit 5 if 1, SFP absent. bit 6 if 1, SFP RX signal lost. bit 7 if 1, RX RS error detected bit 8 if 1, 40MHz clock from 125Mhz is locked bit 9 if 1, fabric_clk in stand alone mode is locked bit 23-10 not used bit 31-24 firmware version, currently 0x04 0x10003 mask register bit 0 if 1, pattern_reg[7:0] are not compared. bit 1 if 1, pattern_reg[15:8] are not compared. ...... bit 9 if 1, pattern_reg[79:72] are not compared. bit 10 if 1, pattern_reg[83:80] are not compared. bit 31-11 all 0 0x10004 pattern register bit(31:0) READ/WRITE 0x10005 pattern register bit(63:32) READ/WRITE 0x10006 bit 19-0 pattern register bit(83:64) READ/WRITE 0x10007 send word count reg R/W bit 31-8 not used bit 8-0 number of TX buffer words to be sent - 1 0x10008 tx_wordclk rate monitor READ ONLY bit 31-16 not used bit 15-0 should be around 0x4289 0x10009 tx_frameclk rate monitor READ ONLY bit 31-16 not used bit 15-0 should be around 0xc79c 0x1000a rx_wordclk rate monitor READ ONLY bit 31-16 not used bit 15-0 should be around 0x4289 0x1000b rx_frameclk rate monitor READ ONLY bit 31-16 not used bit 15-0 should be around 0xc79c 0x1000c fabric_clk rate monitor READ ONLY bit 31-16 not used bit 15-0 should be around 0xc79c 0x1000d mgt_refclk rate monitor READ ONLY bit 31-16 not used bit 15-0 should be around 0x4289 0x1000e RX RS error counter READ ONLY 0x11000-0x117ff RX buffer data READ/WRITE Every four 32bit word maps to one received word 0x40001000 bit(31:0) of the pattern word 0x40001001 bit(63:32) of the pattern word 0x40001002 bit 19-0 bit(83:64) of the pattern word 0x40001003 allways all 0 ...... 0x11800-0x11fff TX buffer data READ/WRITE Every four 32bit word maps to one word to be sent 0x40001800 bit(31:0) of the pattern word 0x40001801 bit(63:32) of the pattern word 0x40001802 bit 19-0 bit(83:64) of the pattern word 0x40001803 irrelavant ...... The simplest test of the module is a loopback test. SFP module is always in the top position. Loop back with a fiber from TX to RX. w 0x10000 1 --reset GBT w 0x10004 0xabcd -- pattern bit 31-0 w 0x10005 0x12345 -- pattern bit 63-32 w 0x10006 0x67890 -- pattern bit 83-64 w 0x11800 0xabcd -- same as pattern bit 31-0 w 0x11801 0x12345 -- same as pattern bit 63-32 w 0x11802 0x67890 -- same as pattern bit 83-64 w 0x11804 .... -- fill TX buffer with data w 0x10001 0x200 -- arm RX buffer w 0x10000 0x100 -- start sending TX data r 0x11000 -- read out RX buffer r 0x11001 ...... data from RX buffer should be the same as that read back from TX buffer.