------------------------------------------------------------------------------ -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 1.12 -- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard -- / / Filename : htr.vhd -- /___/ /\ -- \ \ / \ -- \___\/\___\ -- -- -- Instantiation Template -- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard --**************************Component Declarations***************************** component HTR generic ( -- Simulation attributes WRAPPER_SIM_GTXRESET_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset ); port ( --_________________________________________________________________________ --_________________________________________________________________________ --GTX0 (X0_Y0) ------------------------ Loopback and Powerdown Ports ---------------------- GTX0_LOOPBACK_IN : in std_logic_vector(2 downto 0); ----------------------- Receive Ports - 8b10b Decoder ---------------------- GTX0_RXCHARISCOMMA_OUT : out std_logic_vector(1 downto 0); GTX0_RXCHARISK_OUT : out std_logic_vector(1 downto 0); GTX0_RXDISPERR_OUT : out std_logic_vector(1 downto 0); GTX0_RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0); ------------------- Receive Ports - Clock Correction Ports ----------------- GTX0_RXCLKCORCNT_OUT : out std_logic_vector(2 downto 0); --------------- Receive Ports - Comma Detection and Alignment -------------- GTX0_RXENMCOMMAALIGN_IN : in std_logic; GTX0_RXENPCOMMAALIGN_IN : in std_logic; ------------------- Receive Ports - RX Data Path interface ----------------- GTX0_RXDATA_OUT : out std_logic_vector(15 downto 0); GTX0_RXUSRCLK2_IN : in std_logic; ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ GTX0_RXCDRRESET_IN : in std_logic; GTX0_RXEQMIX_IN : in std_logic_vector(2 downto 0); GTX0_RXN_IN : in std_logic; GTX0_RXP_IN : in std_logic; --------------- Receive Ports - RX Loss-of-sync State Machine -------------- GTX0_RXLOSSOFSYNC_OUT : out std_logic_vector(1 downto 0); ------------------------ Receive Ports - RX PLL Ports ---------------------- GTX0_GTXRXRESET_IN : in std_logic; GTX0_MGTREFCLKRX_IN : in std_logic; GTX0_PLLRXRESET_IN : in std_logic; GTX0_RXPLLLKDET_OUT : out std_logic; GTX0_RXRESETDONE_OUT : out std_logic; ----------------- Receive Ports - RX Polarity Control Ports ---------------- GTX0_RXPOLARITY_IN : in std_logic; ---------------- Transmit Ports - 8b10b Encoder Control Ports -------------- GTX0_TXCHARISK_IN : in std_logic_vector(1 downto 0); ------------------ Transmit Ports - TX Data Path interface ----------------- GTX0_TXDATA_IN : in std_logic_vector(15 downto 0); GTX0_TXOUTCLK_OUT : out std_logic; GTX0_TXUSRCLK2_IN : in std_logic; ---------------- Transmit Ports - TX Driver and OOB signaling -------------- GTX0_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0); GTX0_TXN_OUT : out std_logic; GTX0_TXP_OUT : out std_logic; GTX0_TXPOSTEMPHASIS_IN : in std_logic_vector(4 downto 0); --------------- Transmit Ports - TX Driver and OOB signalling -------------- GTX0_TXPREEMPHASIS_IN : in std_logic_vector(3 downto 0); ----------------------- Transmit Ports - TX PLL Ports ---------------------- GTX0_GTXTXRESET_IN : in std_logic; GTX0_TXRESETDONE_OUT : out std_logic; -------------------- Transmit Ports - TX Polarity Control ------------------ GTX0_TXPOLARITY_IN : in std_logic ); end component; ----------------------------- The GTX Wrapper ----------------------------- HTR_i : HTR generic map ( WRAPPER_SIM_GTXRESET_SPEEDUP => 1 ) port map ( --_____________________________________________________________________ --_____________________________________________________________________ --GTX0 (X0Y0) ------------------------ Loopback and Powerdown Ports ---------------------- GTX0_LOOPBACK_IN => , ----------------------- Receive Ports - 8b10b Decoder ---------------------- GTX0_RXCHARISCOMMA_OUT => , GTX0_RXCHARISK_OUT => , GTX0_RXDISPERR_OUT => , GTX0_RXNOTINTABLE_OUT => , ------------------- Receive Ports - Clock Correction Ports ----------------- GTX0_RXCLKCORCNT_OUT => , --------------- Receive Ports - Comma Detection and Alignment -------------- GTX0_RXENMCOMMAALIGN_IN => , GTX0_RXENPCOMMAALIGN_IN => , ------------------- Receive Ports - RX Data Path interface ----------------- GTX0_RXDATA_OUT => , GTX0_RXUSRCLK2_IN => , ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ GTX0_RXCDRRESET_IN => , GTX0_RXEQMIX_IN => , GTX0_RXN_IN => , GTX0_RXP_IN => , --------------- Receive Ports - RX Loss-of-sync State Machine -------------- GTX0_RXLOSSOFSYNC_OUT => , ------------------------ Receive Ports - RX PLL Ports ---------------------- GTX0_GTXRXRESET_IN => , GTX0_MGTREFCLKRX_IN => , GTX0_PLLRXRESET_IN => , GTX0_RXPLLLKDET_OUT => , GTX0_RXRESETDONE_OUT => , ----------------- Receive Ports - RX Polarity Control Ports ---------------- GTX0_RXPOLARITY_IN => , ---------------- Transmit Ports - 8b10b Encoder Control Ports -------------- GTX0_TXCHARISK_IN => , ------------------ Transmit Ports - TX Data Path interface ----------------- GTX0_TXDATA_IN => , GTX0_TXOUTCLK_OUT => , GTX0_TXUSRCLK2_IN => , ---------------- Transmit Ports - TX Driver and OOB signaling -------------- GTX0_TXDIFFCTRL_IN => , GTX0_TXN_OUT => , GTX0_TXP_OUT => , GTX0_TXPOSTEMPHASIS_IN => , --------------- Transmit Ports - TX Driver and OOB signalling -------------- GTX0_TXPREEMPHASIS_IN => , ----------------------- Transmit Ports - TX PLL Ports ---------------------- GTX0_GTXTXRESET_IN => , GTX0_TXRESETDONE_OUT => , -------------------- Transmit Ports - TX Polarity Control ------------------ GTX0_TXPOLARITY_IN => ); -----------------------Dedicated GTX Reference Clock Inputs --------------- -- Each dedicated refclk you are using in your design will need its own IBUFDS_GTXE1 instance q0_clk1_refclk_ibufds_i : IBUFDS_GTXE1 port map ( O => , ODIV2 => , CEB => , I => , -- Connect to package pin AH6 IB => -- Connect to package pin AH5 );