AMC13_T2 Project Status (02/01/2015 - 11:19:07)
Project File: T2New.xise Parser Errors: No Errors
Module Name: AMC13_T2 Implementation State: Programming File Generated
Target Device: xc6slx45t-2fgg484
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
1254 Warnings (3 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 5,786 54,576 10%  
    Number used as Flip Flops 5,782      
    Number used as Latches 4      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 5,047 27,288 18%  
    Number used as logic 4,777 27,288 17%  
        Number using O6 output only 2,950      
        Number using O5 output only 515      
        Number using O5 and O6 1,312      
        Number used as ROM 0      
    Number used as Memory 46 6,408 1%  
        Number used as Dual Port RAM 18      
            Number using O6 output only 2      
            Number using O5 output only 0      
            Number using O5 and O6 16      
        Number used as Single Port RAM 0      
        Number used as Shift Register 28      
            Number using O6 output only 16      
            Number using O5 output only 0      
            Number using O5 and O6 12      
    Number used exclusively as route-thrus 224      
        Number with same-slice register load 185      
        Number with same-slice carry load 39      
        Number with other load 0      
Number of occupied Slices 2,017 6,822 29%  
Number of MUXCYs used 972 13,644 7%  
Number of LUT Flip Flop pairs used 6,300      
    Number with an unused Flip Flop 1,442 6,300 22%  
    Number with an unused LUT 1,253 6,300 19%  
    Number of fully used LUT-FF pairs 3,605 6,300 57%  
    Number of unique control sets 190      
    Number of slice register sites lost
        to control set restrictions
508 54,576 1%  
Number of bonded IOBs 84 296 28%  
    Number of LOCed IOBs 66 84 78%  
    IOB Flip Flops 31      
    IOB Master Pads 13      
    IOB Slave Pads 13      
    Number of bonded IPADs 6 16 37%  
        Number of LOCed IPADs 6 6 100%  
    Number of bonded OPADs 4 8 50%  
        Number of LOCed OPADs 4 4 100%  
Number of RAMB16BWERs 39 116 33%  
Number of RAMB8BWERs 1 232 1%  
Number of BUFIO2/BUFIO2_2CLKs 6 32 18%  
    Number used as BUFIO2s 6      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 5 32 15%  
    Number used as BUFIO2FBs 5      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 11 16 68%  
    Number used as BUFGs 11      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 6 8 75%  
    Number used as DCMs 6      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 4 376 1%  
    Number used as ILOGIC2s 4      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 376 0%  
Number of OLOGIC2/OSERDES2s 15 376 3%  
    Number used as OLOGIC2s 15      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 256 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 58 0%  
Number of GTPA1_DUALs 1 2 50%  
Number of ICAPs 1 1 100%  
Number of MCBs 0 2 0%  
Number of PCIE_A1s 0 1 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 4 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Number of RPM macros 1      
Average Fanout of Non-Clock Nets 3.25      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSun Feb 1 11:14:28 20150995 Warnings (1 new)48 Infos (14 new)
Translation ReportCurrentSun Feb 1 11:14:39 20150235 Warnings (0 new)5 Infos (0 new)
Map ReportCurrentSun Feb 1 11:17:10 201509 Warnings (1 new)275 Infos (0 new)
Place and Route ReportCurrentSun Feb 1 11:18:14 201507 Warnings (0 new)1 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentSun Feb 1 11:18:29 201501 Warning (0 new)3 Infos (0 new)
Bitgen ReportCurrentSun Feb 1 11:18:56 201507 Warnings (1 new)2 Infos (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateFri Dec 12 11:02:41 2014
Physical Synthesis ReportCurrentSun Feb 1 11:17:10 2015
WebTalk ReportCurrentSun Feb 1 11:18:58 2015
WebTalk Log FileCurrentSun Feb 1 11:19:07 2015

Date Generated: 02/01/2015 - 11:19:07