REM ############################################################################
REM   ____  ____ 
REM  /   /\/   / 
REM /___/  \  /    Vendor: Xilinx 
REM \   \   \/     Version : 1.12
REM  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
REM  /   /         Filename : simulate_ncsim.bat
REM /___/   /\      
REM \   \  /  \ 
REM  \___\/\___\ 
REM
REM
REM Script SIMULATE_NCSIM.BAT
REM Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
REM
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REM 
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REM **************************** Beginning of Script ***************************

        
REM Ensure the follwoing
REM The library paths for UNISIMS_VER, SIMPRIMS_VER, XILINXCORELIB_VER,
REM UNISIM, SIMPRIM, XILINXCORELIB are set correctly in the cds.lib and hdl.var files.
REM Variables LMC_HOME and XILINX are set 
REM Define the mapping for the work library in cds.lib file. DEFINE work ./work

mkdir work
REM MGT Wrapper
ncvhdl -RELAX -V93 -work work   ..\..\..\htr_gtx.vhd
ncvhdl -RELAX -V93 -work work   ..\..\..\htr.vhd



REM Example Design modules
ncvhdl -RELAX -V93 -work work  ..\..\example_design\frame_gen.vhd
ncvhdl -RELAX -V93 -work work  ..\..\example_design\frame_check.vhd
ncvhdl -RELAX -V93 -work work  ..\..\example_design\htr_top.vhd

ncvhdl -RELAX -V93 -work work  ..\demo_tb.vhd

REM Other modules
ncvhdl -RELAX -V93 -work work ..\sim_reset_mgt_model.vhd

REM Elaborate Design
ncelab -relax -TIMESCALE 1ns/1ps -ACCESS +rwc work.DEMO_TB

ncsim +access+rw work.DEMO_TB -input @"simvision -input wave_ncsim.sv"