################################################################################ ## ____ ____ ## / /\/ / ## /___/ \ / Vendor: Xilinx ## \ \ \/ Version : 1.12 ## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard ## / / Filename : gtx_attributes.ucf ## /___/ /\ ## \ \ / \ ## \___\/\___\ ## ## ## GTX ATTRIBUTES ## This file contains the attributes for the active GTX transceivers in the ## design. If you would like to use this file in your design, please make ## sure that the path to the GTX instance is correct. ## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard ## ## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. ## ## This file contains confidential and proprietary information ## of Xilinx, Inc. and is protected under U.S. and ## international copyright and other intellectual property ## laws. ## ## DISCLAIMER ## This disclaimer is not a license and does not grant any ## rights to the materials distributed herewith. Except as ## otherwise provided in a valid license issued to you by ## Xilinx, and to the maximum extent permitted by applicable ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and ## (2) Xilinx shall not be liable (whether in contract or tort, ## including negligence, or under any other theory of ## liability) for any loss or damage of any kind or nature ## related to, arising under or in connection with these ## materials, including for any direct, or any indirect, ## special, incidental, or consequential loss or damage ## (including loss of data, profits, goodwill, or any type of ## loss or damage suffered as a result of any action brought ## by a third party) even if such damage or loss was ## reasonably foreseeable or Xilinx had been advised of the ## possibility of the same. ## ## CRITICAL APPLICATIONS ## Xilinx products are not designed or intended to be fail- ## safe, or for use in any application requiring fail-safe ## performance, such as life-support or safety devices or ## systems, Class III medical devices, nuclear facilities, ## applications related to the deployment of airbags, or any ## other applications that could lead to death, personal ## injury, or severe property or environmental damage ## (individually and collectively, "Critical ## Applications"). Customer assumes the sole risk and ## liability of any use of Xilinx products in Critical ## Applications, subject only to applicable laws and ## regulations governing limitations on product liability. ## ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS ## PART OF THIS FILE AT ALL TIMES. ############################## Active GTX Attributes ####################### ##________________________ Attributes for GTX 0_____________________ ##--------------------------TX PLL---------------------------- INST HTR_i/gtx0_HTR_i/gtxe1_i TX_CLK_SOURCE = "RXPLL"; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_OVERSAMPLE_MODE = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i TXPLL_COM_CFG = 24'h21680a; INST HTR_i/gtx0_HTR_i/gtxe1_i TXPLL_CP_CFG = 8'h0D; INST HTR_i/gtx0_HTR_i/gtxe1_i TXPLL_DIVSEL_FB = 2; INST HTR_i/gtx0_HTR_i/gtxe1_i TXPLL_DIVSEL_OUT = 1; INST HTR_i/gtx0_HTR_i/gtxe1_i TXPLL_DIVSEL_REF = 2; INST HTR_i/gtx0_HTR_i/gtxe1_i TXPLL_DIVSEL45_FB = 5; INST HTR_i/gtx0_HTR_i/gtxe1_i TXPLL_LKDET_CFG = 3'b111; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_CLK25_DIVIDER = 10; INST HTR_i/gtx0_HTR_i/gtxe1_i TXPLL_SATA = 2'b00; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_TDCC_CFG = 2'b11; INST HTR_i/gtx0_HTR_i/gtxe1_i PMA_CAS_CLK_EN = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i POWER_SAVE = 10'b0000110100; ##-----------------------TX Interface------------------------- INST HTR_i/gtx0_HTR_i/gtxe1_i GEN_TXUSRCLK = "TRUE"; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_DATA_WIDTH = 20; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_USRCLK_CFG = 6'h00; INST HTR_i/gtx0_HTR_i/gtxe1_i TXOUTCLK_CTRL = "TXOUTCLKPMA_DIV2"; INST HTR_i/gtx0_HTR_i/gtxe1_i TXOUTCLK_DLY = 10'b0000000000; ##------------TX Buffering and Phase Alignment---------------- INST HTR_i/gtx0_HTR_i/gtxe1_i TX_PMADATA_OPT = 1'b0; INST HTR_i/gtx0_HTR_i/gtxe1_i PMA_TX_CFG = 20'h80082; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_BUFFER_USE = "TRUE"; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_BYTECLK_CFG = 6'h00; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_EN_RATE_RESET_BUF = "TRUE"; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_XCLK_SEL = "TXOUT"; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_DLYALIGN_CTRINC = 4'b0100; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_DLYALIGN_LPFINC = 4'b0110; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_DLYALIGN_MONSEL = 3'b000; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_DLYALIGN_OVRDSETTING = 8'b10000000; ##-----------------------TX Gearbox--------------------------- INST HTR_i/gtx0_HTR_i/gtxe1_i GEARBOX_ENDEC = 3'b000; INST HTR_i/gtx0_HTR_i/gtxe1_i TXGEARBOX_USE = "FALSE"; ##--------------TX Driver and OOB Signalling------------------ INST HTR_i/gtx0_HTR_i/gtxe1_i TX_DRIVE_MODE = "DIRECT"; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_IDLE_ASSERT_DELAY = 3'b100; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_IDLE_DEASSERT_DELAY = 3'b010; INST HTR_i/gtx0_HTR_i/gtxe1_i TXDRIVE_LOOPBACK_HIZ = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i TXDRIVE_LOOPBACK_PD = "FALSE"; ##------------TX Pipe Control for PCI Express/SATA------------ INST HTR_i/gtx0_HTR_i/gtxe1_i COM_BURST_VAL = 4'b1111; ##----------------TX Attributes for PCI Express--------------- INST HTR_i/gtx0_HTR_i/gtxe1_i TX_DEEMPH_0 = 5'b11010; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_DEEMPH_1 = 5'b10000; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_MARGIN_FULL_0 = 7'b1001110; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_MARGIN_FULL_1 = 7'b1001001; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_MARGIN_FULL_2 = 7'b1000101; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_MARGIN_FULL_3 = 7'b1000010; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_MARGIN_FULL_4 = 7'b1000000; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_MARGIN_LOW_0 = 7'b1000110; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_MARGIN_LOW_1 = 7'b1000100; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_MARGIN_LOW_2 = 7'b1000010; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_MARGIN_LOW_3 = 7'b1000000; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_MARGIN_LOW_4 = 7'b1000000; ##--------------------------RX PLL---------------------------- INST HTR_i/gtx0_HTR_i/gtxe1_i RX_OVERSAMPLE_MODE = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i RXPLL_COM_CFG = 24'h21680a; INST HTR_i/gtx0_HTR_i/gtxe1_i RXPLL_CP_CFG = 8'h0D; INST HTR_i/gtx0_HTR_i/gtxe1_i RXPLL_DIVSEL_FB = 2; INST HTR_i/gtx0_HTR_i/gtxe1_i RXPLL_DIVSEL_OUT = 1; INST HTR_i/gtx0_HTR_i/gtxe1_i RXPLL_DIVSEL_REF = 2; INST HTR_i/gtx0_HTR_i/gtxe1_i RXPLL_DIVSEL45_FB = 5; INST HTR_i/gtx0_HTR_i/gtxe1_i RXPLL_LKDET_CFG = 3'b111; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_CLK25_DIVIDER = 10; ##-----------------------RX Interface------------------------- INST HTR_i/gtx0_HTR_i/gtxe1_i GEN_RXUSRCLK = "TRUE"; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_DATA_WIDTH = 20; INST HTR_i/gtx0_HTR_i/gtxe1_i RXRECCLK_CTRL = "RXRECCLKPMA_DIV2"; INST HTR_i/gtx0_HTR_i/gtxe1_i RXRECCLK_DLY = 10'b0000000000; INST HTR_i/gtx0_HTR_i/gtxe1_i RXUSRCLK_DLY = 16'h0000; ##--------RX Driver,OOB signalling,Coupling and Eq.,CDR------- INST HTR_i/gtx0_HTR_i/gtxe1_i AC_CAP_DIS = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i CDR_PH_ADJ_TIME = 5'b10100; INST HTR_i/gtx0_HTR_i/gtxe1_i OOBDETECT_THRESHOLD = 3'b011; INST HTR_i/gtx0_HTR_i/gtxe1_i PMA_CDR_SCAN = 27'h640404C; INST HTR_i/gtx0_HTR_i/gtxe1_i PMA_RX_CFG = 25'h05ce008; INST HTR_i/gtx0_HTR_i/gtxe1_i RCV_TERM_GND = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i RCV_TERM_VTTRX = "TRUE"; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_EN_IDLE_HOLD_CDR = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_EN_IDLE_RESET_FR = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_EN_IDLE_RESET_PH = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i TX_DETECT_RX_CFG = 14'h1832; INST HTR_i/gtx0_HTR_i/gtxe1_i TERMINATION_CTRL = 5'b00000; INST HTR_i/gtx0_HTR_i/gtxe1_i TERMINATION_OVRD = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i CM_TRIM = 2'b01; INST HTR_i/gtx0_HTR_i/gtxe1_i PMA_RXSYNC_CFG = 7'h00; INST HTR_i/gtx0_HTR_i/gtxe1_i PMA_CFG = 76'h0040000040000000003; INST HTR_i/gtx0_HTR_i/gtxe1_i BGTEST_CFG = 2'b00; INST HTR_i/gtx0_HTR_i/gtxe1_i BIAS_CFG = 17'h00000; ##------------RX Decision Feedback Equalizer(DFE)------------- INST HTR_i/gtx0_HTR_i/gtxe1_i DFE_CAL_TIME = 5'b01100; INST HTR_i/gtx0_HTR_i/gtxe1_i DFE_CFG = 8'b00011011; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_EN_IDLE_HOLD_DFE = "TRUE"; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_EYE_OFFSET = 8'h4C; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_EYE_SCANMODE = 2'b00; ##-----------------------PRBS Detection----------------------- INST HTR_i/gtx0_HTR_i/gtxe1_i RXPRBSERR_LOOPBACK = 1'b0; ##----------------Comma Detection and Alignment--------------- INST HTR_i/gtx0_HTR_i/gtxe1_i ALIGN_COMMA_WORD = 2; INST HTR_i/gtx0_HTR_i/gtxe1_i COMMA_10B_ENABLE = 10'b1111111111; INST HTR_i/gtx0_HTR_i/gtxe1_i COMMA_DOUBLE = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i DEC_MCOMMA_DETECT = "TRUE"; INST HTR_i/gtx0_HTR_i/gtxe1_i DEC_PCOMMA_DETECT = "TRUE"; INST HTR_i/gtx0_HTR_i/gtxe1_i DEC_VALID_COMMA_ONLY = "TRUE"; INST HTR_i/gtx0_HTR_i/gtxe1_i MCOMMA_10B_VALUE = 10'b1010000011; INST HTR_i/gtx0_HTR_i/gtxe1_i MCOMMA_DETECT = "TRUE"; INST HTR_i/gtx0_HTR_i/gtxe1_i PCOMMA_10B_VALUE = 10'b0101111100; INST HTR_i/gtx0_HTR_i/gtxe1_i PCOMMA_DETECT = "TRUE"; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_DECODE_SEQ_MATCH = "TRUE"; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_SLIDE_AUTO_WAIT = 5; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_SLIDE_MODE = "OFF"; INST HTR_i/gtx0_HTR_i/gtxe1_i SHOW_REALIGN_COMMA = "TRUE"; ##---------------RX Loss-of-sync State Machine---------------- INST HTR_i/gtx0_HTR_i/gtxe1_i RX_LOS_INVALID_INCR = 8; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_LOS_THRESHOLD = 128; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_LOSS_OF_SYNC_FSM = "TRUE"; ##-----------------------RX Gearbox--------------------------- INST HTR_i/gtx0_HTR_i/gtxe1_i RXGEARBOX_USE = "FALSE"; ##-----------RX Elastic Buffer and Phase alignment------------ INST HTR_i/gtx0_HTR_i/gtxe1_i RX_BUFFER_USE = "TRUE"; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_EN_IDLE_RESET_BUF = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_EN_MODE_RESET_BUF = "TRUE"; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_EN_RATE_RESET_BUF = "TRUE"; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_EN_REALIGN_RESET_BUF = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_EN_REALIGN_RESET_BUF2 = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_FIFO_ADDR_MODE = "FULL"; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_IDLE_HI_CNT = 4'b1000; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_IDLE_LO_CNT = 4'b0000; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_XCLK_SEL = "RXREC"; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_DLYALIGN_CTRINC = 4'b1110; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_DLYALIGN_EDGESET = 5'b00010; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_DLYALIGN_LPFINC = 4'b1110; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_DLYALIGN_MONSEL = 3'b000; INST HTR_i/gtx0_HTR_i/gtxe1_i RX_DLYALIGN_OVRDSETTING = 8'b10000000; ##----------------------Clock Correction---------------------- INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_ADJ_LEN = 2; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_DET_LEN = 2; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_INSERT_IDLE_FLAG = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_KEEP_IDLE = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_MAX_LAT = 18; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_MIN_LAT = 14; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_PRECEDENCE = "TRUE"; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_REPEAT_WAIT = 0; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_SEQ_1_1 = 10'b0111111011; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_SEQ_1_2 = 10'b0111011100; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_SEQ_1_3 = 10'b0100000000; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_SEQ_1_4 = 10'b0100000000; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_SEQ_1_ENABLE = 4'b1111; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_SEQ_2_1 = 10'b0100000000; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_SEQ_2_2 = 10'b0100000000; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_SEQ_2_3 = 10'b0100000000; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_SEQ_2_4 = 10'b0100000000; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_SEQ_2_ENABLE = 4'b1111; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_COR_SEQ_2_USE = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i CLK_CORRECT_USE = "TRUE"; ##----------------------Channel Bonding---------------------- INST HTR_i/gtx0_HTR_i/gtxe1_i CHAN_BOND_1_MAX_SKEW = 1; INST HTR_i/gtx0_HTR_i/gtxe1_i CHAN_BOND_2_MAX_SKEW = 1; INST HTR_i/gtx0_HTR_i/gtxe1_i CHAN_BOND_KEEP_ALIGN = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i CHAN_BOND_SEQ_1_1 = 10'b0000000000; INST HTR_i/gtx0_HTR_i/gtxe1_i CHAN_BOND_SEQ_1_2 = 10'b0000000000; INST HTR_i/gtx0_HTR_i/gtxe1_i CHAN_BOND_SEQ_1_3 = 10'b0000000000; INST HTR_i/gtx0_HTR_i/gtxe1_i CHAN_BOND_SEQ_1_4 = 10'b0000000000; INST HTR_i/gtx0_HTR_i/gtxe1_i CHAN_BOND_SEQ_1_ENABLE = 4'b1111; INST HTR_i/gtx0_HTR_i/gtxe1_i CHAN_BOND_SEQ_2_1 = 10'b0000000000; INST HTR_i/gtx0_HTR_i/gtxe1_i CHAN_BOND_SEQ_2_2 = 10'b0000000000; INST HTR_i/gtx0_HTR_i/gtxe1_i CHAN_BOND_SEQ_2_3 = 10'b0000000000; INST HTR_i/gtx0_HTR_i/gtxe1_i CHAN_BOND_SEQ_2_4 = 10'b0000000000; INST HTR_i/gtx0_HTR_i/gtxe1_i CHAN_BOND_SEQ_2_CFG = 5'b00000; INST HTR_i/gtx0_HTR_i/gtxe1_i CHAN_BOND_SEQ_2_ENABLE = 4'b1111; INST HTR_i/gtx0_HTR_i/gtxe1_i CHAN_BOND_SEQ_2_USE = "FALSE"; INST HTR_i/gtx0_HTR_i/gtxe1_i CHAN_BOND_SEQ_LEN = 1; INST HTR_i/gtx0_HTR_i/gtxe1_i PCI_EXPRESS_MODE = "FALSE"; ##-----------RX Attributes for PCI Express/SATA/SAS---------- INST HTR_i/gtx0_HTR_i/gtxe1_i SAS_MAX_COMSAS = 52; INST HTR_i/gtx0_HTR_i/gtxe1_i SAS_MIN_COMSAS = 40; INST HTR_i/gtx0_HTR_i/gtxe1_i SATA_BURST_VAL = 3'b100; INST HTR_i/gtx0_HTR_i/gtxe1_i SATA_IDLE_VAL = 3'b100; INST HTR_i/gtx0_HTR_i/gtxe1_i SATA_MAX_BURST = 7; INST HTR_i/gtx0_HTR_i/gtxe1_i SATA_MAX_INIT = 22; INST HTR_i/gtx0_HTR_i/gtxe1_i SATA_MAX_WAKE = 7; INST HTR_i/gtx0_HTR_i/gtxe1_i SATA_MIN_BURST = 4; INST HTR_i/gtx0_HTR_i/gtxe1_i SATA_MIN_INIT = 12; INST HTR_i/gtx0_HTR_i/gtxe1_i SATA_MIN_WAKE = 4; INST HTR_i/gtx0_HTR_i/gtxe1_i TRANS_TIME_FROM_P2 = 12'h03c; INST HTR_i/gtx0_HTR_i/gtxe1_i TRANS_TIME_NON_P2 = 8'h19; INST HTR_i/gtx0_HTR_i/gtxe1_i TRANS_TIME_RATE = 8'hff; INST HTR_i/gtx0_HTR_i/gtxe1_i TRANS_TIME_TO_P2 = 10'h064;