################################################################################
##   ____  ____
##  /   /\/   /
## /___/  \  /    Vendor: Xilinx
## \   \   \/     Version : 1.12
##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
##  /   /         Filename : HTR_top.ucf
## /___/   /\     
## \   \  /  \ 
##  \___\/\___\
##
##
## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN
## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
##
## Device:  xc6vlx130t
## Package: ff1156
##
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################################## Clock Constraints ##########################

NET "q0_clk1_refclk_i" TNM_NET = "q0_clk1_refclk_i";
TIMESPEC "TS_q0_clk1_refclk_i" = PERIOD "q0_clk1_refclk_i" 4.0;



# User Clock Constraints
NET "gtx0_txusrclk2_i" TNM_NET = "gtx0_txusrclk2_i";
TIMESPEC "TS_gtx0_txusrclk2_i" = PERIOD "gtx0_txusrclk2_i" 8.0;



#################### locs for top level ports (ML623 Board) ###################



####################### GTX reference clock constraints #######################
NET Q0_CLK1_MGTREFCLK_PAD_N_IN  LOC=AH5;
NET Q0_CLK1_MGTREFCLK_PAD_P_IN  LOC=AH6;

################## Track Data LED constraint (ML623 Board) ####################

##NET TRACK_DATA_OUT LOC=M15;

################################# mgt wrapper constraints #####################

##---------- Set placement for gtx0_gtx_wrapper_i/GTX_DUAL ------
INST HTR_i/gtx0_HTR_i/gtxe1_i LOC=GTXE1_X0Y0;