##############################################################
#
# Xilinx Core Generator version 13.4
# Date: Fri May 04 17:28:16 2012
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
#  Generated from component: xilinx.com:ip:v6_gtxwizard:1.12
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6vlx130t
SET devicefamily = virtex6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff1156
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -1
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Virtex-6_FPGA_GTX_Transceiver_Wizard xilinx.com:ip:v6_gtxwizard:1.12
# END Select
# BEGIN Parameters
CSET advanced_clocking=false
CSET bytes_to_reduce_error=8
CSET cb_seq_1_1=00000000
CSET cb_seq_1_1_disp=false
CSET cb_seq_1_1_k=false
CSET cb_seq_1_1_mask=true
CSET cb_seq_1_2=00000000
CSET cb_seq_1_2_disp=false
CSET cb_seq_1_2_k=false
CSET cb_seq_1_2_mask=true
CSET cb_seq_1_3=00000000
CSET cb_seq_1_3_disp=false
CSET cb_seq_1_3_k=false
CSET cb_seq_1_3_mask=true
CSET cb_seq_1_4=00000000
CSET cb_seq_1_4_disp=false
CSET cb_seq_1_4_k=false
CSET cb_seq_1_4_mask=true
CSET cb_seq_2_1=00000000
CSET cb_seq_2_1_disp=false
CSET cb_seq_2_1_k=false
CSET cb_seq_2_1_mask=true
CSET cb_seq_2_2=00000000
CSET cb_seq_2_2_disp=false
CSET cb_seq_2_2_k=false
CSET cb_seq_2_2_mask=true
CSET cb_seq_2_3=00000000
CSET cb_seq_2_3_disp=false
CSET cb_seq_2_3_k=false
CSET cb_seq_2_3_mask=true
CSET cb_seq_2_4=00000000
CSET cb_seq_2_4_disp=false
CSET cb_seq_2_4_k=false
CSET cb_seq_2_4_mask=true
CSET cb_sequence_1_max_skew=1
CSET cb_sequence_2_max_skew=1
CSET cb_sequence_length=1
CSET cc_keep_one_idle=false
CSET cc_seq_1_1=11111011
CSET cc_seq_1_1_disp=false
CSET cc_seq_1_1_k=true
CSET cc_seq_1_1_mask=false
CSET cc_seq_1_2=11011100
CSET cc_seq_1_2_disp=false
CSET cc_seq_1_2_k=true
CSET cc_seq_1_2_mask=false
CSET cc_seq_1_3=00000000
CSET cc_seq_1_3_disp=false
CSET cc_seq_1_3_k=true
CSET cc_seq_1_3_mask=true
CSET cc_seq_1_4=00000000
CSET cc_seq_1_4_disp=false
CSET cc_seq_1_4_k=true
CSET cc_seq_1_4_mask=true
CSET cc_seq_2_1=00000000
CSET cc_seq_2_1_disp=false
CSET cc_seq_2_1_k=true
CSET cc_seq_2_1_mask=true
CSET cc_seq_2_2=00000000
CSET cc_seq_2_2_disp=false
CSET cc_seq_2_2_k=true
CSET cc_seq_2_2_mask=true
CSET cc_seq_2_3=00000000
CSET cc_seq_2_3_disp=false
CSET cc_seq_2_3_k=true
CSET cc_seq_2_3_mask=true
CSET cc_seq_2_4=00000000
CSET cc_seq_2_4_disp=false
CSET cc_seq_2_4_k=true
CSET cc_seq_2_4_mask=true
CSET cc_sequence_length=2
CSET cdr_ph_adj_time=10100
CSET chan_bond_keep_align=false
CSET chan_bond_seq_2_cfg=00000
CSET clk_cor_precedence=CC
CSET clk_cor_repeat_wait=0
CSET column=Left
CSET com_burst_val=15
CSET comma_alignment=Even_Byte_Boundaries
CSET comma_double=false
CSET comma_mask=1111111111
CSET comma_preset=K28.5
CSET component_name=HTR
CSET dec_mcomma_detect=true
CSET dec_pcomma_detect=true
CSET dec_valid_comma_only=true
CSET decoding=8B/10B
CSET dfe_mode=Fixed_tap_mode
CSET disable_ac_coupling=false
CSET driver_swing=Use_TXDIFFCTRL_Port
CSET en_idle_reset_buf=false
CSET enable_dfe=false
CSET encoding=8B/10B
CSET errors_to_lose_sync=128
CSET fifo_lower_bounds=14
CSET fifo_upper_bounds=18
CSET highpass_pole_location=Use_RXEQPOLE_Port
CSET max_cb_level=7
CSET mcomma_detect=true
CSET minus_comma=1010000011
CSET oob_clk_divider=0000000
CSET pci_express_mode=false
CSET pcomma_detect=true
CSET pll_sata=false
CSET plus_comma=0101111100
CSET postemphasis_level=Use_TXPOSTEMPHASIS_Port
CSET ppm_offset=0_(Synchronous)
CSET preemphasis_level=Use_TXPREEMPHASIS_Port
CSET protocol_file=Start_from_scratch
CSET refclk_ac_coupling_x0_y0=false
CSET refclk_ac_coupling_x0_y1=false
CSET refclk_ac_coupling_x0_y10=false
CSET refclk_ac_coupling_x0_y11=false
CSET refclk_ac_coupling_x0_y12=false
CSET refclk_ac_coupling_x0_y13=false
CSET refclk_ac_coupling_x0_y14=false
CSET refclk_ac_coupling_x0_y15=false
CSET refclk_ac_coupling_x0_y16=false
CSET refclk_ac_coupling_x0_y17=false
CSET refclk_ac_coupling_x0_y18=false
CSET refclk_ac_coupling_x0_y19=false
CSET refclk_ac_coupling_x0_y2=false
CSET refclk_ac_coupling_x0_y20=false
CSET refclk_ac_coupling_x0_y21=false
CSET refclk_ac_coupling_x0_y22=false
CSET refclk_ac_coupling_x0_y23=false
CSET refclk_ac_coupling_x0_y3=false
CSET refclk_ac_coupling_x0_y4=false
CSET refclk_ac_coupling_x0_y5=false
CSET refclk_ac_coupling_x0_y6=false
CSET refclk_ac_coupling_x0_y7=false
CSET refclk_ac_coupling_x0_y8=false
CSET refclk_ac_coupling_x0_y9=false
CSET rx_datapath_width=16
CSET rx_decode_seq_match=true
CSET rx_divider=/1
CSET rx_en_idle_hold_cdr=false
CSET rx_en_idle_hold_dfe=true
CSET rx_en_idle_reset_fr=false
CSET rx_en_idle_reset_ph=false
CSET rx_en_mode_reset_buf=true
CSET rx_en_rate_reset_buf=true
CSET rx_en_realign_reset_buf=false
CSET rx_fifo_addr_mode=FULL
CSET rx_idle_hi_cnt=1000
CSET rx_idle_lo_cnt=0000
CSET rx_line_rate=2.5
CSET rx_oob_threshold=011
CSET rx_refclk_x0_y0=REFCLK1_Q0
CSET rx_refclk_x0_y1=REFCLK1_Q0
CSET rx_refclk_x0_y10=REFCLK1_Q2
CSET rx_refclk_x0_y11=REFCLK1_Q2
CSET rx_refclk_x0_y12=REFCLK1_Q3
CSET rx_refclk_x0_y13=REFCLK1_Q3
CSET rx_refclk_x0_y14=REFCLK1_Q3
CSET rx_refclk_x0_y15=REFCLK1_Q3
CSET rx_refclk_x0_y16=REFCLK1_Q4
CSET rx_refclk_x0_y17=REFCLK1_Q4
CSET rx_refclk_x0_y18=REFCLK1_Q4
CSET rx_refclk_x0_y19=REFCLK1_Q4
CSET rx_refclk_x0_y2=REFCLK1_Q0
CSET rx_refclk_x0_y20=REFCLK1_Q5
CSET rx_refclk_x0_y21=REFCLK1_Q5
CSET rx_refclk_x0_y22=REFCLK1_Q5
CSET rx_refclk_x0_y23=REFCLK1_Q5
CSET rx_refclk_x0_y24=REFCLK1_Q6
CSET rx_refclk_x0_y25=REFCLK1_Q6
CSET rx_refclk_x0_y26=REFCLK1_Q6
CSET rx_refclk_x0_y27=REFCLK1_Q6
CSET rx_refclk_x0_y28=REFCLK1_Q7
CSET rx_refclk_x0_y29=REFCLK1_Q7
CSET rx_refclk_x0_y3=REFCLK1_Q0
CSET rx_refclk_x0_y30=REFCLK1_Q7
CSET rx_refclk_x0_y31=REFCLK1_Q7
CSET rx_refclk_x0_y32=REFCLK1_Q8
CSET rx_refclk_x0_y33=REFCLK1_Q8
CSET rx_refclk_x0_y34=REFCLK1_Q8
CSET rx_refclk_x0_y35=REFCLK1_Q8
CSET rx_refclk_x0_y4=REFCLK1_Q1
CSET rx_refclk_x0_y5=REFCLK1_Q1
CSET rx_refclk_x0_y6=REFCLK1_Q1
CSET rx_refclk_x0_y7=REFCLK1_Q1
CSET rx_refclk_x0_y8=REFCLK1_Q2
CSET rx_refclk_x0_y9=REFCLK1_Q2
CSET rx_reference_clock=250.00
CSET rx_slide_mode=OFF
CSET rx_termination_voltage=MGTAVTT
CSET rxlossofsyncport=true
CSET rxrecclk_source=AUTO
CSET rxrundisp_indicates_cc=false
CSET rxusrclk_source=TXOUTCLK
CSET sas_max_comsas=52
CSET sas_min_comsas=40
CSET sata_burst_val=4
CSET sata_idle_val=4
CSET second_order_cdr_loop=false
CSET show_realign_comma=true
CSET sync_app=true
CSET termination_ctrl=00000
CSET termination_imp=50
CSET termination_ovrd=false
CSET trans_time_from_p2=60
CSET trans_time_non_p2=25
CSET trans_time_rate=FF
CSET trans_time_to_p2=100
CSET tx_datapath_width=16
CSET tx_divider=/1
CSET tx_drive_mode=DIRECT
CSET tx_en_rate_reset_buf=true
CSET tx_idle_assert_delay=100
CSET tx_idle_deassert_delay=010
CSET tx_line_rate=2.5
CSET tx_refclk_x0_y0=use_rx_pll
CSET tx_refclk_x0_y1=use_rx_pll
CSET tx_refclk_x0_y10=use_rx_pll
CSET tx_refclk_x0_y11=use_rx_pll
CSET tx_refclk_x0_y12=use_rx_pll
CSET tx_refclk_x0_y13=use_rx_pll
CSET tx_refclk_x0_y14=use_rx_pll
CSET tx_refclk_x0_y15=use_rx_pll
CSET tx_refclk_x0_y16=use_rx_pll
CSET tx_refclk_x0_y17=use_rx_pll
CSET tx_refclk_x0_y18=use_rx_pll
CSET tx_refclk_x0_y19=use_rx_pll
CSET tx_refclk_x0_y2=use_rx_pll
CSET tx_refclk_x0_y20=use_rx_pll
CSET tx_refclk_x0_y21=use_rx_pll
CSET tx_refclk_x0_y22=use_rx_pll
CSET tx_refclk_x0_y23=use_rx_pll
CSET tx_refclk_x0_y24=use_rx_pll
CSET tx_refclk_x0_y25=use_rx_pll
CSET tx_refclk_x0_y26=use_rx_pll
CSET tx_refclk_x0_y27=use_rx_pll
CSET tx_refclk_x0_y28=use_rx_pll
CSET tx_refclk_x0_y29=use_rx_pll
CSET tx_refclk_x0_y3=use_rx_pll
CSET tx_refclk_x0_y30=use_rx_pll
CSET tx_refclk_x0_y31=use_rx_pll
CSET tx_refclk_x0_y32=use_rx_pll
CSET tx_refclk_x0_y33=use_rx_pll
CSET tx_refclk_x0_y34=use_rx_pll
CSET tx_refclk_x0_y35=use_rx_pll
CSET tx_refclk_x0_y4=use_rx_pll
CSET tx_refclk_x0_y5=use_rx_pll
CSET tx_refclk_x0_y6=use_rx_pll
CSET tx_refclk_x0_y7=use_rx_pll
CSET tx_refclk_x0_y8=use_rx_pll
CSET tx_refclk_x0_y9=use_rx_pll
CSET tx_reference_clock=250.00
CSET tx_tdcc_cfg=11
CSET txoutclk_source=AUTO
CSET txpll_sata=00
CSET txrx_invert=00011
CSET txusrclk_source=TXOUTCLK
CSET use_cb=false
CSET use_cc=true
CSET use_comma_detect=true
CSET use_external_rxusrclk=false
CSET use_external_txusrclk=false
CSET use_gtx_x0_y0=true
CSET use_gtx_x0_y1=false
CSET use_gtx_x0_y10=false
CSET use_gtx_x0_y11=false
CSET use_gtx_x0_y12=false
CSET use_gtx_x0_y13=false
CSET use_gtx_x0_y14=false
CSET use_gtx_x0_y15=false
CSET use_gtx_x0_y16=false
CSET use_gtx_x0_y17=false
CSET use_gtx_x0_y18=false
CSET use_gtx_x0_y19=false
CSET use_gtx_x0_y2=false
CSET use_gtx_x0_y20=false
CSET use_gtx_x0_y21=false
CSET use_gtx_x0_y22=false
CSET use_gtx_x0_y23=false
CSET use_gtx_x0_y24=false
CSET use_gtx_x0_y25=false
CSET use_gtx_x0_y26=false
CSET use_gtx_x0_y27=false
CSET use_gtx_x0_y28=false
CSET use_gtx_x0_y29=false
CSET use_gtx_x0_y3=false
CSET use_gtx_x0_y30=false
CSET use_gtx_x0_y31=false
CSET use_gtx_x0_y32=false
CSET use_gtx_x0_y33=false
CSET use_gtx_x0_y34=false
CSET use_gtx_x0_y35=false
CSET use_gtx_x0_y4=false
CSET use_gtx_x0_y5=false
CSET use_gtx_x0_y6=false
CSET use_gtx_x0_y7=false
CSET use_gtx_x0_y8=false
CSET use_gtx_x0_y9=false
CSET use_no_rx=false
CSET use_no_tx=false
CSET use_port_comfinish=false
CSET use_port_cominitdet=false
CSET use_port_comsasdet=false
CSET use_port_comwakedet=false
CSET use_port_drp=false
CSET use_port_enmcommaalign=true
CSET use_port_enpcommaalign=true
CSET use_port_gtxtest=false
CSET use_port_loopback=true
CSET use_port_phystatus=false
CSET use_port_plllkdet=true
CSET use_port_plllkdeten=true
CSET use_port_pllpowerdown=false
CSET use_port_refclkpowerdown=false
CSET use_port_rxbufreset=false
CSET use_port_rxbufstatus=false
CSET use_port_rxbyteisaligned=false
CSET use_port_rxbyterealign=false
CSET use_port_rxcdrreset=true
CSET use_port_rxchariscomma=true
CSET use_port_rxcharisk=true
CSET use_port_rxcommadet=false
CSET use_port_rxlossofsync=true
CSET use_port_rxoversampleerr=false
CSET use_port_rxpolarity=true
CSET use_port_rxpowerdown=false
CSET use_port_rxrate=false
CSET use_port_rxrecclk=false
CSET use_port_rxreset=false
CSET use_port_rxrundisp=false
CSET use_port_rxslide=false
CSET use_port_rxstatus=false
CSET use_port_rxvalid=false
CSET use_port_txbufstatus=false
CSET use_port_txbypass8b10b=false
CSET use_port_txchardispmode=false
CSET use_port_txchardispval=false
CSET use_port_txcominit=false
CSET use_port_txcomsas=false
CSET use_port_txcomwake=false
CSET use_port_txdetectrx=false
CSET use_port_txelecidle=false
CSET use_port_txenprbstst=false
CSET use_port_txinhibit=false
CSET use_port_txkerr=false
CSET use_port_txoutclk=true
CSET use_port_txpolarity=true
CSET use_port_txpowerdown=false
CSET use_port_txprbsforceerr=false
CSET use_port_txrate=false
CSET use_port_txreset=false
CSET use_port_txrundisp=false
CSET use_prbs_detector=false
CSET use_resistor_cal_circuit=false
CSET use_rx_eq=false
CSET use_rx_oob=false
CSET use_rx_oversampling=false
CSET use_rxbuffer=true
CSET use_rxpllrefclk=false
CSET use_rxprbserr_loopback=false
CSET use_turbo_mode=false
CSET use_two_cb_sequences=false
CSET use_two_cc_sequences=false
CSET use_tx_oversampling=false
CSET use_txbuffer=true
CSET use_txpllrefclk=false
CSET wideband_highpass_mix=Use_RXEQMIX_Port
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-04-08T05:24:23Z
# END Extra information
GENERATE
# CRC: 995693ec