SFP assignment from top to bottom on module's front panel: DAQlink LDC DAQlink LSC Gigabit ethernet(normally not used) TTC Spartan chip IP address 192.168.1.(254 - 2*SN) Virtex chip IP address 192.168.1.(255 - 2*SN) Viretx chip memory map: 0x0 read/write write: bit 0 general reset write: bit 1 counter reset write: bit 2 reset LSC except GTX write: bit 3 reset LSC GTX write: bit 4 reset LDC except GTX write: bit 5 reset LDC GTX read: bit 15-0 LSC event counter bit 31-16 LSC Resend counter(packets resent) 0x1 read/write bit 0 test mode bit 1 pause test bit 14 inject error to LSC transmission(800Hz) bit 15 inject error to LDC transmission(800Hz) bit 31 if 0, backplane GbE connected to spartan6 and SFP GbE to virtex6 if 1, backplane GbE connected to Virtex6 and SFP GbE to spartan6 0x2 bit 31 LSC linkdown bit 30 LDC linkdown bit 15-12 SFP TxDisable(read/write) bit 11-8 SFP Transmit Fault bit 6-4 SFP loss of signal bit 3-0 SFP not present 0x3 bit 31-0 LDC received cms event counter 0x4 bit 31-0 LDC received cms event CRC error counter 0x5 bit 31-0 LDC accepted packet counter 0x6 bit 31-0 LDC aborted packet counter 0x7 bit 31-0 LDC acknowledged packet counter 0x8 bit 27-16 TTC L1 Bcnt register bit 15-0 TTC event number register 0x9 bit 31-0 TTC L1 orbit count register 0xa bit 23-16 TTC multi-bit error counter bit 15-8 TTC single bit error counter bit 7-0 TTC Bcnt error counter 0xb bit 31-16 LSC ID number read/write bit 15-0 LDC ID number read/write 0xc bit 31-24 ddr test error counter bit 23-16 ddr read data LSB bit 15-8 ddr write data LSB bit 7 ddr init done bit 6 ddr in test mode 0xd read: bit 15-0 LSC event counter bit 31-16 LSC Resend counter(packets resent) 0xe bit 23-0 Link throughput=readout/0x200000(Gbit/s) 0xf bit 27-16 AMC port test error bit 11-0 AMC port running DAQ link test procedure: connect fibre between LSC and LDC SFPs. reset LSC(write 1 to bit2 at address 0) start test mode(write 1 to bit0 at address 1) reset counters(write 1 to bit1 at address 0) on LDC module, register 3 should be counting and register 4 should always be 0. register 0xe should display a number close to 0x800000 to pause test data generation write 3 to register 1 to restart test data generation write 1 to register 1 to inject error into LSC sent data, write 0x4001. This injects error at about 800Hz. No counts in 4 should be observed. The throughput only slightly reduced. spartan chip memory map: 0x0 reads: bit 23-16 SN number bit 15-0 firmware version write: bit 0 general reset write: bit 4 start V6 reconfiguration 0x1 read only bit 0 FLASH busy 0x2 read/write bit 11-0 enables TTC clock to AMC modules 0x3 read only bit 31 if '1', virtex chip INIT_B is low bit 30 if '1', virtex chip DONE is low bit 23-0 configuration data CRC(not quite right yet) 0x4 bit 15-0 TTC event number register 0x5 bit 11-0 TTC L1 Bcnt register 0x6 bit 31-0 TTC L1 orbit count register 0x7 bit 7-0 TTC Bcnt error counter 0x8 bit 7-0 TTC single bit error counter 0x9 bit 7-0 TTC multi-bit error counter 0xa bit 7-0 T1 Serial Number