APr.17.2012 Spartan chip version 6 safeboot implemented. Now: FLASH address 0x0 contains an 80 bytes Header which should never be overwritten. FLASH address 0x100000 contains a Golden T2 file with version 0xffff. Normally this file does not need to be updated unless FLASH algorithm or ipbus firmware has to be updated. FLASH address 0x200000 contains the current AMC13T2 firmware FLASH address 0x400000 contains the current AMC13T1 firmware To update a module with T2 version earlier than v6, first use an older FLASH program to erase the old firmware(not necessary, but this results in a clean FLASH) then use python script p_flash_v12.py to write AMC13T2Header.mcs, AMC13T2Golden.mcs and the most up-to-date T1 and T2 versions into the FLASH. APr.13.2012 Spartan chip version 5 added Spartan6 reconfigure command(write 0x100 to register 0) APr.13.2012 Spartan chip version 4 Fixed a problem in ipbus. The same problem exists in Virtex chip which will be fixed in the next version. Mar.26.2012 Spartan chip now has version number 2 Fixed a bug in polarities of TTC_DATA outputs. TTC_DATA output timing adjusted to ease miniCTR design. SFP assignment from top to bottom on module's front panel: DAQlink LDC DAQlink LSC Gigabit ethernet(normally not used) TTC Spartan chip IP address 192.168.1.(254 - 2*SN) Virtex chip IP address 192.168.1.(255 - 2*SN) Viretx chip memory map: 0x0 read/write write: bit 0 general reset write: bit 1 counter reset write: bit 2 reset LSC except GTX write: bit 3 reset LSC GTX write: bit 4 reset LDC except GTX write: bit 5 reset LDC GTX read: 0 LSC Link Down read: 1 LSC Link almost full read: 2 monitor buffer full read: 3 monitor buffer empty read: 4 memory input fifo for monitored events overflow read: 5 TTC not ready read: 6 TTC bcnt error read: 7 TTC single bit error read: 8 TTC multi-bit error read: 9 TTC sync lost(L1A buffer overflow) read: 13 L1A overflow warning read: bit 31-24 T1 board SN 0x1 read/write bit 31-16 read only Virtex firmware version bit 15 if '1', trigger rule violation outputs TTS BUSY bit 14 if '1', monitor buffer full will stop event builder bit 13 if '1', send all data to downstream when ttc reset is received. if '0', flush all data when ttc reset is received. bit 12 if '1', TTS outputs correspond to bits 11-8 instead of TTS state when run bit(bit 0) is '1', this bit will be forced to '0' bit 11-8 used for TTS driver test bit 7 not used bit 6 if '0', memory test uses 64bit PRBS. If '1', uses 32 bit sequencial numbers. bit 5 '1' enables TTCrx broadcast commands bit 4 '1' enables memory self test bit 3 if '1', pauses event building. For debugging only bit 2 not used bit 1 '1' enables SLINK bit 0 run mode 0x2 monitoring event control R/W read: bit 31-24 read only. records the occurence of enabled error conditions happened to recorded events bit 23-16 read back what was written to. bit 15-0 scale factor, when bits 23-16 are not all zero, these bits are bit 15 set to '1' when when at least 128 events are in the buffer bit 14-8 monitor buffer write pointer bit 7-0 number of events captured after trigger event. Normally it should be 0x40, but could be less if event building stops due to other problems. write: if bits 23-16 are not all zeros, the monitor buffer keeps overwriting old events after 128 events are filled until the enabled error consition happens and it records 64 more events and stops. To re-enabling it, this register must be written again. If bits 23-16 are all zeros, buffering stops after becoming full. bit 23-18 not used bit 17 If set to '1', catches events when CRC error happened bit 16 If set to '1', catches events when evn/oc/bcn mismatch happened bit 15-0 scale factor( = contents + 1) 0x3 HTR channel enable register R/w read: bit 31-28 always '0' bit 27 '1' indicates AMC12 Link Ready bit 26 '1' indicates AMC11 Link Ready bit 25 '1' indicates AMC10 Link Ready bit 24 '1' indicates AMC9 Link Ready bit 23 '1' indicates AMC8 Link Ready bit 22 '1' indicates AMC7 Link Ready bit 21 '1' indicates AMC6 Link Ready bit 20 '1' indicates AMC5 Link Ready bit 19 '1' indicates AMC4 Link Ready bit 18 '1' indicates AMC3 Link Ready bit 17 '1' indicates AMC2 Link Ready bit 16 '1' indicates AMC1 Link Ready bit 15-12 always '0' bit 11 '1' enables AMC12 bit 10 '1' enables AMC11 bit 9 '1' enables AMC10 bit 8 '1' enables AMC9 bit 7 '1' enables AMC8 bit 6 '1' enables AMC7 bit 5 '1' enables AMC6 bit 4 '1' enables AMC5 bit 3 '1' enables AMC4 bit 2 '1' enables AMC3 bit 1 '1' enables AMC2 bit 0 '1' enables AMC1 0x5 HTR-AMC link version check Read only bit 31-12 always '0' bit 11 '1' AMC12 link version wrong bit 10 '1' AMC11 link version wrong bit 9 '1' AMC10 link version wrong bit 8 '1' AMC9 link version wrong bit 7 '1' AMC8 link version wrong bit 6 '1' AMC7 link version wrong bit 5 '1' AMC6 link version wrong bit 4 '1' AMC5 link version wrong bit 3 '1' AMC4 link version wrong bit 2 '1' AMC3 link version wrong bit 1 '1' AMC2 link version wrong bit 0 '1' AMC1 link version wrong 0x30 V6 die temperature in unit of 0.1 degree Celsius 0x31 1.0V analog power voltage in millivolt(available for SN >= 0x10 only) 0x32 1.2V analog power voltage in millivolt(available for SN >= 0x10 only) 0x33 1.0V power voltage in millivolt 0x34 1.5V power voltage in millivolt(available for SN >= 0x10 only) 0x35 2.5V power voltage in millivolt 0x36 3.3V power voltage in millivolt(available for SN >= 0x10 only) 0x37 3.6V power voltage in millivolt(available for SN >= 0x10 only) 0x38 12V power voltage in millivolt(available for SN >= 0x10 only) 0x800-0x83F AMC1 counter 0x0-1 AMC accept counter 0x2-3 AMC ACK counter 0x4-5 AMC L1A abort counter 0x6-7 AMC Evn mismatch counter 0x8-9 AMC OrN mismatch counter 0xa-b AMC BcN mismatch counter 0xc-d AMC event counter 0xe-f AMC Coutner ACK counter 0x10-11 AMC Resend counter 0x12-13 AMC event CRC error counter 0x14-15 AMC event trailer Evn mismatch error counter 0x20-21 total word counter 0x22-23 single bit error counter 0x24-25 multi-bit error counter 0x26-27 BC0 mismatch error counter 0x28-29 bcnt mismatch error counter 0x2a-2b ReSend counter 0x2c-2d Accept counter 0x2e-2f ACK counter 0x30-31 Abort counter 0x32-33 Receive Event counter 0x34-35 Read Event counter 0x840-0x87F AMC2 counter 0x880-0x8bF AMC3 counter 0x8c0-0x8FF AMC4 counter 0x900-0x93F AMC5 counter 0x940-0x97F AMC6 counter 0x980-0x9bF AMC7 counter 0x9c0-0x9fF AMC8 counter 0xa00-0xa3F AMC9 counter 0xa40-0xa7F AMC10 counter 0xa80-0xabF AMC11 counter 0xac0-0xafF AMC12 counter 0x4000-0x7fff memory read window spartan chip memory map: 0x0 reads: bit 23-16 SN number bit 15-0 T2 firmware version write: bit 0 general reset write: bit 4 start V6 reconfiguration write: bit 8 start both S6 and V6 reconfiguration 0x1 read/write read bit 0 FLASH busy write sends data stored in FLASH wbuf to FLASH memory chip bit 8-0 specifies number of (clocks/8 -1) to be sent to the FLASH memory (depends on the type of the FLASH command and number of bytes to be read or written) 0x2 read/write bit 11-0 enables TTC clock to AMC modules 0x3 read only bit 31 if '1', virtex chip INIT_B is low bit 30 if '1', virtex chip DONE is low bit 23-0 configuration data CRC 0x4 bit 15-0 TTC event number register 0x5 bit 11-0 TTC L1 Bcnt register 0x6 bit 31-0 TTC L1 orbit count register 0x7 bit 7-0 TTC Bcnt error counter 0x8 bit 7-0 TTC single bit error counter 0x9 bit 7-0 TTC multi-bit error counter 0xa bit 7-0 T1 Serial Number 0x1000 thru 0x107f read/write FLASH write buffer always write FLASH command(including FLASH address if any) to address 0x1000 for page write command, attach the write data starting at address 0x1001 you can read back what you have writen to the write buffer. 0x1080 thru 0x10ff read only FLASH read buffer you read whatever data are returned from the FLASH memory here