Mar. 27 2014 T1 version 0x2e and T2 version 0x1c ipbus interface code modified. transactor_sm.vhd changed back to module come with ipbus_2_0_v1.r27848 Mar. 19 2014 T1 version 0x2d and T2 version 0x1b problem detected, replace transcator_sm.vhd with the home-modified version Mar. 18 2014 T1 version 0x2c and T2 version 0x1a ipbus firmware updated to ipbus_2_0_v1.r27848 Dec. 12 2013 T1 version 0x2b and T2 version 0x19 A bug in the SPI interface since T2 version 0x17 causes SPI data always to be written to both T1 and T2 and the SPI read data is always from T2. Modules with T2 version 0x17 and 0x18 must be updated to 0x19 in order to get correct IP address. Jun.24.2013 Virtex chip version 0x2b AMC link runs at 5.0Gb/s now May.17.2013 Virtex chip version 0x2a New version uses ipbus2, FPGA DNA registers added(0x1e and 0x1f) May.8.2013 spartan chip version 0x17 New version uses ipbus2, FPGA DNA registers added(0xe and 0xf) Jan.27.2013 spartan chip version 0x11 added register 0xd, which could send TTC clock and data to additional AMC modules other than specified by V6's register 0x3. Jan.11.2013 Virtex chip version 0x25 fixed a TTC timing problem Jan.9.2013 Virtex chip version 0x23 fixed a bug in the TTS module Jan.7.2013 Virtex chip version 0x22 fixed a bug in the new feature added to 0x21 Jan.6.2013 Virtex chip version 0x21 definition of register 0x2 changed. Now bits 22-19 control the scaling factor when bit 23 is set to '1' Nov.12.2012 Virtex chip version 0x20 DAQLDC and DAQLSC works correctly starting from this version. by setting bit 7 of register 1, events received by DAQLDC can be stored in the monitor event buffer. TTS output now can be used as TTC clock input TTC internal trigger implemented Please read instructions at the end of this document about details of internal TTC clock and L1A generation Nov.5.2012 Virtex chip version 0x1f Both DAQLDC and DAQLSC now instantiated. Counters added. IP address setting through MMC fixed since v0x1d and s0xf Oct.5.2012 Virtex chip version 0x1c added new bit(23rd) to register 0x2 to control monitoring event scaling Oct.4.2012 Virtex chip version 0x1b added more counter and status registers for links to the HTR. registers from 0x800 through 0xe13 are mainly for diagnostic purposes in case of event building problems. Oct.1.2012 spartan chip version 0xd fixed a problem to enable program FLASH while Virtex chip is not configured Sept.30.2012 Virtex chip version 0x1a fixed a reset problem fixed HTR Header CRC error and mismatch error bits problem(were always 0) added HTR interface counters for evn, bcn and ocn mismatch An error in HTR monitor counter address map corrected, new counters added to the map. local L1A added. It is enabled by bit 2 of register 1. new local L1A control register 0x1c added version 0x1a is a revision of version 0x17 Sept.12.2012 Virtex chip version 0x17 DAQLSC port polarity modified upon request from DAQ group version 0x17 is a revision of version 0x16 Sept.11.2012 Virtex chip version 0x16 A bug in ddr control fixed. SDRAM write page address can be read at 0xb version 0x16 is a revision of version 0x14 Sept.11.2012 Virtex chip version 0x15 A bug in ddr control fixed. SDRAM write page address can be read at 0xb version 0x15 is a revision of version 0x13 Sept.10.2012 Virtex chip version 0x14 A bug in fake HTR events fixed. version 0x14 is a revision of version 0x12 Sept.7.2012 Virtex chip version 0x13 A bug in fake HTR events fixed. version 0x13 is a revision of version 0x10 Aug.13.2012 Virtex chip version 0x12 ipbus register Aug.10.2012 Virtex chip version 0x11 LSCDAQ replaced by DAQ group's version Jul.16.2012 Virtex chip version 0x10 Checking of individual HTR CRC in built event added at HTR_if output. Corresponding Error counter added. Jul.9.2012 Virtex chip version f bug fix for fake HTR events building Jul.7.2012 Virtex chip version e bug fix for monitor buffer writing Jul.6.2012 Virtex chip version d New data format implemented. New ipbus memory readout should have fixed the readout problem. Jul.3.2012 Spartan chip version b This version fixed a bug in reconfigure T1 Virtex chip Jun.30.2012 Virtex chip version c a bug in DAQLSC instantiation fixed(refclk used instead of sysclk for LinkClk) Jun.21.2012 Spartan chip version 9 This version works for both xc6vlx130T and xc6vlx240T Jun.20.2012 Virtex chip version b AMC Link RxLossOfSync added to register 0x5(used during AMC13 test on test stand) HTR_if module now has a test event generation feature for testing purposes. AMC module numbering in HTR data header changed to 0 - 11 ddr3 dm pins connected to ground for new T1 boards Jun.16.2012 Virtex chip version a Bc0_lock status of AMC modules added to register 6 HTR summary V and C bits changed to '1' for mismatch and bad CRC TTS output added Jun.14.2012 Virtex chip version 9 fixed a problem in ipbus readout of ddr memory. fixed a problem in SFP ROM readout Jun.13.2012 Virtex chip version 8 I2C registeres added Jun.12.2012 Virtex chip version 7 HTR link implemented major change in register address map Jun.11.2012 Spartan chip version 8 A bug is fixed in reprogramming V6 command. This bug also exists in v6. Jun.4.2012 Spartan chip version 7 change register 0x2 to read only. (The value written to V6 0x3) APr.17.2012 Spartan chip version 6 safeboot implemented. Now: FLASH address 0x0 contains an 80 bytes Header which should never be overwritten. FLASH address 0x100000 contains a Golden T2 file with version 0xffff. Normally this file does not need to be updated unless FLASH algorithm or ipbus firmware has to be updated. FLASH address 0x200000 contains the current AMC13T2 firmware FLASH address 0x400000 contains the current AMC13T1 firmware To update a module with T2 version earlier than v6, first use an older FLASH program to erase the old firmware(not necessary, but this results in a clean FLASH) then use python script p_flash_v12.py to write AMC13T2Header.mcs, AMC13T2Golden.mcs and the most up-to-date T1 and T2 versions into the FLASH. APr.13.2012 Spartan chip version 5 added Spartan6 reconfigure command(write 0x100 to register 0) APr.13.2012 Spartan chip version 4 Fixed a problem in ipbus. The same problem exists in Virtex chip which will be fixed in the next version. Mar.26.2012 Spartan chip now has version number 2 Fixed a bug in polarities of TTC_DATA outputs. TTC_DATA output timing adjusted to ease miniCTR design. SFP assignment from top to bottom on module's front panel: DAQlink LDC (if module configured with AMC13T1EB.bit, this is a backplane Ethernet feedthrough port) DAQlink LSC Gigabit ethernet(normally not used) TTC Spartan chip IP address 192.168.1.(254 - 2*SN) Virtex chip IP address 192.168.1.(255 - 2*SN) Viretx chip memory map: 0x0 read/write write: bit 0 general reset write: bit 1 counter reset write: bit 2 reset LSC except GTX write: bit 3 reset LSC GTX write: bit 4 reset LDC except GTX write: bit 5 reset LDC GTX write: bit 10 if bit 10 reads '0', it sends a burst of local L1A if bit 10 reads '1', it only resets it to '0' write: bit 11 sends event number reset thru TTC when in local L1A mode write: bit 12 sends orbut number reset thru TTC when in local L1A mode write: bit 26 set continous local L1A(setup with register 0x1c) read: 0 LSC Link Down read: 1 LSC Link almost full read: 2 monitor buffer full read: 3 monitor buffer empty read: 4 memory input fifo for monitored events overflow read: 5 TTC not ready read: 6 TTC bcnt error read: 7 TTC single bit error read: 8 TTC multi-bit error read: 9 TTC sync lost(L1A buffer overflow) read: 10 continous local L1A on(setup with register 0x1c) read: 13 L1A overflow warning read: bit 31-24 T1 board SN 0x1 read/write bit 31-16 read only Virtex firmware version bit 15 if '1', save received DAQ data to moniter buffer bit 14 if '1', monitor buffer full will stop event builder bit 13 if '1', send all data to downstream when ttc reset is received. if '0', flush all data when ttc reset is received. bit 12 if '1', TTS outputs correspond to bits 3-0 of register 0x19 instead of TTS state when run bit(bit 0) is '1', this bit will be forced to '0' bit 11-9 not used bit 8 if '1', TTS output is TTC signal output(you have to set bit 2 also to use this feature) bit 7 if '1', generate fake event upon receiving L1A bit 6 if '0', memory test uses 64bit PRBS. If '1', uses 32 bit sequencial numbers. bit 5 '1' enables non-standard TTCrx broadcast commands bit 4 '1' enables memory self test bit 3 if '1', pauses event building. For debugging only bit 2 if '1', uses internally generated L1A bit 1 '1' enables SLINK bit 0 run mode 0x2 monitoring event control R/W read: bit 31-24 read only. records the occurence of enabled error conditions happened to recorded events bit 23-16 read back what was written to. bit 15-0 scale factor, when bits 23-16 are not all zero, these bits are bit 15 set to '1' when when at least 128 events are in the buffer bit 14-8 monitor buffer write pointer bit 7-0 number of events captured after trigger event. Normally it should be 0x40, but could be less if event building stops due to other problems. write: if bits 23-16 are not all zeros, the monitor buffer keeps overwriting old events after 128 events are filled until the enabled error condition happens and it records 64 more events and stops. To re-enabling it, this register must be written again. If bits 23-16 are all zeros, buffering stops after becoming full. bit 23 If set to '1', bit 22-19 determine which events will be saved bit 22-19 when x"0", only saves events which evn has lower 20 bits all 0 when x"1", only saves events which evn has lower 19 bits all 0 when x"2", only saves events which evn has lower 18 bits all 0 when x"3", only saves events which evn has lower 17 bits all 0 when x"4", only saves events which evn has lower 16 bits all 0 when x"5", only saves events which evn has lower 15 bits all 0 when x"6", only saves events which evn has lower 14 bits all 0 when x"7", only saves events which evn has lower 13 bits all 0 when x"8", only saves events which evn has lower 12 bits all 0 when x"9", only saves events which evn has lower 11 bits all 0 when x"a", only saves events which evn has lower 10 bits all 0 when x"b", only saves events which evn has lower 9 bits all 0 when x"c", only saves events which evn has lower 8 bits all 0 when x"d", only saves events which evn has lower 7 bits all 0 when x"e", only saves events which evn has lower 6 bits all 0 when x"f", only saves events which evn has lower 5 bits all 0 bit 18 not used bit 17 If set to '1', catches events when CRC error happened bit 16 If set to '1', catches events when evn/oc/bcn mismatch happened bit 15-0 scale factor( = contents + 1). Note: if bit 18 is set to '1', these bits are ignored. 0x3 HTR channel enable register R/w read: bit 31-28 always '0' bit 27 '1' indicates AMC12 Link Ready bit 26 '1' indicates AMC11 Link Ready bit 25 '1' indicates AMC10 Link Ready bit 24 '1' indicates AMC9 Link Ready bit 23 '1' indicates AMC8 Link Ready bit 22 '1' indicates AMC7 Link Ready bit 21 '1' indicates AMC6 Link Ready bit 20 '1' indicates AMC5 Link Ready bit 19 '1' indicates AMC4 Link Ready bit 18 '1' indicates AMC3 Link Ready bit 17 '1' indicates AMC2 Link Ready bit 16 '1' indicates AMC1 Link Ready bit 15-12 always '0' bit 11 '1' enables AMC12 bit 10 '1' enables AMC11 bit 9 '1' enables AMC10 bit 8 '1' enables AMC9 bit 7 '1' enables AMC8 bit 6 '1' enables AMC7 bit 5 '1' enables AMC6 bit 4 '1' enables AMC5 bit 3 '1' enables AMC4 bit 2 '1' enables AMC3 bit 1 '1' enables AMC2 bit 0 '1' enables AMC1 0x4 SFP Control and Status register R/w read: bit 31-16 SLINK ID bit 15 '1' disables TTS transmitter bit 14 '1' disables SLINK transmitter bit 13 '1' disables SLINK spare transmitter bit 12 '1' disables SFP Ethernet transmitter bit 11 '1' indicates TTS TxFault bit 10 '1' indicates SLINK TxFault bit 9 '1' indicates SLINK spare TxFault bit 8 '1' indicates SFP Ethernet TxFault bit 7 '1' indicates TTC_LOS or TTC_LOL bit 6 '1' indicates SLINK Receiver signal lost bit 5 '1' indicates SLINK spare Receiver signal lost bit 4 '1' indicates SFP Ethernet Receiver signal lost bit 3 '1' indicates TTC/TTS SFP absent bit 2 '1' indicates SLINK SFP absent bit 1 '1' indicates SLINK spare SFP absent bit 0 '1' indicates Ethernet SFP absent write: bit 15-12 write '1' to disable the transmitter other bits not writable 0x5 HTR-AMC link version check and loss of sync status Read only bit 31-28 always '0' bit 27-16 '1' indicates loss of sync for corresponding AMC port bit 15-12 always '0' bit 11 '1' AMC12 link version wrong bit 10 '1' AMC11 link version wrong bit 9 '1' AMC10 link version wrong bit 8 '1' AMC9 link version wrong bit 7 '1' AMC8 link version wrong bit 6 '1' AMC7 link version wrong bit 5 '1' AMC6 link version wrong bit 4 '1' AMC5 link version wrong bit 3 '1' AMC4 link version wrong bit 2 '1' AMC3 link version wrong bit 1 '1' AMC2 link version wrong bit 0 '1' AMC1 link version wrong 0x6 AMC trigger data BC0 compensation register Read/write bit 31-28 always '0' bit 27 '1' AMC12 BC0 locked (Read only) bit 26 '1' AMC11 BC0 locked (Read only) bit 25 '1' AMC10 BC0 locked (Read only) bit 24 '1' AMC9 BC0 locked (Read only) bit 23 '1' AMC8 BC0 locked (Read only) bit 22 '1' AMC7 BC0 locked (Read only) bit 21 '1' AMC6 BC0 locked (Read only) bit 20 '1' AMC5 BC0 locked (Read only) bit 19 '1' AMC4 BC0 locked (Read only) bit 18 '1' AMC3 BC0 locked (Read only) bit 17 '1' AMC2 BC0 locked (Read only) bit 16 '1' AMC1 BC0 locked (Read only) bit 15-5 always '0' bit 4-0 set BCo compensation, default to 0x18 0x7 DCC source ID register Read/write read: bit 31-24 always '0' bit 23-0 source ID write: bit 31-24 not used bit 23-20 evt_ty bit 19-12 evt_stat bit 11-0 source ID 0x8 OrN/BCNT offset register R/W read: bit 31-20 always '0' bit 19-16 OrN offset bit 15-13 always '0' bit 12 if '1', ttc_bcntres only works once after system reset bit 11-0 BCNT offset write: bit 31-20 always '0' bit 19-16 OrN offset bit 15-13 always '0' bit 12 ttc_bcntres control bit bit 11-0 BCNT offset 0x9 calibration window register R/W read: bit 31 if '1', calibration events enabled bit 30-28 always '0' bit 27-16 calibration window upper limit(included) bit 15-12 current Laser position bit 11-0 calibration window lower limit(not included) write: bit 31 default to '1', enabling calibration events bit 30-28 always '0' bit 27-22 fixed as "110110" bit 21-16 settable part of calibration window upper limit,3519 maximum(included), default to "100110" bit 15-12 read only bit 11-6 fixed as "110110" bit 5-0 settable part of calibration window upper limit,3456 minimum(not included), default to "011101" offset 0xa memory status register lower word Read only For debugging purposes only offset 0xb memory status register high word Read only For debugging purposes only bit 10-0 SDRAM write page address offset 0xc SDRAM page register R/W read: bit 31-12 always '0' bit 11-0 SDRAM page number write: If run bit is '1', write '0' to bit 0 of this register increments page number by 1 If run bit is '1', write '1' to bit 0 of this register increments page number by 128 bit 31-12 not used bit 11-0 SDRAM page number, each page is 64kbytes size In catch mode, each catched event occupies 128 pages, 64 events following the bad event will be captured, and normally 63 events before the bad event will also be there. In catch mode, bits 6-0 of the page address is offset so that when these bits are all 0 points to the bad event. offset 0xd monitoring event word count Read only read: bit 31 always '0' bit 30-24 all 0 if not in catch mode, otherwise gives the number of events stored after the bad event bit 23-16 all 0 if not in catch mode, otherwise gives the type of error of the bad event bit 15-14 always '0' bit 13-0 monitored event size in 32-bit word. In run mode, it returns '0' if there is no data avaiable offset 0xe monitored event count Read only read: bit 31-12 always '0' bit 11-0 number of unread events captured by monitor offset 0xf HTR CRC check error count of built events Read only offset 0x10 LSCDAQ ack_cntr Read only offset 0x11 LSCDAQ pckt_cntr Read only offset 0x12 LSCDAQ retransmit_cntr Read only offset 0x13 LSCDAQ event_cntr Read only offset 0x14 LSCDAQ word_cntr Read only offset 0x15 LSCDAQ sync_loss_cntr Read only offset 0x16 LSCDAQ status output bits 31-0 Read only offset 0x17 LSCDAQ status output bits 63-32 Read only offset 0x18 payload size in 16bit words of faked HTR event R/W read: bit 31-11 always '0' bit 10-0 payload size write: bit 31-11 not used bit 10-0 payload size in 16bit words of faked HTR event(default 0x400) offset 0x19 TTS test pattern register R/W read: bit 31-4 always '0' bit 3-0 TTS test pattern write: bit 31-4 always '0' bit 3-0 TTS test pattern offset 0x1c Local L1A control register bit 31-30 type of L1A "00": L1A per Orbit "10": L1A per Bunch crossing "11": random L1A bit 29-28 trigger rules enforced "00": all four rules "01": all except rule 4 "10": rules 1 and 2 "11": only rule 1 bit 27-16 number of L1A generated in a burst equals its contents N+1. One L1A if all zero bit 15-0 determines L1A rates generated if in per orbit mode, it generates a L1A every N+1 orbits at BCN = 0x1f4 if in per BX mode, it generates a L1A every N+1 Bx trigger rules are applied if in random mode, it generates a L1A at 2*N/s trigger rules are applied 0x1e Viretx6 chip DNA bit 31-0 0x1f bit 31-25 always reads 0 bit 24-0 Virtex6 chip DNA bit 56-32 0x30 V6 die temperature in unit of 0.1 degree Celsius 0x31 1.0V analog power voltage in millivolt(available for SN >= 0x10 only) 0x32 1.2V analog power voltage in millivolt(available for SN >= 0x10 only) 0x33 1.0V power voltage in millivolt 0x34 1.5V power voltage in millivolt(available for SN >= 0x10 only) 0x35 2.5V power voltage in millivolt 0x36 3.3V power voltage in millivolt(available for SN >= 0x10 only) 0x37 3.6V power voltage in millivolt(available for SN >= 0x10 only) 0x38 12V power voltage in millivolt(available for SN >= 0x10 only) 0x40 TTC single bit error counter bits[31:0] 0x41 bit 31-16 always 0 bit 15-0 TTC single bit error counter bits[47:32] 0x42 TTC multi-bit error counter bits[31:0] 0x43 bit 31-16 always 0 bit 15-0 TTC multi-bit error counter bits[47:32] 0x44 TTC BC0 error counter bits[31:0] 0x45 bit 31-16 always 0 bit 15-0 TTC BC0 error counter bits[47:32] 0x46 L1A counter bits[31:0] 0x47 bit 31-16 always 0 bit 15-0 L1A counter bits[47:32] 0x48 run time counter bits[31:0] 0x49 bit 31-16 always 0 bit 15-0 run time counter bits[47:32] 0x4a ready time counter bits[31:0] 0x4b bit 31-16 always 0 bit 15-0 ready time counter bits[47:32] 0x4c busy time counter bits[31:0] 0x4d bit 31-16 always 0 bit 15-0 busy time counter bits[47:32] 0x4e L1A sync lost time counter bits[31:0] 0x4f bit 31-16 always 0 bit 15-0 L1A sync lost time counter bits[47:32] 0x50 L1A overflow warning time counter bits[31:0] 0x51 bit 31-16 always 0 bit 15-0 L1A overflow warning time counter bits[47:32] 0x52 SLINK total word counter bits[31:0] 0x53 bit 31-16 always 0 bit 15-0 SLINK total word counter bits[47:32] 0x54 SLINK total event counter bits[31:0] 0x55 bit 31-16 always 0 bit 15-0 SLINK total event counter bits[47:32] 0x56 total monitored event counter bits[31:0] 0x57 bit 31-16 always 0 bit 15-0 total monitored event counter bits[47:32] offset 0x80 DAQLDC register for func(0)='1' R/W offset 0x81 DAQLDC register for func(1)='1' R/W offset 0x82 DAQLDC register for func(2)='1' R/W offset 0x83 DAQLDC status register Read only bit 31-4 always '0' bit 3 memory FIFO for DAQLDC output enabled bit 2 DAQLDC sync_loss bit 1 DAQLDC func_done bit 0 DAQLDC link_init_done offset 0x84 DAQLDC status_port register bit 31-0 Read only offset 0x85 DAQLDC status_port register bit 63-32 Read only offset 0x86 DAQLDC data_seq_num register Read only offset 0x87 DAQLDC cmd_seq_num register Read only offset 0x90 DAQLDC word_cntr Read only written to FIFO offset 0x91 DAQLDC ctrl_cntr Read only written to FIFO offset 0x92 DAQLDC event_cntr Read only written to FIFO offset 0x93 DAQLDC rcv_word_cntr Read only read from FIFO offset 0x94 DAQLDC rcv_ctrl_cntr Read only read from FIFO offset 0x95 DAQLDC rcv_event_cntr Read only read from FIFO offset 0x96 DAQLDC fifo_werr_cntr Read only offset 0x97 DAQLDC CRC_err_cntr Read only offset 0x98 DAQLDC sync_loss_cntr Read only offset 0x99 DAQLDC ack_cntr Read only offset 0x9a DAQLDC valid_pckt_cntr Read only offset 0x9b DAQLDC all_pckt_cntr Read only offset 0x9c DAQLDC bad_pckt_cntr Read only offset 0x9d DAQLDC BackP_cntr Read only offset 0x9e DAQLDC Ctrl_err_cntr Read only offset 0x9f DAQLDC data rate in bytes/s Read only 0x100-0x11f Ethernet SFP ROM data(first 128 bytes, little endian) 0x120-0x13f SLINK spare SFP ROM data(first 128 bytes, little endian) 0x140-0x15f SLINK SFP ROM data(first 128 bytes, little endian) 0x160-0x17f TTC/TTS SFP ROM data(first 128 bytes, little endian) 0x180-0x183 AMC reference clock oscillator Si570 data 0x180 bit 7-0 reads 0 bit 15-8 register7 before modification bit 23-16 register8 before modification bit 31-24 register9 before modification 0x181 bit 7-0 register10 before modification bit 15-8 register11 before modification bit 23-16 register12 before modification bit 31-24 reads 0 0x182 bit 7-0 reads 0 bit 15-8 register7 after modification bit 23-16 register8 after modification bit 31-24 register9 after modification 0x183 bit 7-0 register10 after modification bit 15-8 register11 after modification bit 23-16 register12 after modification bit 31-24 reads 0 0x184-0x187 SLINK reference clock oscillator Si570 data 0x184 bit 7-0 reads 0 bit 15-8 register7 before modification bit 23-16 register8 before modification bit 31-24 register9 before modification 0x185 bit 7-0 register10 before modification bit 15-8 register11 before modification bit 23-16 register12 before modification bit 31-24 reads 0 0x186 bit 7-0 reads 0 bit 15-8 register7 after modification bit 23-16 register8 after modification bit 31-24 register9 after modification 0x187 bit 7-0 register10 after modification bit 15-8 register11 after modification bit 23-16 register12 after modification bit 31-24 reads 0 0x800-0x87F AMC1 counter 0x0-1 AMC accept counter 0x2-3 AMC ACK counter 0x4-5 AMC L1A abort counter 0x6-7 AMC Evn mismatch counter 0x8-9 AMC OrN mismatch counter 0xa-b AMC BcN mismatch counter 0xc-d AMC received event counter 0xe-f AMC Counter ACK counter 0x10-11 AMC Resend counter 0x12-13 AMC event CRC error counter 0x14-15 AMC event trailer Evn mismatch error counter 0x16-17 AMC event buffer almost full time counter 0x18-19 total word counter at link input 0x1a-1b header word counter at link input 0x1c-1d trailer word counter at link input 0x1e-1f event number error counter at link input 0x20 AMC DAQ_Link ststus bit 31-16 Always 0 bit 15 FIFO_ovf bit 14-13 Always 0 bit 12-8 EventStatus_ra bit 7-6 Always 0 bit 4-0 EventStatus_wa 0x22 AMC DAQ_Link ststus bit 31-15 Always 0 bit 14-0 DataBuf_wa 0x24 AMC DAQ_Link ststus bit 31-15 Always 0 bit 14-0 DataBuf_ra 0x26 AMC DAQ_Link ststus bit 31-10 Always 0 bit 9-0 L1Ainfo_wa 0x28 AMC DAQ_Link ststus bit 31-10 Always 0 bit 9-0 L1Ainfo_ra 0x2a AMC DAQ_Link ststus bit 31-10 Always 0 bit 9-0 HTRinfo_wa 0x2c AMC DAQ_Link ststus bit 31-10 Always 0 bit 9-0 HTRinfo_ra 0x2e AMC DAQ_Link ststus bit 31-9 Always 0 bit 8-4 EventCnt bit 3-2 ReSendQue_a bit 1 AlmostFull bit 0 dataFIFO_Empty 0x40-41 total word counter 0x42-43 single bit error counter 0x44-45 multi-bit error counter 0x46-47 BC0 mismatch error counter 0x48-49 bcnt mismatch error counter 0x4a-4b ReSend counter 0x4c-4d Accept counter 0x4e-4f Counter Accept counter 0x50-51 ACK counter 0x52-53 Receive Event counter 0x54-55 Read Event counter 0x56-57 Data abort counter 0x58-59 Counter abort counter 0x5a-5b abort due to ACKNUM_full counter 0x5c-5d abort due to EventBuf_full counter 0x5e-5f abort due to EventInfo_full counter 0x60-61 abort due to bad SEQ counter 0x62-63 abort due to bad CRC counter 0x64-65 abort due to bad frame counter 0x66-67 abort due to bad K character counter 0x68-69 BUSY time counter(reserved) 0x6a-6b HTR event EVN mismatch counter 0x6c-6d HTR event BCN mismatch counter 0x6e-6f HTR event OCN mismatch counter 0x70 HTR_Link ststus bit 31-16 Always 0 bit 15 EventBuf_ovf_flag bit 14 Always 0 bit 13-0 EventBuf_wa 0x72 HTR_Link ststus bit 31-14 Always 0 bit 13-2 EventBuf_ra bit 1-0 Always 0 0x74 HTR_Link ststus bit 31-14 Always 0 bit 13-4 EventBuf_rap bit 3-0 Always 0 0x76 HTR_Link ststus bit 31-10 Always 0 bit 9-0 L1Ainfo_wa 0x78 HTR_Link ststus bit 31-10 Always 0 bit 9-0 L1Ainfo_ra 0x7a HTR_Link ststus bit 31-16 Always 0 bit 15 HTR_L1A_full bit 14 Always 0 bit 13-8 HTR_L1A bit 7-0 L1Ainfo_wap 0x7c HTR_Link ststus bit 31-16 Always 0 bit 15-14 ReSendQue_a bit 13-12 rfifo_a bit 11-10 ACKNUM_a bit 9 reset_sync(3) bit 8 RXLOSSOFSYNC(1) bit 7 TxResetDone bit 6 RxResetDone bit 5 RxPllLock bit 4 InitLink bit 3-0 TxState 0x7e HTR_Link ststus bit 31-15 Always 0 bit 4 got_HTR_BC0 bit 3 TTC_lock bit 2 BC0_lock bit 1 HTR_RdEnToggle bit 0 EventInfoToggle 0x880-0x8FF AMC2 counter 0x900-0x97F AMC3 counter 0x980-0x9FF AMC4 counter 0xa00-0xa7F AMC5 counter 0xa80-0xaFF AMC6 counter 0xb00-0xb7F AMC7 counter 0xb80-0xbFF AMC8 counter 0xc00-0xc7F AMC9 counter 0xc80-0xcFF AMC10 counter 0xd00-0xd7F AMC11 counter 0xd80-0xdFF AMC12 counter 0xe00 HTR_if status for AMC1 bit 31-28 TTS bit 27-20 TrigData bit 19-0 EventInfo 0xe01 HTR_if status for AMC2 0xe02 HTR_if status for AMC3 0xe03 HTR_if status for AMC4 0xe04 HTR_if status for AMC5 0xe05 HTR_if status for AMC6 0xe06 HTR_if status for AMC7 0xe07 HTR_if status for AMC8 0xe08 HTR_if status for AMC9 0xe09 HTR_if status for AMC10 0xe0a HTR_if status for AMC11 0xe0b HTR_if status for AMC12 0xe0c HTR_if status bit 31-12 Always 0 bit 11-0 EventInfo_dav 0xe0d HTR_TTC_status bit 31-28 Always 0 bit 27-16 1 if corresponding HTR enabled and TTC locked bit 15-12 Always 0 bit 11-0 1 if corresponding HTR enabled and BC0 locked 0xe0f HTR_if status bit 31-8 Always 0 bit 7-0 evn_cnt 0xe10 HTR_if status bit 31-25 Always 0 bit 24-16 evn_ra bit 15-9 Always 0 bit 8-0 evn_wa 0xe11 HTR_if status bit 31-24 Always 0 bit 23-0 evn 0xe12 HTR_if status bit 31-25 Always 0 bit 24-16 CDF_ra bit 15-9 Always 0 bit 8-0 CDF_wa 0xe13 HTR_if status bit 31 Always 0 bit 30 evn_empty bit 29 event_avl bit 28 trailer_sent bit 27 ec_CDF_ra bit 26 sel_HTR_DATA bit 25 sel_Header bit 24-23 sel_evn bit 22 sel_CDF bit 21-19 sel_trailer bit 18-17 head_and_tail bit 16 SendEvent bit 15-12 first_amc bit 11-8 Next_HTR_a bit 7-4 Next_HTR bit 3-0 sel_HTR 0xe14 HTR_if status bit 31-0 fake_word_cnt 0xe15 HTR_if status bit 31-0 fake_header_cnt 0xe16 HTR_if status bit 31-0 fake_evt_cnt 0xe17 HTR_if status bit 31-0 fake_empty_cnt 0x4000-0x7fff memory read window spartan chip memory map: 0x0 reads: bit 23-16 SN number bit 15-0 T2 firmware version write: bit 0 general reset write: bit 4 start V6 reconfiguration write: bit 8 start both S6 and V6 reconfiguration 0x1 read/write read bit 0 FLASH busy write sends data stored in FLASH wbuf to FLASH memory chip bit 8-0 specifies number of (clocks/8 -1) to be sent to the FLASH memory (depends on the type of the FLASH command and number of bytes to be read or written) 0x2 read only (reads back what was written to V6 chip 0x3) bit 11-0 enables TTC clock and data to AMC modules 0x3 read only bit 31 if '1', virtex chip INIT_B is low bit 30 if '1', virtex chip DONE is low bit 23-0 configuration data CRC 0x4 bit 15-0 TTC event number register 0x5 bit 11-0 TTC L1 Bcnt register 0x6 bit 31-0 TTC L1 orbit count register 0x7 bit 7-0 TTC Bcnt error counter 0x8 bit 7-0 TTC single bit error counter 0x9 bit 7-0 TTC multi-bit error counter 0xa bit 7-0 T2 Serial Number 0xd read/write bit 11-0 enables TTC clock and data to AMC modules 0xe Spartan6 chip DNA bit 31-0 0xf bit 31-25 always reads 0 bit 24-0 Spartan6 chip DNA bit 56-32 0x1000 thru 0x107f read/write FLASH write buffer always write FLASH command(including FLASH address if any) to address 0x1000 for page write command, attach the write data starting at address 0x1001 you can read back what you have writen to the write buffer. 0x1080 thru 0x10ff read only FLASH read buffer you read whatever data are returned from the FLASH memory here initial test of AMC13 on the special test stand: connect the third SFP from top of the module under test to the top SFP of any AMC13 module in the uTCA crate and configure that module in the uTCA crate with AMC13T1EB.bit write 0xfff to register 3. read back from register 3 should be 0xfff. Then read from register 5, bit 27 thru 16 should be all 0. If any bit is non zero, corresponging AMC Tx/Rx has a proprblem. Connect TTC signal to the bottom SFP and you should be able to see TTC clock signals on the terminating resistors on the test stand. instructions about internal TTC clock and L1A generation To use internally generated TTC clock, use an optical fiber to loop back the bottom SFP transceiver optical signal. Bit 8 of register 1 must be set to '1' To use internally generated L1A, bit 2 of register 1 must be set to '1' To send a predetermined number of L1A, write 1 to bit 10 of register 0 To send continous L1A, write 1 to bit 26 of register 0, to termainate it, write 1 to bit 10 of register 0. write 1 of bit 0 of register 0 will also terminate it. when in internal L1A mode, you can write 1 to bit 11 of register 0 to send an reset event number command through TTC, or write 1 to bit 12 to reset the orbit count TTC command. You can send both at the same time. A general reset, i.e. write 1 to bit 0 of register 0 will reset both too among other things. register 0x1c is used to configure internal L1A generation: N is contents of bit 15-0 bit 31 and 30 is used to chose the type of L1A: if "00", L1A is generated every N+1 orbits at BX = 500 if "10", L1A is generated every N+1 BX, trigger rules apply when N < 63 if "11", L1A is generated at random spacing, trigger rules apply. The average frequency is 2N Bit 29-28 determines how many trigger rules are enforced: "00": all four rules "01": all except rule 4 "10": rules 1 and 2 "11": only rule 1 bit 27-16 number of L1A sent in a burst is its countents + 1 To run memory test, first write 0 to register 0x1, then write 1 to register0x0, write either 0x10 or 0x50 to register 0x1 to start the test.