July 03 2014 T1 version 0x1001 and T2 version 0x21 New version can generate random length events. now there are two length size registers: If they are set to equal the length is fixed as before. If they are unequal, they represent the upper and lower limits of the length. register 0x1a is used as the seed of random number generator. This ensures sequence can be reproduced. If the seed is set to all 1, which is not legal, the sequence is complete random and can not be reproduced. The above three registers are at 0x18, 0x19 and 0x1a. notice that the pattern register has been moved to 0x1b now May. 06 2014 T1 version 0x1000 and T2 version 0x20 This version is used to emulate an AMC module for AMC13 test. Its usage is very simple: The test function is enabled by default(bit 7 of register 1 set to 1) write to register 0x18 to set AMC payload length in unit of 64 bit word.(AMC event header/trailer not included) write 1 to register 0 to reset it module is ready now You can also use register 1 to set its TTS signal and check it by reading amc13xg registers 0xe1a, 0xe1b and 0xe1c or you can also check it at amc13xg's TTS output Spartan chip default IP address 192.168.1.(254 - 2*SN) T1 chip default IP address 192.168.1.(255 - 2*SN) T1 chip memory map: 0x0 read/write write: bit 0 general reset(ddr3 memory controller not encluded) write: bit 1 counter reset write: bit 5 reset ddr3 memory controller write: bit 10 if bit 10 reads '0', it sends a burst of local L1A if bit 10 reads '1', it only resets it to '0' write: bit 11 sends event number reset thru TTC when in local L1A mode write: bit 12 sends orbut number reset thru TTC when in local L1A mode write: bit 26 set continous local L1A(setup with register 0x1c) read: 0 reads '1' when any of the enabled SFP ports is down read: 1 monitor buffer overflow read: 2 monitor buffer full read: 3 monitor buffer empty read: 5 TTC not ready read: 6 TTC bcnt error read: 7 TTC single bit error read: 8 TTC multi-bit error read: 9 TTC sync lost(L1A buffer overflow) read: 10 continous local L1A on(setup with register 0x1c) read: 13 L1A overflow warning read: 15 if 0, DDR memory reset done read: bit 31-24 T1 board SN 0x1 read/write bit 31-16 read only Virtex firmware version bit 15 not used bit 14 if '1', monitor buffer full will stop event builder bit 13 if '1', send all data to downstream when ttc reset is received. if '0', flush all data when ttc reset is received. bit 12 if '1', TTS outputs correspond to bits 3-0 of register 0x19 instead of TTS state when run bit(bit 0) is '1', this bit will be forced to '0' bit 11-9 not used bit 8 if '1', TTS output is TTC signal output(you have to set bit 2 also to use this feature) bit 7 if '1', generate fake event upon receiving L1A bit 6 if '0', memory test uses 64bit PRBS. If '1', uses 32 bit sequencial numbers. bit 5 '1' enables non-standard TTCrx broadcast commands bit 4 '1' enables memory self test bit 3 if '1', pauses event building. For debugging only bit 2 if '1', uses internally generated L1A bit 1 '1' enables DAQLSC bit 0 run mode offset 0x7 AMC board ID R/W read: bit 31-16 always '0' bit 15-0 board ID write: bit 31-16 not used bit 15-0 board ID offset 0x18 payload size in 64bit words of faked HTR event R/W read: bit 31-18 always '0' bit 17-0 payload size write: bit 31-18 not used bit 17-0 payload size in 64bit words of faked HTR event(default 0x400) offset 0x19 second payload size in 64bit words of faked HTR event R/W read: bit 31-18 always '0' bit 17-0 payload size write: bit 31-18 not used bit 17-0 payload size in 64bit words of faked HTR event(default 0x400) offset 0x1a payload size random number seed R/W read: bit 31-18 always '0' bit 17-0 random number seed write: bit 31-18 not used bit 17-0 random number seed(defalt all one) offset 0x1b AMC TTS pattern register R/W read: bit 31-4 always '0' bit 3-0 TTS pattern write: bit 31-4 always '0' bit 3-0 TTS pattern